FREQUENTLY ASKED 100+

BACK-END INTERVIEW
QUESTIONS
MUST HAVE INTERVIEW HANDBOOK
1. What are the key steps in the Physical Design
flow?
Answer:
Floorplanning: Define the chip size, block
locations, IO pins.
Power Planning: Create power grids (VDD/VSS).
Placement: Place standard cells.
Clock Tree Synthesis (CTS): Distribute the clock
uniformly.
Routing: Connect signals and clocks.
Physical Verification: DRC/LVS checks.
Static Timing Analysis (STA): Verify timing
closure.
IR Drop & EM Analysis: Power integrity checks.
Signoff: Final checks before tape-out.

2. What is congestion in physical design? How do

you handle it?
Answer:
Congestion happens when routing resources are
insufficient for the required nets in a region.
Causes: High cell density, excessive fanout,
poor floorplanning.
Fixes:
Spread cells during placement.
Use blockage or routing guides.
3. What is antenna effect? How do you fix it?
Answer:
Antenna Effect occurs during fabrication when
long metal wires accumulate charge and
damage gates.
Fixes:
Antenna Diode Insertion
Layer Jumping (Route signal through higher
metal layers)
Metal Jogging

4. What is IR Drop? How do you reduce it?

Answer:
IR Drop is the voltage drop due to resistance in
power lines.
Types:
Static IR Drop: Due to average current.
Dynamic IR Drop: Due to switching activity.
Solutions:
Wider power grids.
More vias.
Decaps.
Power grid optimization.
5. Explain the importance of CTS (Clock Tree
Synthesis).

Answer:
Distributes the clock signal to all sequential
elements.
Targets:
Minimize skew (difference in arrival time)
Minimize insertion delay
Balance clock tree
Techniques:
H-tree, X-tree structures
Buffer insertion
Gating for power saving

6. What is DRC and LVS?

Answer:
DRC (Design Rule Check):
Checks if layout obeys foundry rules
(spacing, width, enclosure).
LVS (Layout vs Schematic):
Ensures the layout is electrically equivalent
to schematic (netlist vs layout comparison).
7. How do you fix setup timing violations?
Answer:
Add buffers in clock path (to delay clock).
Size-up driving cells in data path.
Reduce logic depth.
Use multi-cycle paths if valid.
Apply low Vt cells.

8. How do you fix hold timing violations?

Answer:
Add buffers in data path to increase delay.
Reduce delay in clock path.
Use delay cells.
No margin for increasing clock delay here
(opposite of setup).

9. What is Electromigration (EM)?

Answer:
Gradual movement of metal atoms due to high
current density.
Leads to open/short circuits over time.
Fixed by:
Increasing wire width.
Using redundant vias.
Limiting current density per metal layer.
10. What is Multi-Corner Multi-Mode (MCMM)
Analysis and why is it important?
Answer:
MCMM enables analyzing design behavior
across multiple PVT corners and functional
modes simultaneously.
Corners: e.g., SS@125°C, TT@25°C, FF@-40°C
Modes: Functional, Scan, Test, Sleep
Importance:
Ensures robustness across all real-world
conditions.
Avoids timing closure issues late in the
tape-out phase.

11. Explain the ECO (Engineering Change Order)

Flow in physical design.
Answer:
ECOs are changes after signoff or near-tapeout
due to: Timing fixes, Functional bugs, Late RTL
changes
Types:
Functional ECO: logic edits using spare
cells.
Timing ECO: buffer insertion/removal,
sizing.
12. What are the techniques used in Low Power
Physical Design?
Answer:
Multi-Vt cells: Balance power and performance.
Power Gating: Shut down unused blocks.
Clock Gating: Disable unnecessary clock
toggling.
Multi-VDD Domains: Different blocks operate at
different voltages.
Placement-aware optimization: Reduce
wirelength = reduce dynamic power.

13. What are Metal Fill and Dummy Fill? Why are
they used?
Answer:
Used to maintain uniform metal density for
Chemical Mechanical Polishing (CMP).
Dummy Fill: non-functional metal added for
uniformity.
Rules depend on:
Min/Max metal density per layer
Fill exclusion near sensitive nets
Side-effects:
Increased capacitance (can be shielded or
excluded)
Needs post-fill timing re-analysis.
14. How do you handle Clock Skew and Clock
Latency during CTS?
Answer:
Skew: Arrival time difference between clocked
elements.
Latency: Delay from clock source to a flip-flop.
Techniques to handle:
Balancing paths with buffers/inverters
Clock gating considerations
Avoid clock gate race-through
Use of useful skew to fix timing

15. What are false paths and multi-cycle paths?

How are they handled in STA?
Answer:
False Paths: Do not affect functionality.
Declared to STA to avoid fixing them.
Multi-Cycle Paths (MCP): Valid data transfer
spans multiple clock cycles.
Declared using set_false_path,
set_multicycle_path constraints.
Used in:
Synchronizers
Asynchronous interfaces
Deep pipeline paths
16. How do you do signoff for physical design?
What reports must be clean?
Answer:
Final Signoff Steps:
STA (with signoff tool like PrimeTime)
IR Drop & EM Analysis
(RedHawk/Totem/Voltus)
DRC/LVS (Calibre, Pegasus)
Timing reports (setup/hold clean)
Power analysis
Antenna clean
All reports (timing, power, physical) must pass
foundry signoff criteria.

17. How do you debug a negative slack path that

violates both setup and hold?
Answer:
This is a rare case and often due to incorrect
constraints or clock definition.
Steps:
1. Check create_clock definitions – incorrect period
or waveform?
2. Inspect set_input_delay / set_output_delay.
3. Verify if it's an asynchronous path – use
set_false_path.
4. Re-characterize cells or check wrong library usage.
18. What are the challenges in hierarchical physical
design flows?
Answer:
Challenges:
Interface congestion and block pin
planning.
Clock synchronization across blocks.
Solutions:
Use physical abstract models (LEF, TLU+).
Apply interface optimization (bus
compaction, soft macro grouping).

19. How do you analyze and reduce dynamic IR

drop in a design?
Answer:
Use vector-based or vectorless IR drop analysis
tools.
Causes: High toggle rate, poor decap placement,
long power paths.
Reductions:
Insert decap cells near hotspots.
Optimize placement to spread switching logic.
Balance clock gating regions.
Improve power routing metal width and via
density.
20. What is a useful skew and how is it intentionally
used in design?
Answer:
Useful Skew: Intentionally delaying clock at FFs
to improve setup or hold margins.
Example:
If data arrives late, delay capture clock to
fix setup.
If data is fast, advance capture clock to fix
hold.
Used during CTS optimization with constraints
like set_clock_latency -source.

21. How do you perform cell legalization and what

issues can arise?
Answer:
Cell Legalization aligns placed cells to legal sites
without overlap.
Done post-placement and post-ECO.
Issues:
Overlap
Cell shifting causing timing degradation
Track alignment violations
Ensure utilization below 70–75% before placement
to ease legalization.
22. What is multi-bit flop merging? Why is it used?
Answer:
Combine 2 or 4 1-bit flops into a single multi-
bit flop.
Benefits:
Less routing congestion
Lower clock tree power
Better timing correlation
Must ensure:
Clock pin compatibility
No excessive timing skew on individual bits

23. How do you handle clock domain crossing (CDC)

at physical level?
Answer:
Ensure robust synchronizers:
2-FF sync for control signals
FIFO-based or handshake logic for data
Placement Rules:
Synchronizer flops close together
Avoid long inter-domain nets
Analyze with CDC tools (e.g., SpyGlass CDC)
24. What is double patterning, and how does it
impact layout design?
Answer:
Required in sub-20nm nodes for
manufacturing.
Double Patterning (DPT) splits a layer into 2
masks to avoid lithography issues.
Impact:
Design rule complexity (coloring)
DRC errors like odd cycle violations
Need color-aware routing and placement
Tools: Calibre DRC+, color-aware P&R tools

25. How is Metal Slotting handled and what are its

implications?
Answer:
Used in wide metal wires (e.g., power rails) to
reduce mechanical stress and CMP dishing.
Slotting is patterning wide wires with slots or
holes.
Must follow foundry rules for spacing, density,
and proximity.
Can impact EM/IR and shielding if not properly
managed.
26. What is FinFET, and how does it change
physical design constraints?
Answer:
FinFET is a 3D transistor with vertical fins,
replacing planar CMOS.
PD Implications:
Discretized width (number of fins per
device, e.g., 1, 2, 3... no in-between).
Cell libraries are finned, limiting drive
strength granularity.
Local interconnect layers (LI) introduced.
Tighter DRC (spacing, coloring).
Pin access is complex due to fin
quantization.

27. What is the role of LEF/DEF in physical design?

Answer:
LEF (Library Exchange Format):
Abstract view of cells (pins, size, blockages)
for placement/routing.
DEF (Design Exchange Format):
Stores instance placement, nets, routing
info for the entire chip.
LEF + DEF → used by P&R tools for standard
cell layout and design connectivity.
28. What is RC extraction, and how accurate must it
be at signoff?
Answer:
RC Extraction estimates resistance (R) and
capacitance (C) of interconnects.
Must be accurate because:
Impacts timing (delay), power, and SI.
Types:
Pre-layout: based on estimation (wire load
models).
Post-route: uses parasitic extraction tools
(SPEF/RCDEX).
At signoff:
Use field solver-based tools (e.g., StarRC)
with metal fill, coupling, and variation.

29. How does signal shielding help reduce crosstalk

and how is it implemented?
Answer:
Shielding places GND/VDD lines adjacent to
sensitive nets while its benefits are:
Absorbs coupling capacitance
Protects timing-critical or clock nets
Implemented by:
Manually routing critical nets with shielding
Tool directives (routeShield, netClass)
30. What is floorplan entropy and how does it
affect design convergence?
Answer:
Entropy quantifies cell distribution randomness
in a floorplan.
High entropy → Poor clustering → Higher
congestion.
Metrics:
Pin density
Macro placement overlap
Net cut & HPWL
Lower entropy → Easier placement, timing
convergence.

31. How do you automate ECO flow using scripts?

Answer:
Use TCL or Python in tools like ICC2, Innovus,
or PrimeECO.
Steps:
a. Identify ECO cells/spares
b. Logic mapping (change_port, connect_net)
c. Legalize + re-route + re-ECO STA
d. Generate updated DEF/Verilog
Advanced:
Build ECO cell database, auto-buffering
templates, placement constraints.
32. What is physical-aware synthesis?
Answer:
Logic synthesis with physical constraints in
mind.
Reduces timing surprises post-P&R.
Uses:
Floorplan info (congestion maps, placement
regions)
Wireload & parasitic estimation
Tools: Design Compiler Graphical, Genus iSpatial.
Result: Better QoR and fewer ECOs.

33. How does high-frequency design impact

physical design flow?

Answer:
Short timing windows → Zero margin for delay.
Impacts:
Floorplan: Minimize long interconnects.
Placement: Path delay optimization.
Clock: Low skew, multi-stage CTS.
STA: Tight derates, AOCV/POCV.
Requires multiple optimization loops, detailed
SI/IR handling, and redundant buffering.
34. What is Design for Manufacturability (DFM), and
how is it ensured in the PD flow?

Answer:
DFM improves the yield, reliability, and
robustness of ICs by making the design more
fabrication-friendly.
Key DFM Techniques:
Litho-aware layout (hotspot detection)
Dummy metal fill optimization
Via redundancy insertion
CMP-aware metal slotting

35. What are Antenna Violations and how are they

fixed?

Answer:
Occur during fabrication when long metal nets
accumulate charge and damage the gate oxide.
Common during routing before the gate is
protected.
Fixes:
Antenna diode insertion
Layer jumping
Route shielding
Verified through Antenna Rule Check (ARC)
using foundry decks.
36. How do you ensure physical design is PPA-
optimized?

Answer:
PPA = Power, Performance, Area
Optimized through:
Power: Multi-Vt cells, clock gating, min
switching logic.
Performance: Timing closure, minimal path
delay, less skew.
Area: Optimal cell utilization, floorplan packing,
multi-bit flops.
Use PPA reports from Innovus/ICC2 and
prioritize paths based on slack-weighted
criticality.

37. How do you handle hierarchical vs flat STA in

large SoCs?

Answer:
Hierarchical STA:
Faster, uses abstract models (.lib, .spf)
May miss interface glitches/timing bugs.
Flat STA:
Full netlist + parasitics = accurate.
Heavy runtime and memory.
Hybrid approach: block-level signoff with top-
level black-box glue logic.
38. What are TLU+ and ITF files in timing signoff?

Answer:
TLU+ (Table Lookup +): used in Cadence tools
for RC modeling.
Contains resistance, capacitance tables
across layers, width, spacing.
ITF (Interconnect Technology File): used by
Synopsys for interconnect modeling.
Inputs to RC extraction engines.
Both depend on process tech node and
foundry.

39. What is IR-aware placement and why is it

important?

Answer:
Places cells based on IR drop profile to prevent
hotspots.
Importance:
Prevents timing degradation due to local
voltage drops.
Ensures long-term EM reliability.
Achieved using:
Floorplan-aware IR maps
Power domain constraints
Tools like RedHawk integration into
Innovus/ICC2
40. What is ECO leakage, and how do you avoid it?

Answer:
Occurs when ECO introduces extra paths,
glitches, or wrong functionality due to poor net
rewiring.
Avoid by:
ECO-aware logic synthesis tools
Formal verification post-ECO (Conformal
ECO/Spyglass)
Proper mapping of spares and gate types
Best practice: always re-run STA and functional
checks post-ECO.

41. How do you prepare a design for tapeout

handoff? What checklist is followed?

Answer:
Tapeout Checklist:
DRC/LVS clean (Calibre)
STA: Setup/Hold, SI, MCMM clean
(PrimeTime/Tempus)
Antenna violations fixed
EM/IR validated (RedHawk/Totem)
Power integrity checks passed
42. What are Process Corners and how do they
impact physical design signoff?

Answer:
Process Corners represent variations in
manufacturing, modeled as:
TT (Typical-Typical), SS, FF, SF, FS
Impact:
Different corners yield different timing
paths (e.g., FF is fastest, SS is slowest).
Signoff includes:
Timing at worst-case PVT (Process-Voltage-
Temperature)
Aging analysis at high-temp corners (e.g.,
125°C)

43. How is hierarchical IP reused in multi-die SoCs

or chiplets?

Answer:
Reuse includes:
Abstract views: .lef/.lib for P&R
Power intent: UPF files for integration
Ensure:
Proper interface isolation
Glue logic optimization
Black-box verification at SoC level
44. How do you prepare a design for foundry
tapeout submission?

Answer:
Final deliverables:
GDSII, LEF, Liberty (.lib), DEF
Signoff reports: DRC, LVS, STA, IR, SI
Fill layers + MEBES conversion
Use foundry signoff decks (e.g., TSMC,
Samsung)
Must pass PV, DFM, and tapeout readiness
reviews by CAD team

45. How is low-power intent handled in physical

design?

Answer:
Defined via UPF (Unified Power Format) or CPF.
Flow includes:
Level shifters between voltage domains
Isolation cells for power-down domains
Retention flops for saving states
Power gating using switch cells
Tools support power-aware PnR, CTS, STA, and
IR-drop validation.
46. What are the challenges of integrating hard
macros/IPs in floorplanning?

Answer:
Challenges:
Blockage handling (cell, routing)
Power strap alignment
Timing closure across macro interfaces
Macro orient/placement for routability
Best practices:
Keep I/O ports on same side of interface
Use channels between macros

47. How do you ensure clean timing across

asynchronous clock domains?

Answer:
Use:
Synchronizers (2/3-stage FFs), CDC FIFOs
Handshake circuits
Tools: CDC verification tools (e.g., Spyglass
CDC, Questa CDC)
Static Timing:
No setup/hold checks across async
boundaries
Mark paths as false paths with
set_false_path directives
48. What are filler cells and why are they inserted?
Answer:
Filler cells fill empty spaces between standard
cells.
Purpose:
Maintain well continuity
Ensure metal layer density
Avoid DRC and antenna violations

49. How do you handle last-minute ECOs before

tapeout?

Answer:
Types:
Functional ECOs: fix RTL bugs
Timing ECOs: buffer insertion/removal
Flow:
Use ECO spare gates and change_gate,
connect_net flows
Run incremental STA, DRC/LVS
Formal equivalence check (e.g., Conformal
ECO)
50. How do you ensure IR-safe design for power
gating domains?

Answer:
Use power switches (header/footer) to isolate
power domains.
Ensure:
Adequate width of switch gates
Local decap insertion in gated domain
Separate power grid routing with M1-M4
meshes

51. What are post-silicon debug hooks, and how are

they integrated into layout?
Answer:
Hooks added for observability and
controllability:
Scan chains
JTAG interfaces
Spare muxes or probe pads
Floorplan guidelines:
Reserve routing channels
Isolate debug pads from critical paths
52. What is retiming, and how is it used in physical
design?

Answer:
Retiming = Moving flip-flops across
combinational logic to optimize timing.
Can improve:
Critical path delays
Setup/hold margin
Done at:
RTL (with tools like Design Compiler
optimize_registers)
Physical level (timing-driven tools like ICC2
or Fusion Compiler)

53. How is ESD (Electrostatic Discharge) protection

achieved in chip design?
Answer:
Key Techniques:
I/O clamp cells (diodes, SCRs)
Power clamps (triggered by high voltage
events)
Well tie-downs
Backend role:
Ensure ESD paths are short and wide (low
impedance)
Place guard rings, add ESD-safe routing
54. What are antenna violations and how are they
fixed?

Answer:
Occur when metal wire area is large before gate
is connected → may accumulate charge and
damage gate oxide.
Detected during DRC
Fixes:
Add antenna diodes
Use layer jump (via to higher metal early)
Break net with deferred connect

55. What is DFT-aware physical design?

Answer:
Includes:
Scan chain optimization (route-length,
congestion-aware placement)
Test point insertion (via low toggle FFs)
MBIST and BIST controller integration
Backend ensures:
Proper routing of scan_in/out
Placement of test logic with low impact on
PPA
56. How are multiple power domains handled in
floorplanning and signoff?

Answer:
Floorplanning:
Isolate domains physically
Route dedicated power grids
Insert level shifters, isolation cells
Signoff:
Must verify power intent (UPF) alignment
Run power-aware STA across domain
boundaries

57. What are Non-Default Rules (NDRs) and why are

they used?
Answer:
NDRs override default routing rules:
Wider/Thicker metal
More spacing
Specific layer constraints
Use Cases:
High-speed clocks
EM-prone nets (VDD/GND, high fanout)
Shielding sensitive nets
58. How are chiplets integrated in backend design?
Answer:
Chiplets = small dies with defined functions
connected via interposers or bridges.
Challenges:
Floorplan alignment
Bump placement, TSV alignment
Power delivery & IR consistency
Backend role:
Generate physical abstracts (LEF + bump
map)
Ensure IO ring compatibility
Cross-chip clock domain handling

59. What are late-stage LVS issues and how do you

debug them quickly?
Answer:
Common late-stage LVS issues:
Mismatch in pin names / labels
Shorts/missing connects due to ECOs
Incorrect PG net connections
Debug tips:
Use highlightDiff commands in Calibre
Extract GDS-only netlists for comparison
Run incremental LVS on suspect blocks
60. What are the best practices for metal density
and CMP compliance?
Answer:
Metal fill needed for CMP uniformity
Foundry rules:
Metal density between 30–70% per window
(e.g., 100um x 100um)
Uniform fill across layers
Strategy:
Use net-aware fill on signal nets
Avoid fill in critical signal regions
Re-run timing + SI after fill

61. What are timing ECO spare cells and how are
they used?
Answer:
Spare cells = pre-instantiated logic gates (INV,
AND, OR, BUF) placed for future use.
Timing ECO flow:
Use connect_net, change_cell, or tool-
driven ECO flows
Stitch new logic using existing spare gates
Benefits:
Avoids full re-PnR
Reduces tapeout risk & delay
62. How is IR-drop-aware Clock Tree Synthesis
performed?
Answer:
Conventional CTS may ignore voltage drop →
timing issues
IR-aware CTS:
Analyzes voltage at sink locations
Avoids buffer placement in IR-critical
regions
Tools: PrimeCTS, Innovus, Fusion Compiler
support IR-aware clock optimization.

63. What is RDL (Redistribution Layer) and where is

it used?
Answer:
RDL = Additional metal layer(s) added on top of
chip to reroute signals to new bump locations.
Used in:
Flip-chip designs
Fan-out wafer-level packaging (FOWLP)
Backend responsibilities:
Follow foundry RDL DRC
Place micro-bumps and TSVs
Connect RDL nets to die bumps, I/Os, ESD
structures
64. How does machine learning assist in physical
design closure?
Answer:
ML in PD:
Predict congestion hotspots
Estimate timing/IR drop early
Optimize placement and power grid
Tools: Synopsys [Link], Cadence Cerebrus
Benefits:
Faster closure (20–30% TAT reduction)
Better PPA convergence

65. What are the steps to debug level shifter

placement issues?
Answer:
Symptoms:
Missing level shifters
Wrong domain assignment
LS placed far → long delay
Debug:
Check UPF/CPF domain definition
Use report_level_shifter and
verify_power_domain
Visualize using voltage-aware GUI
66. How are TSVs used in 3D ICs and what are
backend challenges?
Answer:
TSV (Through-Silicon Via): Vertical
interconnects connecting stacked dies.
Backend concerns:
Placement blockages
DRC compliance (minimum keep-out zone)
Alignment with micro-bumps
Must handle:
Thermal hotspot due to TSV density
Crosstalk between vertical nets

67. What is thermal-aware floorplanning?

Answer:
Places hot modules apart and aligns them with
thermal vias / heat sinks
Uses:
Activity maps, IR/Temp sensors
Thermal analysis tools (e.g., ANSYS,
HotSpot)
Techniques:
Spread macros
Align PG network with thermal sinks
Avoid hotspots near seal rings or IO pads
68. What is variation-aware signoff and why is it
critical at advanced nodes?
Answer:
At 7nm and below, process and voltage
variations significantly impact timing/yield.
Variation-aware STA includes:
On-chip variation (OCV)
AOCV (Advanced OCV)
LVF (Liberty Variation Format): includes
delay distributions
Tools simulate worst-case + statistical delays
Enables more accurate guardbands for timing
closure

69. How are ECOs handled in UPF-based designs?

Answer:
Late-stage RTL or netlist ECOs must maintain
power intent.
Risks:
Broken isolation/retention
Mismatched supply nets
Steps:
Regenerate merged UPF
Verify with check_power_domain
Re-run power-aware STA + LVS
70. How do you verify physical IP (e.g., SerDes, DDR
PHY) integration in a SoC?
Answer:
Checks:
Pin mapping (macro vs. SoC top)
PG alignment (e.g., AVDD/DVDD isolation)
Placement according to electrical specs
(near IO ring, shielding)
Verify:
TCL-based DRC/LVS
Clock domain alignment between PHY and
controller

71. How does FinFET architecture impact backend

layout and routing?

Answer:
Key FinFET Constraints:
Fixed transistor width in terms of number
of fins
Restricted cell height (e.g., 9-track, 7.5-
track cells)
Backend implications:
Routing is layer-aware: lower metals are
unidirectional
Placement must honor fin pitch
72. What is CPPR and how does it improve timing
accuracy?
Answer:
CPPR = Common Path Pessimism Removal
In traditional STA:
Setup and hold analysis assume
independent clock paths, adding pessimism
CPPR corrects this by removing the common
portion of the clock path delay between launch
and capture FFs
Improves:
Timing accuracy
ECO timing margin prediction

73. What is DFM-aware placement and routing?

Answer:
Design for Manufacturability (DFM) rules help
improve yield and reliability
Backend actions:
Avoid line-end spacing violations
Use dummy vias/fills in sparse areas
Use routing redundancy (e.g., redundant
vias)
Enable DFM scoring engines
74. What are the types of metal fill and how do
they affect timing?
Answer:
Types:
Dummy Fill: Non-functional metal added
for CMP uniformity
Net-aware Fill: Connected to power or
shield nets
Effects:
Changes capacitance of nearby signal nets
May degrade timing/SI

75. How do you handle clock domain crossing in

backend ?
Answer:
Must ensure:
Data from domain A to domain B is
synchronized properly
Checks:
Use CDC tools (e.g., SpyGlass CDC, Questa
CDC)
Add synchronizer cells in placement
Place synchronizers close together to avoid
glitch
76. What is IR drop recovery flow before signoff?
Answer:
If static/dynamic IR drop exceeds threshold:
Reinforce metal widths or use PG straps
Add power vias
Improve PG tap spacing
Floorplan stage: use power stripes
Post-route: enable IR-aware ECO, use IR-safe
buffer insertions
Final step: Re-run RedHawk/Voltus → confirm
IR within budget

77. What are EM-aware signoff practices for high

current nets?
Answer:
Electromigration (EM) is current-induced metal
migration → causes failures
EM-safe routing involves:
Wider metals for PG nets, clock nets
Check current density per layer
EM analysis tools:
Ansys RedHawk
Synopsys PrimeRail
78. What is a die seal ring and how is it designed?
Answer:
Seal ring = protective ring around the active die
area
Includes:
Guard rings, filler cells
ESD clamps, GDS markers
Design must follow:
Foundry edge rules
Include stress buffer structures

79. What is a PVT-aware timing signoff?

Answer:
PVT = Process, Voltage, Temperature
Timing closure must be met for:
All process corners (e.g., ss, ff, typical)
All voltages (min/max)
All temperatures (-40°C to 125°C)
Tools like PrimeTime or Tempus run multi-
corner, multi-mode (MCMM) analysis
Also check derates and variation models across
PVTs
80. What is the difference between 2.5D and 3D IC
packaging from a backend design perspective?
Answer:
2.5D IC:
Dies placed on an interposer
Easier thermal management
More area → lower density
3D IC:
Dies stacked vertically with TSVs
Needs TSV planning, alignment markers
Higher density → complex IR drop and
heat
81. How is IR-drop-aware cell placement
performed?
Answer:
Goal: Place cells in regions with reliable power
delivery
Techniques:
Use IR-drop maps from Voltus/RedHawk
Avoid placing near PG weak spots
IR-aware placement during initial &
legalization stage
Bonus: Improves post-route IR convergence and
reduces PG ECO.
83. What is a dummy cell and why is it added in
the layout?
Answer:
Used to:
Maintain pattern density uniformity
Avoid lithography hotspots
Help fill gaps between standard cells
Types:
Non-functional filler cells
Well tap cells / Decap cells

84. How do you debug hold violations in post-route

STA?
Answer:
Root causes:
Short data paths, excessive derating, clock
uncertainty
Fixes:
Add delay chains / buffers
Reduce clock skew
Modify clock tree buffering
Tools: PrimeTime, Tempus (setup and hold
fixing modes)
Best practice: Run timing ECOs with hold-first
strategy at 5nm and below.
85. What is thermal throttling and how does it
affect floorplan and signoff?
Answer:
Thermal throttling = Reducing performance due
to excessive die temperature
Causes:
Poor thermal conduction
Hot macros close together
Backend actions:
Spread hotspots apart
Insert thermal vias, TSVs
Rerun thermal-aware analysis before
signoff
86. How are chiplet interfaces handled in multi-die
backend integration?
Answer:
Interface examples: BoW, UCIe, AIB, XSR
Backend challenges:
Align micro-bumps across dies
Co-design RDL + TSV map
Ensure supply isolation between chiplets
Must pass:
D2D LVS
Timing correlation between chiplet timing
arcs
Signal integrity at high-speed die interfaces
87. What are electromigration-aware via insertion
best practices?
Answer:
Add parallel vias on high current nets
Use:
Via arrays (VIA12, VIA23)
Double via strategy in PG routing
Tools check:
Via resistance
Current density per via

88. How does ML help in IR/congestion prediction

in backend flow?
Answer:
AI/ML engines like [Link], Cerebrus:
Predict routing congestion hotspots
Forecast IR-drop based on early placement
Benefits:
Minimize rework
Avoid over-buffering or area bloat
Example: Use ML during placement trials to
converge on best IR-safe floorplan
89. What are the key ISO 26262 compliance
requirements for automotive physical design?
Answer:
ISO 26262 = Functional Safety in Automotive
Physical Design must ensure:
Redundant power domains
Safe clock trees (glitch-free CTS)
Split channel routing for ASIL-D blocks
DRC/LVS + FMEDA-aware CDC
Verified with:
TCL-based LVS
UPF safety path verification

90. What is final signoff checklist for 3DIC or

chiplet-based SoC?
Answer:
Per-die DRC/LVS clean
TSV/IO alignment check
Co-simulation of die-to-die delay
Inter-die IR/thermal maps verified
Micro-bump vs RDL maps validated
Redundancy nets inserted
Packaging parasitics extracted and STA updated
Final GDS + OASIS + interposer DEF delivered
91. What is the UCIe standard and its impact on
backend?
Answer:
UCIe (Universal Chiplet Interconnect Express)
standardizes die-to-die interfaces. Backend must
handle:
Micro-bump floorplanning
Routing across bridges/interposers
Matching latency across links
EM/IR analysis per chiplet
Used in advanced 3D SoC and chiplet
ecosystems.

92. What is zero-trust physical signoff in secure

chip design?
Answer:
In security-sensitive chips, zero-trust signoff
means:
No block is assumed to be inherently
“trusted”
Insert obfuscation cells, camouflaged logic,
or dummy vias
Protect layout from reverse engineering
Tools:
Formal equivalence after obfuscation
Split manufacturing strategy (FEOL vs BEOL
separation)
93. How do you correlate timing between synthesis
and signoff tools?
Answer:
Match timing libraries, derates, wire-load
models
Use same OCV and PVT setup
Cross-check netlist versions
Run report_timing -path_type full_clock in both
tools
Correlation ensures valid signoff after RTL
handoff.

94. How do you correlate timing between chiplets

in a 3DIC system?
Answer:
Each chiplet may use:
Different PVT corners
Different clock sources
Solution:
Run Inter-die timing simulations
Align launch/capture flops across dies
Use package parasitics in SDF for STA
95. What is physical-aware RTL synthesis?
Answer:
Incorporates placement and congestion
estimates into RTL synthesis
Reduces timing closure iterations
Tools like Synopsys Design Compiler Graphical
or Genus iSpatial support it
Benefits: Fewer hold fixes, better cell
utilization.
96. What are best practices for ESD-aware layout in
backend?
Answer:
Add diodes, clamps, and discharge paths near
I/O cells
Use thick metals and multiple vias for ESD
discharge
Ensure ESD discharge path has minimal
resistance
Place ESD cells in dedicated ring outside core
97. How do you handle skew optimization in high-
frequency designs (3+ GHz)?
Answer:
Use low insertion delay buffers
Enable useful skewing
Place clock tree closer to endpoints
Avoid high fanout buffers on global nets
Run clock_opt -skew_opt_mode or equivalent
for fine-tuning

98. How is clock gating integrated in backend flow?

Answer:
Synthesis inserts gating logic (AND, MUX)
Backend must preserve placement constraints
Clock tree should drive gated and ungated
domains with correct skew
CTS tools treat clock gating cells as stop points
or clock dividers depending on config

99. What is ISO 21434 and how does it affect

backend design?
Answer:
ISO 21434 = cybersecurity for automotive
electronics
Backend considerations:
Data bus shielding
Tamper-proof layout constraints
100. How does AI help in signoff ECO closure?
Answer:
ML models analyze:
Where violations are most likely
Which buffer or cell size will fix timing
Example tools:
Cadence Cerebrus, Synopsys [Link]
Benefits:
Faster timing closure
Reduce iterations in PnR and signoff loops

101. How do you analyze power-aware placement in

AI/ML cores?
Answer:
Group cells by:
Power domain
Activity factor
Thermal profile
Ensure:
Minimal IR drop near MAC units
Optimal voltage island partitioning
102. What are the key metrics for backend PPA
optimization in AI accelerators?
Answer:
PPA = Power, Performance, Area
For AI/ML:
Performance = MAC throughput
Power = thermal density vs leakage
Area = reuse-based datapaths
Tools provide cost functions to optimize:
PPA_cost = w1×delay + w2×power + w3×area

103. What is the role of ML-based congestion

predictors in early-stage backend?
Answer:
During early floorplan:
ML models forecast hotspots based on
macro locations, netlist stats
Helps:
Reduce congestion loops later
Decide optimal placement region
Tools: AI-powered PnR engines ([Link],
Synopsys Fusion)
104. How do you ensure asynchronous boundary
safety in multi-die designs?
Answer:
Insert:
Dual flop synchronizers across domains
Handshake logic or FIFOs for data paths
Backend ensures:
Minimum skew paths
Synchronizers physically grouped &
shielded
Check with CDC tools across dies

105. What are white spaces used for in backend

layout?
Answer:
White space = unused area intentionally left
Used for:
Decap cell insertion
Hold-fixing buffers
Routing detours or fill insertion
Strategically added in:
Clock sinks
PG-sensitive areas
 Excellence in World class
VLSI Training & Placements

Do follow for updates & enquires

+91- 9182280927