NARAYANA ENGINEERING COLLEGE:GUDUR
20EC2011 Digital Design using HDL R2020
Semester Hours / Week Total hrs Credit Max Marks
L T P C CIE SEE TOTAL
VI 3 0 0 48 3 40 60 100
Pre-requisite: Concepts of Switching Theory and Logic Design.
Course Objectives:
1 To describe, design, and simulate digital circuits using the Verilog Hardware description language.
2 To understand behavioural and RTL modelling of digital circuits
3 To verify timing constraints of digital circuits, through the Verilog HDL
4 To synthesize, digital circuits designs on a development board
5 To Implement digital circuits on a development board
Course Outcomes: After successful completion of the course, the student will be able to:
CO 1 Interpret digital design flow used in chip design Flow. (BL-2)
CO 2 Model simple digital circuits using Verilog HDL. (BL-3)
CO 3 Simulate digital circuits using Verilog HDL.(BL-3)
CO 4 Analyze simulation techniques in behavioral and Switch level models of digital circuits. (BL-3)
CO 5 Model digital circuits using Verilog tasks and directives.( BL-3)
CO-PO Mapping
CO COURSE CONTENT PSO
PO PO PO PO PO PO PO PO PO PO PO PO PSO PSO
1 2 3 4 5 6 7 8 9 10 11 12 1 2
CO1 3 3 2 3 2 2
CO2 3 3 1 3 2 1
CO3 3 3 1 3 2 2
CO4 3 3 1 3 3 1
CO5 3 3 3 3 3 3
1: Low, 2-Medium, 3- High
COURSE CONTENT
MODULE -1 Introduction to digital design 10hrs
INTRODUCTION TO DIGITAL DESIGN. Introduction to hardware descriptive language (HDL).
Difference between computer programming languages and HDLs Examples and HDL based digital design
flow based on FPGA and CPL
Verilog as HDL, Levels of Design Description, Concurrency, Simulation and Synthesis using EDA tools
At the end of the Module 1, students will be able to:
1. What is importance of HDL (Hardware Descriptive Language) (BL-2)
2. Describe difference between concurrent and sequential programming (BL-2)
3. Explain Digital design and implementation flow (BL-2)
MODULE -2 Introduction To Verilog 9hrs
Language Constructs And Conventions: Introduction, Keywords, Identifiers, White Space Characters,
Comments, Numbers, Strings, Logic Values, Strengths, Data Types, Scalars and Vectors, Parameters, Operators.
Gate Level Modeling: Introduction, AND Gate Primitive, Module Structure, Other Gate Primitives, Illustrative
Examples, Tri-State Gates, Array of Instances of Primitives, Additional Examples, Design of Flipflops with Gate
Primitives, Delays, Strengths and Contention Resolution, Net Types, Design of Basic Circuits.
At the end of the Module 2, students will be able to:
1. Explain simulation and synthesis models of Digital circuits (BL-2)
2. Describe simulation techniques( BL-2)
3. Explain How to create test bench (BL-2)
4. Model digital circuits in Gate level using Verilog (BL-3)
5. Explain Gate Primitives used in Verilog (BL-2)
MODULE-3 Verilog Modeling -1 10hrs
Data Flow Level Modeling: Introduction, Continuous Assignment Structures, Delays and Continuous
Assignments, Assignment to Vectors, Operators.
Behavioral Modeling: Introduction,Operations and Assignments, Functional Bifurcation, Initial Construct,
Always Construct, Examples, Assignments with Delays, Wait construct, Multiple Always Blocks, Designs at
Behavioral Level, Blocking and Non-blocking Assignments, The case statement, Simulation Flow. iƒandiƒ-else
constructs, assign-deassign construct, repeat construct, for loop, the disable construct, whileloop, forever loop,
parallel blocks, force-release construct, Event.
At the end of the Module 3, students will be able to:
1. Model digital circuits in data flow style (BL-3)
2. Explain High level abstraction of digital systems with behavioral modeling of systems(BL-2)
3. Apply concepts behavioral constructs like ‗always‘ ,‘initial‘, ‗if‘, ‗if-else‘, ‗case‘..etc to describe a
digital system (BL-3)
MODULE-4 Verilog Modeling -2 8hrs
Switch Level Modeling: Introduction, Basic Transistor Switches, CMOS Switch, Bi-directional
Gates, Time Delays with Switch Primitives, Instantiations with Strengths and Delays, Strength Contention with
Tri-reg Nets.
Functions, Tasks, And User-Defined Primitives: Introduction, Function, Tasks, User- Defined Primitives
(UDP), FSM Design (Moore and Mealy Machines).(4h)
At the end of the Module 4, students will be able to:
1. Describe low level abstraction of digital systems with switch modeling of systems (BL-2)
2. Explain Switch level primitives (BL-2)
3. Describe the importance of tasks and functions (BL-2)
4. model digital systems using User- Defined Primitives (UDP) (BL-3)
MODULE-5 Tasks and Functions 11hrs
System Tasks, Functions And Compiler Directives: Introduction, Parameters, Path Delays, Module
Parameters, System Tasks and Functions, File-Based Tasks and Functions, Compiler Directives,
Hierarchical Access, Verilog models for memories and buses:Static RAM memory, UART Design
At the end of the Module 5, students will be able to:
1 Explain the concept of FSM (BL-2)
2 Learn compiler directives. (BL-2)
3 Describe the usage of functions and tasks in packages(BL-2)
Total hours:48 hours
Text Book(s):
1. 1. T.R. Padmanabhan and B. Bala Tripura Sundari, ―Design through Verilog HDL‘‘, WSE, IEEE
Press 2008.
2. 2. J. Bhaskar, ―A Verilog Primer‘‘, BSP, 2nd edition 2003.
3. Samir Palnitkar, ―Verilog HDL‖, Pearson Education,2nd Edition,2003.