COURSE PLAN

Name of the Course : DIGITAL LOGIC DESIGN

Course Level : UG
Academic Year : 2024-2025 Programme : [Link]
Year/Semester : II-I Regulation : R23
Course Type : Core Course Credits : 03
Course Code : B23EC06 L-T-P-C : 3-0-0-3

Department : Electronics and Communication Engineering

Course Coordinator : [Link]
Course Instructors : 1. Dr. Syed Musthak Ahmed
2. [Link]
1. COURSE SUMMARY:
This course introduces the basic principles and techniques used in digital logic design. The
students learn Number systems, Complements of Numbers, Codes, Boolean algebra, and Digital Logic
Gates. Minimization of Boolean functions, Karnaugh map method, Don’t Care Map Entries, and
Tabular Method, Realization of Logic Gates Using Diodes & Transistors i.e, AND, OR and NOT
Gates, DCTL, RTL, DTL, TTL, CML and CMOS Logic Families, Combinational Logic Circuits,
Sequential Circuits, Registers and Counters, Sequential Machines and Finite state machine.

2. COURSE-SPECIFIC LEARNING OUTCOMES (CO):

At the end of the course, the students will be able to

CO-1: Acquire the knowledge on numerical information in different forms and Boolean algebra
theorems.
CO-2: Define Postulates of Boolean algebra and to minimize combinational functions, and design
the combinational circuits.
CO-3: Design and analyze sequential circuits for various cyclic functions.
CO-4: Characterize logic families and analyze them for the purpose of AC and DC parameters.

Course Articulation Matrix

PO/PSO PO PO PO PO PO PO PO PO PO PO PO PO PSO PSO

1 2 3 4 5 6 7 8 9 10 11 12 1 2
CO
CO1 3 2 3 1 2 - - - - - - - - -
CO2 3 2 3 1 2 - - - - - - - - -
CO3 3 2 3 1 2 - - - - - - - - -
CO4 3 2 3 1 2 - - - - - - - - -
Mapping
Target Level

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3. DETAILED SYLLABUS:

UNIT I
Number Systems: Number systems, Complements of Numbers, Codes- Weighted and Non-weighted
codes and its Properties, Parity check code and Hamming code.
Boolean algebra: Basic Theorems and Properties, Switching Functions- Canonical and Standard
Form, Algebraic Simplification, Digital Logic Gates, EX-OR gates, Universal Gates, Multilevel
NAND/NOR realizations. (Contact hours: 09)

UNIT II
Minimization of Boolean functions: Karnaugh Map Method - Up to five Variables, Don’t Care Map
Entries, Tabular Method
Realization of Logic Gates Using Diodes & Transistors: AND, OR and NOT Gates using Diodes
and Transistors, DCTL, RTL, DTL, TTL, CML and CMOS Logic Families and its Comparison,
standard TTL NAND Gate-Analysis & characteristics, TTL open collector O/Ps, Tristate TTL, MOS
& CMOS open drain and tri-state outputs ,IC interfacing- TTL driving CMOS & CMOS driving TTL.
(Contact hours: 10)
UNIT III
Combinational Logic Circuits: Adders, Subtractors, Comparators, Multiplexers, Demultiplexers,
Encoders, Decoders and Code converters, Hazards and Hazard Free Relations.
Sequential Circuits Fundamentals: Basic Architectural Distinctions between Combinational and
Sequential circuits, SR Latch, Flip Flops: SR, JK, JK Master Slave, D and T Type Flip Flops,
Excitation Table of all Flip Flops, Timing and Triggering Consideration, Conversion from one type
of Flip-Flop to another. (Contact
hours: 14)

UNIT IV
Registers and Counters: Shift Registers – Left, Right and Bidirectional Shift Registers, Applications
of Shift Registers - Design and Operation of Ring and Twisted Ring Counter, Operation of
Asynchronous and Synchronous Counters.
Sequential Machines: Finite State Machines, Synthesis of Synchronous Sequential Circuits- Serial
Binary Adder, Sequence Detector, Parity-bit Generator, Synchronous Modulo N –Counters.
. (Contact hours: 10)
UNIT V
Finite state machine: capabilities and limitations, Mealy and Moore models, State equivalence and
machine minimization, simplification of incompletely specified machines, Merger graphs.
Asynchronous design-modes of operation, Hazards, synthesis of SIC fundamental mode circuits,
synthesis of burst mode circuits. Introduction to ASM Charts (Contact hours: 08)

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4. TEXTBOOKS/LEARNING RESOURCES:
1. Zvi Kohavi &Niraj K. Jha, - Switching and Finite Automata Theory, 3rd Ed., Cambridge, 2010.

2. R. P. Jain - Modern Digital Electronics, 3rd Edition, 2007- Tata McGraw-Hill

5. REFERENCE BOOKS/LEARNING RESOURCES:

1. Morris Mano, Fredriac J. Hill, Gerald R. Peterson - Introduction to Switching Theory and

LogicDesign–3rd Ed., John Wiley & Sons Inc.

2. Charles H. Roth - Fundamentals of Logic Design, 5th ED., Cengage Learning, 2004.
6. MOOC COURSES (Reference to the Course):

1. NPTEL course: Digital Logic Design, IIT Kharagpur

2. Course: Prof. [Link] choudhury, 12 Weeks
3. Course link: [Link]
4. Nptel course: Digital Circuits Systems , IIT Madras
5. Course: [Link] Balachandran,9weeks
6. Course link: [Link]

7. Lecture Wise Plan

[Link]. Topics No of Lectures Cumulative Classes

UNIT-1 Number Systems & Boolean algebra
1 Number systems 1
2 Complements of Numbers 1
3 Codes 1
4 Parity check code and Hamming code 1
5 Basic Theorems and Properties 1 09
6 Switching Functions 1
7 Algebraic Simplification 1
8 Digital Logic Gates 1
9 Multilevel NAND/NOR realizations 1
UNIT-2 Minimization of Boolean functions& Realization of Logic Gates Using Diodes &
Transistors
10 Karnaugh Map Method 2
11 Tabular Method 1
AND, OR and NOT Gates using Diodes and
12 1
Transistors
13 Logic Families 1
standard TTL NAND Gate-Analysis & 10
14 2
characteristics
15 TTL open collector O/Ps 1
Tristate TTL, MOS & CMOS open drain and
16 1
tri-state outputs,
17 IC interfacing- TTL driving CMOS & 1
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 CMOS driving TTL
UNIT-3 Combinational Logic Circuits
18 Adders 1
19 Subtractors 1
20 Comparators 1
21 Multiplexers 1
22 Demultiplexers 1
23 Encoders 1
24 Decoders and Code converters 1
25 Hazards and Hazard Free Relations. 1 14
26 Adders 1
27 Subtractors 1
Basic Architectural Distinctions between
28 1
Combinational and Sequential circuits
29 SR Latch, Flip Flops 1
30 Excitation Table of all Flip Flops 1
Conversion from one type of Flip-Flop to
31 1
another.
UNIT-4 Registers and Counters & Sequential Machines
32 Shift Registers 1
Design and Operation of Ring and Twisted
33 1
Ring Counter
Operation of Asynchronous and
34 2
Synchronous Counters.
09
35 Finite State Machines Shift Registers 2
36 Synthesis of Synchronous Sequential Circuits 1
37 Parity-bit Generator 1
38 Synchronous Modulo N –Counters 1
UNIT-5 Finite state machine
39 Mealy and Moore models 1
40 State equivalence and machine minimization 2
simplification of incompletely specified
41 1
machines
42 Merger graphs 1
09
43 Asynchronous design-modes of operation 1
Hazards, synthesis of SIC fundamental mode
44 1
circuits
45 synthesis of burst mode circuits 1
46 Introduction to ASM Charts 1

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8. Tutorial Wise Plan

[Link]. Content Planned

1 Unit 1: Problem solving, Discussion (TPS)

2 Unit 2: Problem solving, Discussion (TPS)

3 Unit 3: Problem solving, Discussion (TPS)

4 Unit 4: Problem solving, Discussion (TPS)

5 Unit 5: Problem solving, Discussion (TPS)

9. Contents Beyond Syllabus

1. Classification of IC’s
2. Chip design concepts

10. Attendance Policy

1. 75% attendance in the course is mandatory.
2. A maximum of 10% shall be allowed under genuine and valid grounds.
3. Students with Shortage of attendance below 65% in aggregate shall in no case be
considered.

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