2-1

TABLE 2-1
Truth Tables for the Three Basic Logic Operations

AND OR NOT

X Y Z = X⋅Y X Y Z = X +Y X Z=X

0 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0
1 0 0 1 0 1
1 1 1 1 1 1

Table 2-1 Truth Tables for the Three Basic Logical Operations

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-2
X X
Y
Z = X •Y
Y
Z = X +Y X • X

AND gate OR gate NOT gate or

inverter
(a) Graphic symbols

X 0 0 1 1

Y 0 1 0 1

(AND) X •Y 0 0 0 1

(OR) X +Y 0 1 1 1

(NOT) X 1 1 0 0

(b) Timing diagram

Fig. 2-1 Digital Logic Gates

© 2001 Prentice Hall, Inc.
M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-3

A A
B F = A BC B F=A+B+C+D+E+F
C C
D
(a) Three-input AND gate E (b) Six-input OR gate
F

Fig. 2-2 Gates with More than Two Inputs

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-4

TABLE 2-2
Truth Table
for the Function F ⫽ X ⫹ YZ

X Y Z F

0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1

Table 2-2 Truth Table for the Function F ⫽ X ⫹ Y Z

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-5

Y • F
Z

Fig. 2-3 Logic Circuit Diagram for F = X + Y′Z

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-6

TABLE 2-3
Basic Identities of Boolean Algebra

1. X +0 = X 2. X⋅1 = X
3. X +1 = 1 4. X⋅0 = 0
5. X +X = X 6. X⋅X = X
7. X +X = 1 8. X⋅X = 0
9. X=X
10. X +Y = Y +X 11. XY = YX Commutative
12. X + (Y + Z ) = (X + Y ) + Z 13. X( YZ) = ( XY )Z Associative
14. X ( Y + Z) = XY + XZ 15. X + YZ = ( X + Y ) (X + Z ) Distributive
16. X +Y = X⋅Y 17. X⋅Y = X +Y DeMorgan’s

Table 2-3 Basic Identities of Boolean Algebra

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-7

TABLE 2-4
Truth Tables to Verify DeMorgan’s Theorem

A) X Y X ⫹Y X +Y B) X Y X Y X⋅Y

0 0 0 1 0 0 1 1 1
0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 0 1 0
1 1 1 0 1 1 0 0 0

Table 2-4 Truth Tables to Verify DeMorgan’s Theorem

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-8

TABLE 2-5
Truth Table for Boolean Function

X Y Z F

0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

Table 2-5 Truth Table for Boolean Function

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-9

X • • •

Y • F
Z • •

(a) F = XYZ + XYZ + XZ

X • •
Y
F

Z
(b) F = XY + XZ
Fig. 2-4 Implementation of Boolean Function with Gates

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-10

TABLE 2-6
Minterms for Three Variables

Product
X Y Z Term Symbol m0 m1 m2 m3 m4 m5 m6 m7

0 0 0 XYZ m0 1 0 0 0 0 0 0 0
0 0 1 X YZ m1 0 1 0 0 0 0 0 0
0 1 0 XYZ m2 0 0 1 0 0 0 0 0
0 1 1 XYZ m3 0 0 0 1 0 0 0 0
1 0 0 XY Z m4 0 0 0 0 1 0 0 0
1 0 1 XYZ m5 0 0 0 0 0 1 0 0
1 1 0 XYZ m6 0 0 0 0 0 0 1 0
1 1 1 XYZ m7 0 0 0 0 0 0 0 1

Table 2-6 Minterms for Three Variables

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-11

TABLE 2-7
Maxterms for Three Variables

X Y Z Sum Term Symbol M0 M1 M2 M3 M4 M5 M6 M7

0 0 0 X +Y +Z M0 0 1 1 1 1 1 1 1
0 0 1 X +Y +Z M1 1 0 1 1 1 1 1 1
0 1 0 X +Y +Z M2 1 1 0 1 1 1 1 1
0 1 1 X +Y +Z M3 1 1 1 0 1 1 1 1
1 0 0 X +Y +Z M4 1 1 1 1 0 1 1 1
1 0 1 X +Y +Z M5 1 1 1 1 1 0 1 1
1 1 0 X +Y +Z M6 1 1 1 1 1 1 0 1
1 1 1 X +Y +Z M7 1 1 1 1 1 1 1 0

Table 2-7 Maxterms for Three Variables

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-12

TABLE 2-8
Boolean Functions of Three Variables

(a) X Y Z F F (b) X Y Z E

0 0 0 1 0 0 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 1 0 0 1 0 1
0 1 1 0 1 0 1 1 0
1 0 0 0 1 1 0 0 1
1 0 1 1 0 1 0 1 1
1 1 0 0 1 1 1 0 0
1 1 1 1 0 1 1 1 0

Table 2-8 Boolean Functions of Three Variables

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-13

X
Y F
Z
X
Y
Fig. 2-5 Sum-of-Products Implementation

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-14

A
B
A
B C
C D

D C
E E
(a) AB + C ( D + E ) (b) AB + CD + CE

Fig. 2-6 Three-Level and Two-Level Implementation

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-15

Y
F
Z

X
Y
Z
Fig. 2-7 Product-of-Sums Implementation

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-16

Y
X 0 1
m0 m1 0 XY XY

m2 m3 1 XY XY

(a) (b)

Fig. 2-8 Two-Variable Map

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-17

Y Y
X 0 1 X 0 1

0 0 1

1 1 1 1 1

(a) XY (b) X + Y
Fig. 2-9 Representation of Functions in the Map

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-18

YZ Y
X 00 01 11 10

m0 m1 m3 m2 0 XY Z XY Z XY Z XY Z

m4 m5 m7 m6 X 1 XY Z XY Z XY Z XY Z

Z
(a) (b)
Fig. 2-10 Three-Variable Map

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-19

YZ Y
X 00 01 11 10 XY

0 1 1

X 1 1 1

Z
XY
Fig. 2-11 Map for Example 2-3

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-20

YZ Y 3 1
X 00 01 11 10
7 5
XZ
0 0 1 3 2 2 0

X 1 4 5 7 6 6 4
XZ
Z
(a) (b)
Fig. 2-12 Three-Variable Map: Flat and on a Cylinder to Show Adjacent Squares

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-21

X
YZ Y YZ Y
X 00 01 11 10 X 00 01 11 10
Z
0 1 1 0 1 1 1 1

X 1 1 1 X 1 1 1

Z Z
Z Y
(a) (b)

Fig. 2-13 Product Terms Using Four Minterms

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-22

YZ Y YZ Y
X 00 01 11 10 X 00 01 11 10

0 1 0 1 1

X 1 1 1 1 X 1 1 1 1

Z Z
(a) F1 (X, Y, Z) = Σm (3, 4, 6, 7) (b) F2 (X, Y, Z) = Σm(0, 2, 4, 5, 6)
= YZ + XZ = Z + XY
Fig. 2-14 Maps for Example 2-4

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-23

YZ Y
X 00 01 11 10

0 1 1

X 1 1 1 1

Z
Fig. 2-15 F( X, Y , Z ) = Σm(1, 3, 4, 5, 6)

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-24

YZ Y
X 00 01 11 10

0 1 1 1

X 1 1 1

Z
Fig. 2-16 F( X, Y , Z ) = Σm (1 ,2 , 3, 5, 7)

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-25

YZ Y
WX 00 01 11 10
m0 m1 m3 m2 00

m4 m5 m7 m6 01
X
m 12 m 13 m 15 m 14 11
W
m8 m9 m 11 m 10 10

Z
(a) (b)
Fig. 2-17 Four-Variable Map

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-26

YZ Y
WX 00 01 11 10 XZ

00 0 1 3 2 2
0 10
8
01 4 5 7 6
X
11 12 13 15 14
W 11
9
10 8 9 11 10 3
1

XZ Z
(a) (b)
Fig. 2-18 Four-Variable Map: Flat and on a Torus to Show Adjacencies

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-27

YZ Y
WX 00 01 11 10

00 1 1 1

01 1 1 1
X
11 1 1 1
W
10 1 1

Z
Fig. 2-19 Map for Example 2-5: F = Y + WZ + XZ

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-28

CD C
AB 00 01 11 10

00 1 1 1

01 1
B
11
A
10 1 1 1

D
Fig. 2-20 Map for Example 2-6: F = BD + BC + ACD

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-29

CD C
AB 00 01 11 10

00 1 1

01 1 1 1 1
B
11 1 1
A
10

D
Fig. 2-21 Prime Implicants for Example 2-7: AD, BD, and AB

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-30

CD C CD C
AB 00 01 11 10 AB 00 01 11 10

00 1 00 1

01 1 01 1
B B
11 1 1 1 11 1 1 1
A A
10 1 1 10 1 1

D D
(a) Plotting the minterms (b) Essential prime implicants

Fig. 2-22 Simplification with Prime Implicants in Example 2-8

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-31

CD C
AB 00 01 11 10 3
00 1 1 1

01 1 1
B
11 1 1
A
10
1 1

D
1 2
Fig. 2-23 Map for Example 2-9

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-32

CD C
AB 00 01 11 10

00 1 1 0 1

01 0 1 0 0
B
11 0 0 0 0
A
10
1 1 0 1

D
Fig. 2-24 Map for Example 2-10: F = (A + B) (C + D) (B + D)

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-33

CD C CD C
AB 00 01 11 10 AB 00 01 11 10

00 X 1 1 X 00 X 1 1 X

01 0 X 1 0 01 0 X 1 0
B B
11 0 0 1 0 11 0 0 1 0
A A
10 0 0 1 0 10 0 0 1 0

D D
(a) F = CD + AB (b) F = CD + AD
Fig. 2-25 Example with Don't-Care Conditions

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-34 Graphics Symbols

Name Distinctive Rectangular Algebraic Truth

shape shape equation table

X Y F
X & 0 0 0
X
AND F F F = XY 0 1 0
Y 1 0 0
Y
1 1 1

X Y F
X ≥1 0 0 0
X
OR F F F = X +Y 0 1 1
Y 1 0 1
Y
1 1 1

1 X F
NOT
(inverter) X • F X • F F=X 0 1
1 0

1 X F
Buffer X F X F F=X 0 0
1 1

X Y F
X & 0 0 1
X
NAND
Y
• F • F F = X •Y 0 1 1
Y 1 0 1
1 1 0

X Y F
X ≥1 0 0 1
X
NOR
Y
• F • F F = X +Y 0 1 0
Y 1 0 0
1 1 0

X Y F
X =1 F = XY + XY 0 0 0
Exclusive–OR X
(XOR) F F 0 1 1
Y =X Y
Y 1 0 1
1 1 0

X Y F
X =1 0 0 1
Exclusive–NOR X F = XY + XY
(XNOR) Y
• F • F
=X Y
0 1 0
Y 1 0 0
1 1 1

© 2001 Prentice Hall, Inc. Fig. 2-26 Digital Logic Gates

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-35

NOT X • XX • X

X
AND
Y
• • XY = XY

X •
OR
• • XY = X + Y
Y

Fig. 2-27 Logical Operations with NAND Gates

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-36

X X
•
Y • XYZ Y • X + Y + Z = XYZ
Z Z •
(a) AND - NOT (b) NOT – OR

X • X X • X

(c) NOT

Fig. 2-28 Alternative Graphics Symbols for NAND and NOT Gates

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-37

A A
•
B
F
B • F
C C •
D D
•

(a) (b)

A
B
•
C
• F

D
•

(c)

Fig. 2-29 Three Ways to Implement F = AB + CD

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-38

YZ Y
X 00 01 11 10

0 1 1 1
F = XY + XY + Z
X 1 1 1 1

(a)

X X
Y
• Y
•
X • X
• • F • • F
Y • Y

Z • Z

(b) (c)

Fig. 2-30 Solution to Example 2-12

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-39

A
F
B

C
(a) AND – OR gates

C
•
D •
B •
A
•
• F
B •
C
•
(b) NAND gates
Fig. 2-31 Implementing F = A (CD + B) + BC
© 2001 Prentice Hall, Inc.
M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-40

A
B
A
F
B
E
C
D

(a) AND – OR gates

A
•
B •
A • • • F
B
•
E
C • X • •
D •
(b) NAND gates
Fig. 2-32 Implementing F = ( A B + AB )E (C + D)

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-41

Inverter X • XX • X

X
OR
Y
• • X +Y = X +Y

X •
AND
• • X + Y = XY
Y

Fig. 2-33 Logic Operations with NOR Gates

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-42

X X •
Y • X +Y + Z Y • XYZ = X +Y + Z
Z Z •
(a) OR – NOT (b) NOT – AND
Fig. 2-34 Two Graphic Symbols for NOR Gate

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-43

A
B
•
C •
• • F
D •
E
Fig. 2-35 Implementing F = (A + B) (C + D) E with NOR Gates

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-44

A •
B •
• • Y F
A • •
•

•
B

C
E •
D
• •
Fig. 2-36 Implementing F = (AB + AB) E (C + D) with NOR Gates

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-45

X •
•
• •
• • • F=X Y
•
Y •
Fig. 2-37 Exclusive-OR Constructed with NAND Gates

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-46

YZ Y CD C
X 00 01 11 10 AB 00 01 11 10

0 1 1 00 1 1

X 1 1 1 01 1 1
B
Z 11 1 1
A
(a) X Y Z 10 1 1

D
(b) A B C D

Fig. 2-38 Maps for Multiple-Variable Odd Functions

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-47

TABLE 2-9
Truth Table for an Even Parity Generator

Three-Bit Message Parity Bit

X Y Z P

0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

Table 2-9 Truth Table for an Even Parity Generator

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-48

X X
Y Y
C
Z
P
Z P

(a) P = X Y Z (b) C = X Y Z P
Fig. 2-39 Multiple-Input Odd Functions

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-49

IN

IN • OUT OUT tPHL t PLH

t pd = max (t PHL, t PLH )

Fig. 2-40 Propagation Delay for an Inverter

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-50

A B:

No Delay
(ND)
a b c d e

Transport
Delay (TD)

Inertial
Delay (ID)

0 2 4 6 8 10 12 14 16 Time (ns)

Fig. 2-41 Examples of Behavior of Transport and Inertial Delays

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-51

Signal Logic Signal Logic

value value value value

H 1 H 0

L 0 L 1
(a) Positive logic (b) Negative logic

Fig. 2-42 Signal Assignment and Logic Polarity

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-52
X Y Z
L L L
L H L X CMOS Z
H L L Y Gate
H H H

(a) Truth table (b) Gate block diagram

with H and L

X Y Z
0 0 0 X
0 1 0 Z
Y
1 0 0
1 1 1

(c) Truth table (d) Positive-logic

for positive logic AND gate

X Y Z
X
1 1 1 Z
1 0 1 Y
0 1 1
0 0 0
(e) Truth table (f) Negative-logic
for negative logic OR gate

Fig. 2-43 Demonstration of Positive and Negative Logic

© 2001 Prentice Hall, Inc.
M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-53

C X • • Y •
C = 1 and C = 0
• •
(b)
X TG Y
X TG Y
X • • Y
C C = 0 and C = 1

(a) (c) C •
(d)

Fig. 2-44 Transmission Gate (TG)

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
2-54

•
A A C TG1 TG0 F
• TG0
0 0 No path Path 0
C • • • • F 0 1 Path No path 1
• 1 0 No path Path 1
• TG1
1 1 Path No path 0

(a) (b)

Fig. 2-45 Transmission Gate Exclusive-OR

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.