Unit IV
Timers
Timer
Timer maintains the timing of an operation in sync with
a system clock or an external clock
Used to measure time generating delays, used for
generating baud rates (the rate at which information is
transferred). Used to count the time interval between
events.
Watchdog timer
A watchdog timer is a piece of hardware that can be used to
automatically detect software defects and reset the processor if any
occur.
watchdog timer is based on a counter that counts down from some
initial value to zero or counts up from zero to some max value.
During normal operation, the processor regularly resets the
watchdog timer to prevent it from elapsing or "timing out“
Ex: (a) In mobile phone, display is off in case no GUI
interaction takes place,
(b) Used in laptop and in desktop to switch off the screen
and enter into sleep mode when no input with in
predefined time
(c) If Software hangs due to some bug/issue, it helps to
reset the system automatically without any human
interactions.
(d) An application in temperature controller is that if
controller takes no action to switch off the current when
temperature reaches max limit, the current is switched off
by WDT and warning signal is raised as indication of
controller failure. Failure to switch off current may burst a
boiler in which water is over heated
Watchdog timer control register
The operation of the watchdog is controlled by the 16-bit register
called Watchdog timer control register (WDTCTL)
Field Name Bits Description
WDTPW 8 – 15 Watchdog timer PW: If 5A is in higher byte, allows to
write the lower byte, other wise it is not.
A reset will occur if a value with an incorrect PW is written.
This can be done to reset the chip from S/W
WDT-HOLD 7 Watchdog timer hold: This bit is used to stop the watchdog
counter
It is cleared after power on reset (POR)
0 = watchdog timer is not stopped
1 = watchdog timer stopped
WDT- 6 This bit selects the activating edge of the NMI
NMIES input
It is cleared by POR
0 = A rising edge triggers an NMI
1 = A falling edge triggers an NMI
Field Name Bits Description
WDTNMI 5 The NMI bit selects the function of the input pin
It is cleared by POR
0 = The input works as reset input
1 = The input works as an edge-sensitive NMI input
WDT- 4 Watchdog timer mode select: This bit selects the operating
TMSEL mode: watchdog or timer mode of operation
0 = Watchdog mode
1 = Timer mode
WDT- 3 Watchdog timer counter clear: Setting this bit to ‘1’ clear the
CNTCL count value to 0000h. This is called petting/feeding/kicking
the dog
This bit automatically reset to ‘0’ after watchdog counter
(WDTCNT) has been reset
0 = No action
1 = Count value = 0000h, i.e clearing the counter
Field Name Bits Description
WDTSSEL 2 Watchdog timer clock source select: This bit selects the
clock source for watchdog counter (WDTCNT – 16-bit
register)
0 = WDTCNT is clocked by SMCLK
1 = WDTCNT is clocked by ACLK
WDTISX 10 Watchdog timer interval select: These bits select the
watchdog timer interval to set the WDTIFG ( Watchdog timer
interrupt flag) in the SFR IFG1
IS1 IS0 Let fACLK = 32 KHz
0 0 = 64 x 1/fACLK = 2 ms
0 1 = 512 x 1/fACLK = 16 ms
1 0 = 8192 x 1/fACLK = 256 ms
1 1 = 32768 x 1/fACLK = 1024 ms
The watchdog is always active after the MSP430 has been reset
By default the clock is SMCLK, which is in turn derived from the
DCO at about 1 MHz
Thus the default period of the watchdog is 32768 x = 32 ms
It must clear or stop or reconfigure the watchdog before this time
has elapsed, this is done by setting the WDTCNTCL bit in WDTCTL
register - petting/feeding/kicking the dog
If the watchdog is running, the watchdog counter must be
repeatedly cleared to prevent it counting up as far as its limit. This is
done by setting the WDTCNTCL bit in WDTCTL register. This bit
automatically clears again after WDTCNT has been reset.
The watchdog timer sets the watchdog timer interrupt flag
(WDTIFG) in the SFR IFG1( Interrupt flag reg 1) when the count
value in watchdog counter (WDTCNT) reaches maximum value
Thus a program can check this bit to take proper action.
Programming example to show the use of WDT
LED1 – State of button B1 (whether it is up or down)
LED2 – State of WDTIFG
When button is down, LED1 is always in ON state and at the same
time watchdog timer do not take any action. This is done by setting
the WDTCNTCL bit in WDTCTL register.
If the B1 is left up for more than 1 sec, the WDT times out, raises
the WDTIFG, this is shown by LED2 lighting and LED1 get OFF
Basic Timer1
BTSSEL – Basic Timer1 clock source select
BTDIV – Basic Timer1 clock divider
BTCNT1 – Basic Timer1 counter1 (8-bit)
BTCNT2 – Basic Timer1 counter2 (8-bit)
BTFRQx – Basic Timer1 frame frequency select bit
BTIPx – Basic Timer1 interrupt interval
BTIFG – Basic Timer1 interrupt flag bit in SFR IFG2
BTIE – Basic Timer1 interrupt enable bit in SFR IE2
It provides the clock for the LCD module and generates periodic interrupts
Newer devices also contain a RTC driven by a signal at 1 Hz from Basic Timer 1
There are two 8-bit counters – BTCNT1 and BTCNT2 – used independently or
cascaded for longer intervals
BTCNT1: Takes its input from ACLK and provides the clock for the LCD module,
at frequency fLCD
The two BTFRQx ( frame frequency select bits) select the value of fLCD, which
can vary from fACLK /256 to fACLK /32
BTCNT2: can be used independently of BTCNT1 by setting
BTDIV bit to 0, in which case the BTSSEL bit selects the clock
from ACLK (BTSSEL=0) or SMCLK (BTSSEL=1)
For longer intervals, BTCNT2 can be clocked from the output
of BTCNT1 at a frequency of fACLK /256, i.e BTCNT1 and
BTCNT2 are cascaded by setting BTDIV to 1 (here BTSSEL =
1 or 0)
Set the BTDIV bit to cascade the counter
Setting BTHOLD (Basic Timer1 hold) bit stops BTCNT2, but stops
BTCNT1 if both BTHOLD and BTDIV bits are set
BTCNT2 provides no output signals, instead it raises the BTIFG
flag at a frequency determined by the BTIPx (Basic Timer1 interrupt
interval) bits
The range goes from fCLK2 /256 to fCLK2 /2, with the counters
cascaded gives a period from 16 ms to 2 sec
The BTIFG flag is in the SFG IFG2
An interrupt also requested if the BTIE bit is set in SFR
IE2
The interrupt is maskable so GIE must also be set for the
interrupt to be accepted
The BTIFG flag is cleared automatically when the
interrupt is serviced.
Basic Timer1 control register (BTCTL)
Real Time Clock (RTC)
RTC is a h/w device that counts seconds, minutes, hours,
days, months and years.
The current time and date are held in a set of registers
that contains the following bytes:
Real Time Clock control register (RTCCTL)
The RTC has an interrupt flag (RTCFG) and
corresponding enable bit RTCIE in RTCCTL
The flag is set for every minute, every hour, daily at
midnight or daily at noon depending on the RTCTEVx bits
– Calender mode
Interrupts are generated by the RTC module if RTCIE is
set
The interrupt interval is determined by RTCTEVx
RTCFG flag is set at an interrupt and cleared
automatically when it is serviced.
Timer_A
Timer block: It is controlled by Timer A control register (TACTL)
Note: Strongly advised to stop the timer before modifying
its operation (except the TACLR, interrupt enables (TAIE),
and interrupt flags (TAIFG)) to avoid possible errors
Capture/compare channel
Timer_A has three channels (0, 1 and 2). Each channel is controlled
by capture/compare control register (TACCTLn)
It is used to capture the timer data, or to generate time intervals.
Each channel has 16-bit Timer_A Capture/Compare register
(TACCRx)
Timer_ A has two modes of operation
Capture mode
Compare mode
(i) Capture mode:
The capture mode is selected when CAP= 1. Capture mode is used to record
time events
The capture inputs CCIxA and CCIxB are connected to external pins or internal
signals and are selected with the CCISx bits (capture compare input select).
The CMx (Capture Mode) bits select the capture edge of the input signal as
rising, falling, or both.
A capture occurs on the selected edge of the input signal
If a capture occurs: (1) The timer value is copied into the TACCRx register
(2) The interrupt flag CCIFG is set
The input signal level can be read at any time via the CCI ( Capture Compare
Input) bit.
(ii) Compare Mode:
The compare mode is selected when CAP (Capture mode) = 0
The compare mode is used to generate PWM output signals or
interrupts at specific time intervals
When TAR counts to the value in a TACCRx: (1) Interrupt flag
CCIFG is set (2) Internal signal EQUx = 1 (3) EQUx affects the
output according to the output mode (4) The input signal CCI is
latched into SCCI (Synchronized capture compare input).
Timer_A capture/compare control register (TACCTLn)
Interrupts from Timer_A
Interrupts can be generated by the timer block and by
each capture/compare channel
TACCR0 has its own interrupt vector,
TIMERA0_VECTOR. Its priority is higher than the other
vector, TIMERA1_VECTOR and TIMERA2_VECTOR
The CCIFG0 flag is cleared automatically when its
interrupt is serviced
But this does not happen for the other interrupts because
the ISR must first determine the source of the interrupt
The obvious way of doing this is to poll TAIFG and all
the CCIFGn flags to locate which is active, clear the flag
and service the interrupt
This is slow process and undesirable in ISR
The MSP430 provides an interrupt vector register TAIV
to identify the source of the interrupt rapidly
Measurement in the capture mode
The capture mode is used to take a time stamp of an event: to note
the time at which it occurred.
(a) Measurement of a signal duration or period by counting cycles of a
known clock
The timer clock is either ACLK or SMCLK, whose frequency is
known
Unknown signal is applied to the capture input
To measure the length of a single pulse, capture both edges and
subtract the captured times. This gives the duration of the pulse in
units of the timer clock’s period.
For a periodic signal, captured only the rising edges or falling edges
and the difference gives the period directly.
The period of the timer clock should be much less than the duration
of the signal to give good resolution as shown in above waveform.
(b) Measurement of a signal frequency by counting
cycles in a known time
It is used to measure a signal with a high frequency
The signal is used as the timer clock (TACLK) and the captured
events are typically edges of ACLK, whose frequency is known.
The difference b/w the captured value gives the number of cycles
of the signal in one cycle of ACLK. This gives the frequency rather
than the period.
Measurement of time: press and release of a button
Example to measure the time between each press or release of
button S2.
Button S2 is connected to P1.1. It is routed to capture compare
input B-channel0 (CCI0B)
Function definition for initialize ports for board
Output in the continuous mode
In the continuous mode, TAR counts from 0 to 0xFFFF and returns
to 0 on the next clock transition, which sets TAIFG
This mode is used in the following circumstances
All channels are needed for output
Outputs must be driven at different frequencies
Single pulses are required rather than periodic signals.
Some channels are used for capture and some for compare events.
This mode is convenient to calculate time
Limitation of this mode is that the time for the next compare event
must be updated in s/w, usually during an ISR
Operation of Timer_A in the sampling mode
Used for Asynchronous reception of byte
Sl No Asynchronous Synchronous
1 Does not need clock signal between Needs clock signal between the sender and
the sender and receiver receiver
2 Slow data transfer rate Fast data transfer rate
3 Use start bit at beginning and stop Not use start and stop bits
bit at end
4 Transmits character by character Blocks of characters are transmitted
5 Cheaper Costlier
Asynchronous reception of a byte using the capture
mode to detect the start bit and sampling mode (compare)
to read the bits that follow
Timer_B
CNTLx – Counter length
CLLDx – Compare latch load
TBCL1 – Timer_B Compare latch
It is closely similar to Timer_A
The differences between Timer_A and Timer_B are as follows:
The capture/compare registers TBCCRn are double-buffered –
Timer_B has an additional compare latch TBCLn in each channel and
the comparator detects a match between TBR and TBCLn, not with
TBCCRn
The length of TBR can be programmed to be 8, 10, 12 or 16
(default) bits. This is controlled by the CNTLx (counter length) bits
in TBCTL reg and allows a range of periods to be selected for the
continuous mode. Do not use this feature for the up and up/down
mode.
The SCCI (synchronized capture compare input) bit in not provided
– sampling mode is not possible, thus Timer_B is less suitable for
receiving asynchronous signals. So the devices that include Timer_B
are likely to have a dedicated module for communications.
What Timer Where?
What timer to choose for a particular application. A guide to
select a timer is as follows
Pulse-width modulation: Use Timer_A or Timer_B. Connect
the load directly to an output of the timer so that it can be driven
directly by hardware.
Less regular outputs: Connect directly to an output of
Timer_A or B. Use the up mode if the intervals between changes
are always the same. The continuous mode is easier if the
intervals vary.
Inputs to be sampled at regular intervals: Connect directly
to an input of Timer_A and use the sampling mode (compare)
Inputs to be timed: connect slow inputs directly to a capture
input of Timer_A or B. Fast signals should be connected to timer
clock input like TACLK.
What Timer Where? Cond…
Interaction with peripherals: Capture and compare events are
used for interaction with peripherals. This gives precise timing and
saves power if the CPU need not be restarted.
Periodic software interrupts are performed by using the
following timers
Watchdog timer is configured as timer if it is not needed as a
watchdog. Here there is a choice of four intervals like 2, 16, 250,
and 1000 ms from ACLK at 32 KHz. Shorter intervals can be
obtained by using SMCLK.
Basic Timer 1: Here the typical range is 2 to 16 ms. The real time
clock gives further options if available
Timer_A or B is used for any desired interval.
Less regular software interrupts: Use Timer_A or B in
continuous mode.