Interconnections
Spring 2016 CS430 - Computer Architecture 1
Interconnection Structures
• A computer consists of three
types of components or
modules:
– processor
– memory
– I/O
• Interconnection structure –
collection of paths connecting
various modules or
components
Spring 2016 CS430 - Computer Architecture 3
Exchanges
• What exchanges need to happen between the
three main components?
Spring 2016 CS430 - Computer Architecture 4
Memory Module
• Memory module consists of N words of equal
length
Spring 2016 CS430 - Computer Architecture 5
I/O Module
• I/O Module – is similar
functionally to memory
except:
– multiple external devices
can be controlled through
interfaces called ports
– data can be internal or
external
– I/O can send interrupts
Spring 2016 CS430 - Computer Architecture 6
Processor
• The processor
– reads instructions and data
– processes data and writes out
the results
– uses control signals to control
the overall operation of the
system
– receives interrupt signals
Spring 2016 CS430 - Computer Architecture 7
Interconnection Structure
• The interconnection must support the following
data exchanges:
– Memory to Processor
– Processor to Memory
– I/O to Processor
– Processor to I/O
– I/O to Memory (DMA: Direct Memory Access)
– Memory to I/O (DMA: Direct Memory Access)
Spring 2016 CS430 - Computer Architecture 8
Interconnection Structures
• Bus
• Point-to-point interconnection structures with
packetized data transfer
Spring 2016 CS430 - Computer Architecture 9
BUS INTERCONNECTION
Spring 2016 CS430 - Computer Architecture 10
BUS STRUCTURE
Spring 2016 CS430 - Computer Architecture 11
Bus Structure
• Bus – communication pathway connecting two or
more devices
• Multiple buses exist in a computer system
Spring 2016 CS430 - Computer Architecture 12
Data Lines
• Used for moving data
• Width of data bus is the number of lines
• Width of the data bus affects system
performance
Spring 2016 CS430 - Computer Architecture 13
Address Lines
• Used for specifying an address either in memory
or an I/O
• Higher order bits determine module to access
Spring 2016 CS430 - Computer Architecture 14
Control Lines
• Memory Write
• Memory Read
• I/O Write
• I/O Read
• Transfer Acknowledge
• Bus Request
• Bus Grant
• Interrupt Request
• Interrupt Acknowledge
• Clock
• Reset
Spring 2016 CS430 - Computer Architecture 15
MULTIPLE-BUS
HEIRARCHIES
Spring 2016 CS430 - Computer Architecture 16
Multiple-Bus Hierarchies
• The more devices connected to a bus, the more
likely performance will suffer
– More devices means greater bus length means greater
propagation delay
– As aggregate data transfer demand approaches the bus
capacity, the bus becomes a bottleneck
Spring 2016 CS430 - Computer Architecture 17
Traditional Bus Architecture
Spring 2016 CS430 - Computer Architecture 18
High-Performance Architecture
Spring 2016 CS430 - Computer Architecture 19
ELEMENTS OF BUS
DESIGN
Spring 2016 CS430 - Computer Architecture 20
Bus Types
• Dedicated – assigned to a single function (e.g
address bus) or a physical subset of components (e.g.
I/O bus connecting I/O modules)
• Multiplexed – used for both addresses and data
where an address valid control line is needed to
determine whether the data is an address or data
• Note: The term multiplexed can also be used as
follows: A multiplexed bus can be used to transmit
fewer bits of a larger number of bits (e.g. multiplexed
8-bit address bus used to transmit 16-bits of address
data)
Spring 2016 CS430 - Computer Architecture 21
Method of Arbitration
• Centralized – a single hardware device (the bus
controller or arbiter) is responsible for allocating
time on the bus
• Distributed – has no central controller, instead
each module has access control logic where the
modules work together to share the bus
– one module is the master and some other device is the
slave
Spring 2016 CS430 - Computer Architecture 22
Timing
• Synchronous Timing
• Asynchronous Timing
• The following slides depict timing diagrams. You
can read more about these in appendix N
– [Link]
TimingDIagrams
Spring 2016 CS430 - Computer Architecture 23
Synchronous Timing
• Synchronous – the
clock determines the
occurrence of events
• Processor reads from
memory and writes to
memory
Spring 2016 CS430 - Computer Architecture 24
Asynchronous Timing - Read
• Asynchronous –
there is no clock
• Processor reads
from memory
Spring 2016 CS430 - Computer Architecture 25
Asynchronous Timing - Write
• Asynchronous –
there is no clock
• Processor writes
to memory
Spring 2016 CS430 - Computer Architecture 26