PART-A

1. Compare enhancement-mode and depletion-mode MOS transistors.

2. Draw the logic diagram for Pass Transistor Logic.

3. Realize a 2:1 Multiplexer using transmission gates.

4. Define Noise Margin in CMOS logic circuits.

 Noise Margin in CMOS Logic Circuits refers to the maximum noise voltage that can be
tolerated by a circuit without causing an error in the logical operation.
 It ensures reliable signal transmission and noise immunity in digital circuits.

5. Outline the concepts of front-end and back-end design in VLSI.

 Front-end design focuses on the architecture and functionality of the system, while back-
end design focuses on the physical implementation and optimization of the design.
6. List the key technology issues in VLSI.
 Increasing Complexity
 Power Consumption
 Timing Closure
 Physical Design Challenges
7. Tabulate the need and types of testing in VLSI design.

8. State any four layout design rules used in VLSI physical design.
 Minimum Feature Sizes
 Minimum Spacing
 Metal Layer Rules
 Via Rules (like contact size and spacing)
9. Summarize the logic verification principles used in design validation.
 In design validation, logic verification ensures a design meets its specifications through
techniques like simulation, formal verification, and functional verification, checking for
correctness against specifications and intended behavior.
10. Mention the basic concepts involved in manufacturing tests.
 Fault Modeling – Identifying possible defects in circuits
 Fault Simulation – Simulating the circuit to verify how faults affect outputs
 Design for Testability (DFT)
11. When is a MOS transistor said to be pinched off?
 If Vds becomes sufficiently large that Vgd < Vt , the channel is no longer inverted near the
drain and becomes pinched off.
 However, conduction is still brought about by the drift of electrons under the influence of
the positive drain voltage.

12. Mention one advantage and one disadvantage of Built-In Self-Test (BIST).
 Advantage: Reduces External Test Equipment Cost
 Disadvantage: Increases Circuit Area and Power Consumption
13. State the classification of VLSI testing approaches.
The three significant VLSI testing methods are
 DFT(Design for Testability),
 BIST (Built-In Self-Test), and
 ATPG (Automatic Test Pattern Generation)
14. Name the two types of ASICs.
Types of ASICs are
 Full custom ASICs
 Semi-custom ASICs
15. Differentiate full custom design and semi-custom design methodologies. (Any 2 points)

16. Write the significance of Clock Tree Synthesis (CTS) in back-end design.
 Clock Tree Synthesis is a technique for distributing the clock equally among all sequential parts of
a VLSI design.
 The main purpose of CTS is to reduce skew and delay
17. List any two applications of digital IC design.
Digital Signal processor, Memory Chips, Programmable IC’s, Microprocessor
18. State the importance of gate delays in digital circuit modeling.
 Gate delays are crucial in digital circuit modeling because they represent the time it takes for a
logic gate to change its output after a change in its input, impacting circuit speed, timing
accuracy, and overall performance.
19. Define the term pass transistor in digital logic design.
 A widely-used alternative to complementary CMOS is pass-transistor logic, which
attempts to reduce the number of transistors required to implement logic by allowing the
primary inputs to drive gate terminals as well as source/drain terminals.
20. Realize a 2-input XOR gate using transmission gates.

PART-B

11 i) With a neat diagram, explain noise margin in CMOS circuits.

 Noise margin is a parameter related to input output characteristics.
 Noise is present in all real systems. This adds random fluctuations to voltages representing logic levels.
 Hence, the voltage ranges defining the logic levels are more tightly constrained at the output of a gate than at
the input.
 Small amounts of noise will not affect the circuit. The maximum noise voltage that can be tolerated by a circuit
is termed its noise immunity (noise Margin).
 It determines voltage on the input so that the output is not affected. There are two types: LOW noise margin,
HIGH noise margin.
 LOW noise margin: is defines as the difference in magnitude between the maximum low output voltage of the driving
gate and the maximum input Low voltage recognized by the driven gate.
NML=|VILmax- VOLmax|
HIGH noise margin: is defined difference in magnitude between minimum High output voltage of the driving gate and
minimum input High voltage recognized by the receiving gate.

ii) Discuss static, dynamic, and short-circuit power dissipation in CMOS circuits.
Static power dissipation:
 Static power is the power consumed when the device is powered up but no signals are changing value.
 In CMOS devices, the static power consumption is due to leakage mechanism.

 This power dissipation is generally categorized into four major types: Sub-threshold leakage, Gate leakage, Gate-induced
drain leakage, and Junction leakage.
 
Dynamic Power Dissipation:

Dynamic power is the power consumed when the device is active, that is, when the signals of the design are changing values.
It is generally categorized into three types:

✓ Switching Power
✓ Short-Circuit Power
✓ Glitching Power

Short-Circuit Power Dissipation:

 In addition to the switching power, short-circuit power also contributes to the dynamic power.

14 ii) Explain DC transfer characteristics of a CMOS inverter and derive equations for each
region of operation.
 In region A, the nMOS transistor is OFF and the pMOS transistor pulls the output to VDD.
 In region B, the nMOS transistor starts to turn ON. It is pulling the output down.
The expression for the NMOS current is
 In region C, both transistors are in saturation.

 In region D, the pMOS transistor is partially ON

 We can apply the same analysis what we did for region B and C and we can obtain the expression for output voltage.
Region E:
 The output in this region is zero because the P device is OFF and n device is ON.
 ii) The drain of an n - channel MOSFET is shorted to the gate so that V gs = Vds. The
threshold voltage (Vt ) of MOSFET is 1 V. If the drain current (Ids ) is 1 mA for Vgs = 2 V,
then for Vgs = 3V, calculate the value of Ids?
Solution:

15 i) Explain front-end and back-end VLSI design flows along with tools used.
Answer:

1. Specification: This is the first stage in the design process where we define the important parameters
of the system that has to be designed into a specification.
2. High level Design: In this stage, various details of the design architecture are defined.
3. Low level Design: This phase is also known as microarchitecture phase. In this phase lower level
design details about each functional block implementation are designed.
4. RTL coding: In RTL coding phase, the micro design is modelled in a Hardware Description
Language like Verilog/VHDL.
5. Functional Verification: Functional Verification is the process of verifying the functional
characteristics of the design by generating different input stimulus.
6. Logic Synthesis: Synthesis is the process in which a synthesis tool like design compiler takes in the
RTL, target technology, and constraints as inputs and maps the RTL.
7. Placement and Routing: Gate-level netlist from the synthesis tool is taken and imported into place
and route tool in the Verilog netlist format.
8. Gate level Simulation: The Placement and Routing tool generates an SDF (Standard Delay File)
that contains timing information of the gates.
9. Fabrication: Once the gate level simulations verify the functional correctness of the gate level
design after the Placement and Routing phase.
10. Post silicon Validation: Once the chip is back from fabrication, it needs to be put in a real test
environment and tested before it can be used widely in the market.

Front End VLSI Design: All of the stages from Specification to Functional Verification are normally
considered as part of Front end.
Back End VLSI Design: All stages from Logic Synthesis till Fabrication are considered as back end

ii) With a neat diagram, explain the FPGA design flow.

Answer:

Design Entry:
 There are different techniques for design entry. Schematic based, Hardware Description
Language and combination of both.
 Selection of a method depends on the design and designer.

Synthesis:

 The process which translates VHDL or Verilog code into a device netlist format.
 Synthesis process will check code syntax and analyze the hierarchy of the design.
Implementation:
This process consists of three steps
1. Translate
2. Map
3. Place and Route
Translate process combines all the input netlists and constraints to a logic design file.
Map process divides the whole circuit with logical elements into sub blocks such that they can be fit
into the FPGA logic blocks.
Place and Route:
The place and route process places the subblocks from the map process into logic blocks according to
the constraints and connects the logic blocks.
Device Programming:
Now the design must be loaded on the FPGA. But the design must be converted to a format so that the
FPGA can accept it.
Design Verification: Verification can be done at different stages of the process steps.
Behavioral Simulation: This is first of all simulation steps; those are encountered throughout the
hierarchy of the design flow.
Functional simulation: Functional simulation gives information about the logic operation of the circuit.
Static Timing Analysis: This can be done after MAP or PAR processes Post MAP timing report lists
signal path delays of the design derived from the design logic.

17. ii) Using ATPG, generate a test vector to detect a stuck-at-0 (S-a-0) fault at net ‘d’ in the
circuit.

Solutions:

18. Describe Built-In Self-Test (BIST) techniques with appropriate diagrams.

 In Built-in self-test (BIST) design, parts of the circuit are used to test the circuit itself.
 Online BIST is used to perform the test under normal operation, whereas off-line BIST is
used to perform the test off-line.
  The essential circuit modules required for BIST include: Pseudo random pattern
generator (PRPG), Output response analyzer (ORA).
 The implementation of both PRPG and ORA can be done with Linear Feedback Shift
Registers (LFSRs).

Pseudo Random Pattern Generator:

 A pseudo random test generator circuit can use an LFSR, as shown in Fig.

Linear Feedback Shift Register as an ORA :- (4 Marks)

 To reduce the chip area penalty, data compression schemes are used to compare the
compacted test responses instead of the entire raw test data.
 One of the popular data compression schemes is the signature analysis, which is
based on the concept of cyclic redundancy checking.
 [Link]) Discuss delay optimization techniques in CMOS design.

 Delay in CMOS circuits affects the overall speed and performance of digital systems. Optimizing this delay is
crucial, and several techniques are commonly used:
1. Transistor Sizing
Increasing the width of transistors reduces resistance, thus decreasing delay.
2. Logical Effort
This method helps choose the optimal gate sizes to minimize delay across stages.
3. Reducing Load Capacitance
Lowering the capacitive load (fan-out or interconnect capacitance) reduces the RC delay.
4. Buffer Insertion
Buffers can be inserted in long interconnect paths to break the RC delay into smaller segments.
5. Technology Scaling
Using smaller technology nodes (e.g., 7nm instead of 45nm) reduces intrinsic delay of
transistors.

21. (i)Explain how testers write test programs and perform silicon debugging.

1. Writing Test Programs

Testers develop test programs to verify the correct functionality and performance of a silicon chip. This process includes:

 Test Vector Generation: Using simulation tools (like ATPG - Automatic Test Pattern Generation), testers create
input patterns and expected outputs to detect faults in the chip (e.g., stuck-at faults, bridging faults).
 Test Bench Development: A test bench is written in HDL (e.g., Verilog or VHDL) to simulate how the chip
responds to different inputs and validate its behavior.
 Built-In Self-Test (BIST): Some designs integrate self-testing mechanisms, where part of the chip generates and
analyzes test patterns internally.
 Scan Chains: Design-for-Testability (DFT) techniques like scan chains are inserted to make internal states
observable and controllable during testing.

2. Performing Silicon Debugging

After fabrication, the real silicon is tested and debugged to catch any issues that weren’t visible during simulation. This
includes:

 Post-Silicon Validation: Engineers validate chip functionality under real-world conditions (voltage, temperature,
frequency) using lab instruments.
 Probing and Signal Tracing: Tools like logic analyzers and oscilloscopes help observe internal signals using on-
chip debug infrastructure (e.g., JTAG, embedded logic analyzers).
 Failure Analysis: If mismatches or failures occur, engineers identify the root cause using scan dump analysis,
pattern failing logs, or layout inspection.
22. Explain the Design for Testability (DFT) strategy with necessary diagrams and detailed
explanation.
 Test engineers usually have to construct test vectors after the design is completed.
 This invariably requires a substantial amount of time and effort that could be avoided if testing
is considered early in the design flow to make the design more testable.
 To structurally test circuits, we need to control and observe logic values of internal lines.
 Many DFT techniques have been proposed since that time. DFT techniques generally fall into
one of the following three categories: (1) ad hoc DFT techniques, (2) level-sensitive scan design
(LSSD) or scan design, or (3) built-in self-test (BIST).
 Ad hoc methods were the first DFT techniques introduced in the 1970s.
 The goal was to target only those portions of the circuit that would be difficult to test and to add
circuitry to improve the controllability or observability.
 Ad hoc techniques typically use test point insertion to access internal nodes directly.
 Level-sensitive scan design, also referred to as scan design, was the next, and most important,
DFT technique proposed. LSSD is latch based.
 In a flip-flop-based scan design, testability is improved by adding extra logic to each flip-flop in
the circuit to form a shift register, or scan chain.

Figure: Ad hoc DFT test points using multiplexers

 As a result, LSSD reduces the problem of testing sequential logic to that of testing combinational
logic and thereby facilitates the use of ATPG developed for combinational logic.
 Built-in self-test was proposed to integrate a test-pattern generator (TPG) and an output response
analyzer (ORA) in the VLSI device to perform testing internal to the IC.
 Because the test circuitry resides with the CUT, BIST can be used at all levels of testing, from
wafer through system-level testing.
23. Explain how the boundary scan technique aids in testing complex chips, particularly
where physical access to I/O pins is limited.
Answer:
 Boundary scan, based on the basic idea of scan design, inserted logic to provide a scan path
through all I/O buffers of ICs to assist in testing the assembled PCB.
 It is a technique to test the interconnections between different components on a chip.
 The scan chain provides the ability to shift in test vectors to be applied through the pad to the
pins and interconnections on the PCB.
 Thus, boundary scan provides access to the various signal nodes on a PCB without the need for
physical probes.
 In addition to testing the interconnections on the PCB, the boundary scan interface also provides
access to DFT features, such as LSSD or BIST, designed and implemented in the VLSI devices
for board and system-level testing.
 The boundary scan description language (BSDL) provides a mechanism with which IC
manufacturers can describe testability features in a chip.

Figure: Basic boundary scan cell applied to a bidirectional buffer

Table: Boundary Scan Four-Wire Interface

 Scan is the internal modification of the design’s circuitry to increase its test-ability.
 ATPG stands for Automatic Test Pattern Generation; as the name suggests, this is basically the
generation of test patterns.

Figure: A typical sequential circuit (before scan insertion)

 The goal of ‘Scan Insertion’ is to make a difficult-to-test sequential circuit behave (during testing
process) like an easier-to-test combinational circuit. Achieving this goal involves two steps –
 Converting Regular Flop to Scan Flop
 Stitching the Scan Flops to form Scan Chains
 The expected responses along with the patterns are then stored in the memory of Automatic Test
Equipment (ATE).
 In post-silicon, the manufactured chip is tested using the ATE, which loads the pattern and compares it
with the expected response for pass or fail status.