1. Draw the VLSI Design Flow chart.
2. Mention any four advantages of CMOS technology.
Low static power consumption
High noisy immunity
Reduce the complexity of the circuit.
The high density of the logic functions on a chip.
3. What are the benefits of SOI technology relative to conventional bulk
CMOS technology?
Reduced Parasitic Capacitance
Lower Power Consumption
Higher Performance
Better Scalability
4. What are the purposes of photolithography and packaging?
• Photolithography:
• It is used to transfer intricate circuit patterns onto the silicon wafer using light
and a photoresist material.
• It defines the shapes and structures of transistors, interconnects, and other
components with high precision.
Packaging:
• It protects the fabricated IC from physical damage, moisture, and
contaminants.
• It provides electrical connections between the IC and the external circuit,
ensuring proper functionality.
5. Define channel length modulation with its derivation.
The depletion layer increases at the drain as the drain voltage is increased.
This leads to a shorter channel length and the drain current increases by a
factor of (1 +λVds).This is called Channel length modulation.
6. What is meant by body effect and write the derivation.
Vt is not constant with respect to voltage difference between substrate and
source of transistor. This is known as body effect. It is otherwise known as
substrate-bias effect.
7. State the significance of SPICE MOSFET Models.
SPICE (Simulation Program with Integrated Circuit Emphasis) provides an
accurate representation of transistor behavior, enabling designers to simulate
circuits before fabrication.
➢ Accurate Circuit Simulation
➢ Device and Process Optimization
➢ Power and Reliability Analysis
8. Differentiate the procedural assignments and conditional statements.
Procedural Assignments:
• Used within always and initial blocks.
• Assign values to variables (reg, integer, etc.).
Example:
always @(posedge clk)
q <= d; // Non-blocking assignment
Conditional Statements:
• Used for decision-making.
• Includes if-else and case statements.
Example:
always @(a or b) begin
if (a > b)
y = a;
else
y = b;
end
9. List the various operators in Verilog HDL.
Types of operators are:
Arithmetic, Relational, Equality, Logical, Bitwise, Reduction, Shift, Conditional,
concatenation and Replication operators.
10. Write the Verilog HDL code for full adder using mixed style modeling.
module full_adder (
input wire A, B, Cin,
output wire Sum, Cout);
// Using Dataflow modeling for Sum
assign Sum = A ^ B ^ Cin;
// Using Structural modeling for Carry-out
wire w1, w2, w3;
and (w1, A, B);
and (w2, B, Cin);
and (w3, A, Cin);
or (Cout, w1, w2, w3);
endmodule
11. Give the benefits of Hardware Description Language.
Reusability
Flexibility
Lower costs
Better simulation
12. Differentiate dry oxidation and wet oxidation in CMOS fabrication
technologies.
13. Mention the types of Interconnect used in integrated circuits
• Metal Interconnects
• Silicon-Based Interconnects
• Graphene and Carbon Nanotube Interconnects
14. How the packaging concepts used in IC fabrication.
• It protects the fabricated IC from physical damage, moisture, and
contaminants.
• It provides electrical connections between the IC and the external
circuit, ensuring proper functionality.
15. List the two types of layout design rules.
The two major types of layout design are
Lambda design rule
Micron rule
16. What are value sets in Verilog HDL?
17. List any four bitwise operators used in Verilog.
18. What will be the output of the following code?
always (@ A or B)
begin
A = 1;
B =2;
#10;
A <= B;
B<=A;
end
Answer: The operator “< =” represents non-blocking statement assignments.
After the execution of the given Verilog code, A will get assigned the value of
B and B will get assigned the value of A.
A = 2, B =1
PART-B
1. Draw and explain the different phases of VLSI design flow.
Front-end design (Logical design):
1. Design entry – Enter the design in to an ASIC design system using
a hardware description language (HDL) or schematic entry
2. Logic synthesis – Generation of net list (logic cells and their
connections) from HDL code.
Logic synthesis consists of following steps: (i) Technology independent
Logic optimization (ii)Translation (iii) Technology mapping or
Library binding
3. System partitioning - Divide a large system into ASIC-sized pieces
4. Pre-layout simulation - Check to see if the design functions
correctly. Gate level functionality and timing details can be verified.
Back-end design (Physical design):
5. Floor planning - Arrange the blocks of the netlist on the chip
6. Placement - Decide the locations of cells in a block
7. Routing - Make the connections between cells and blocks
8. Circuit Extraction - Determine the resistance and capacitance of
the interconnect
9. Post-layout simulation - Check to see the design still works with
the added loads of the interconnect
2. Explain the concepts and write the Verilog HDL coding for combinational
logic circuits for the following:
a. Binary to Gray code converter
➢ The MSB (Most Significant Bit) of the Gray code is the same as the MSB
of the binary number.
➢ Each subsequent Gray code bit is obtained by XORing the previous binary
bit with the current binary bit.
Verilog Code:
module bg (binary, gray);
input [3:0] binary;
output [3:0] gray;
assign gray[3] = binary[3]; // MSB remains the same
assign gray[2] = binary[3] ^ binary[2]; // XOR operation
assign gray[1] = binary[2] ^ binary[1];
assign gray[0] = binary[1] ^ binary[0];
endmodule.
b. Multiplexer
A Multiplexer (MUX) is a combinational logic circuit that selects one
input from multiple inputs and forwards it to the output based on a selection line(s). It
acts as a data selector, allowing multiple input signals to share a single output
channel.
Verilog Code:
module mux(sel,i0,i1,y);
input sel;
input i0, i1,
output y;
assign y = sel ? i1 : i0;
endmodule
3. Explain in detail about conditional statements in Behavioral modelling.
a. if-else Statement
• Used to execute a block of code when a condition is true.
• If the condition is false, the else block (if present) executes.
Syntax:
if (condition)
statement1;
else
statement2;
b. if-else if-else Ladder
• Used for multiple conditions, executing the first true condition.
c. case Statement
• Efficient alternative to multiple if-else conditions.
Syntax:
case (expression)
value1: statement1;
value2: statement2;
default: statement3;
endcase
4. Summarize the various design rule background in layout design rules.
There are primarily two approaches in describing the design rules.
1. Scalable Design Rules (e.g. SCMOS, λ-based design rules):
In this approach, all rules are defined in terms of a single parameter λ. The
rules are so chosen that a design can be easily ported over a cross section of
industrial process.
2. Absolute Design Rules (e.g. μ-based design rules):
In this approach, the design rules are expressed in absolute dimension and therefore
can exploit the features of a given process to a maximum degree
➢ Lambda-based (scalable CMOS) design rules define scalable rules based on
λ (which is half of the minimum channel length).
➢ Design rules based on single parameter, λ.
➢ Simple for the designer.
5. Write the concepts MOS transistor.
NMOS Transistor:
• Four terminals: gate, source, drain, body
• Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS) capacitor
Source Gate Drain
Polysilicon
SiO2
n+ n+
p bulk Si
PMOS Transistor:
• Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
6. Derive the ideal IV equation for MOS transistor in different regions of
operation.
NMOS Linear I-V
NMOS Saturation I-V
Summary of NMOS I-V characteristics:
7. Explain the Metallization processes in CMOS fabrication.
It involves the following key steps:
1. Metal Deposition – A thin metal layer (typically aluminum or copper) is deposited
using techniques like Physical Vapor Deposition (PVD) or Chemical Vapor
Deposition (CVD).
2. Patterning – Photolithography and etching define the metal interconnects by
removing unwanted metal regions.
3. Dielectric Deposition – An insulating layer (such as silicon dioxide) is deposited over
the metal to prevent short circuits and enable multi-layer connections.
4. Chemical Mechanical Polishing (CMP) – This step smoothens the surface for
subsequent metal layers, crucial for multi-level metallization.
8. With suitable diagram, describe the n-well CMOS fabrication process.
Step 1: Start with blank wafer
First step will be to form the n-well
Step 2: Oxidation
Step 3: Photoresist
• Spin on photoresist – Photoresist is a light-sensitive organic polymer
Step 4: Lithography
• Expose photoresist through n-well mask.
• Strip off exposed photoresist.
Step 10: Metallization
9. For the transistor M1 in the circuit shown in the figure, µ𝒏𝑪𝐨𝐱 = 𝟏𝟎𝟎 µ𝐀/𝐕𝟐
and (𝑾⁄𝑳) = 𝟏𝟎, where µ𝒏 is the mobility of electron, 𝑪𝐨𝐱 is the oxide
capacitance per unit area, 𝑾 is the width and 𝑳 is the length.
The channel length modulation coefficient is ignored. If the gate-to-source
voltage 𝑽𝐆𝐒 is 1 V to keep the transistor at the edge of saturation, then find the
threshold voltage of the transistor?
SOLUTIONS:
10. Explain the concepts and write the Verilog HDL codes for combinational
logic circuits for the following: [Link] to Gray code converter [Link] carry
adder
[Link] to Gray code converter
➢ The MSB (Most Significant Bit) of the Gray code is the same as the MSB
of the binary number.
➢ Each subsequent Gray code bit is obtained by XORing the previous binary
bit with the current binary bit.
Verilog Code:
module bg (binary, gray);
input [3:0] binary;
output [3:0] gray;
assign gray[3] = binary[3]; // MSB remains the same
assign gray[2] = binary[3] ^ binary[2]; // XOR operation
assign gray[1] = binary[2] ^ binary[1];
assign gray[0] = binary[1] ^ binary[0];
endmodule.
[Link] carry adder
A Ripple Carry Adder (RCA) is a type of combinational circuit used for binary
addition. It consists of multiple full adders (FA) connected in series, where the carry
output from one stage serves as the carry input to the next stage.
Verilog Code:
module full_adder(a, b, cin, s, cout);
input a,b, cin;
output s, cout;
assign s = a ^ b ^ cin;
assign cout = ((a ^ b) & cin) | (a & b);
endmodule
module ripple carry adder(a, b, s, cout);
input [3:0] a;
input [3:0] b;
output [3:0] s;
output cout;
wire c1, c2, c3;
full_adder fa0(a[0], b[0], 0, s[0], c1);
full_adder fa1(a[1], b[1], c1, s[1], c2);
full_adder fa2(a[2], b[2], c2, s[2], c3);
full_adder fa3(a[3], b[3], c3, s[3], cout);
endmodule
11. Explain the concepts and write the Verilog HDL coding for combinational
logic circuits for the following: [Link] [Link] encoder
[Link]
[Link]
A Multiplexer (MUX) is a combinational logic circuit that selects one
input from multiple inputs and forwards it to the output based on a selection line(s). It
acts as a data selector, allowing multiple input signals to share a single output
channel.
Verilog Code:
module mux(sel,i0,i1,y);
input sel;
input i0, i1,
output y;
assign y = sel ? i1 : i0;
endmodule
[Link] encoder
module priorityencoder(en,i,y);
input en;
input [7:0]i;
output reg [2:0]y;
always @(en,i)
begin
if(en==1)
begin
if(i[7]==1) y=3'b111;
else if(i[6]==1) y=3'b110;
else if(i[5]==1) y=3'b101;
else if(i[4]==1) y=3'b100;
else if(i[3]==1) y=3'b011;
else if(i[2]==1) y=3'b010;
else if(i[1]==1) y=3'b001;
else
y=3'b000;
end
else y=3'bzzz;
end
endmodule
[Link]
module demux(sel,i, y0, y1);
input sel;
input i;
output y0, y1;
assign {y0,y1} = sel?{1'b0,i}: {i,1'b0};
endmodule
12. Compare the SPICE MOSFET models with different types.
Level 1 (Simplified Model):
• Complexity: Simple and computationally efficient.
• Accuracy: Less accurate for modern MOSFETs, as it uses a basic quadratic equation
for the drain current.
Level 2 (Improved Model):
• Complexity: More complex than Level 1, includes better approximation of current-
voltage characteristics.
• Accuracy: More accurate than Level 1, as it introduces channel-length modulation
and other non-ideal effects.
Level 3 (Advanced Model):
• Complexity: Much more complex, with many parameters to model secondary effects
like mobility degradation, thermal effects, and velocity saturation.
• Accuracy: Highly accurate and suitable for modern MOSFETs and analog design.
13. Discuss wafer fabrication and metallization in CMOS fabrication.
Wafer fabrication
➢ Basic raw material used for manufacturing IC is Wafer or Disk of Silicon.
➢ Wafer- very thin slice of semiconductor is used for IC fabrication.
➢ Here the wafers are cut from ingots of single crystal Silicon, which has been
pulled from crucible melt of pure molten polycrystaline Silicon. This is known
as chochralski method.
Metallization
It involves the following key steps:
1. Metal Deposition – A thin metal layer (typically aluminum or copper) is deposited
using techniques like Physical Vapor Deposition (PVD) or Chemical Vapor
Deposition (CVD).
2. Patterning – Photolithography and etching define the metal interconnects by
removing unwanted metal regions.
14. In the circuit shown in the figure, the transistors M1 and M2 are operating in
saturation. The channel length modulation coefficients of both the transistors are
non-zero. The transconductance of the MOSFETs M1 and M2 are gm1 and gm2,
respectively, and the internal resistance of the MOSFETs M1 and M2 are r01 and
r02, respectively.
Ignoring the body effect, calculate the ac small signal voltage gain (∂Vout⁄∂Vin) of the
circuit.
Solutions: