UNIT 2

Elements of Iot

1. Sensing
The first step in IoT workflow is gathering information at a “point of activity.” This can be
information captured by an appliance, a wearable device, a wall-mounted control or any number
of commonly found devices. The sensing can be biometric, biological, environmental, visual or
audible (or all the above). The unique thing in the context of IoT is that the device doing the
sensing is not one that typically gathered information in this way. Sensing technology specific to
this purpose is required.
2. Communication
This is where things start to get interesting. Many of the new IoT devices we are seeing today are
not designed for optimal communication with cloud services. IoT devices require a means for
transmitting the information sensed at the device level to a Cloud-based service for subsequent
processing. This is where the great value inherent in IoT is created. This requires either WiFi
(wireless LAN based communications) or WAN (wide area network… i.e.
cellular) communications. In addition, depending on the need short-range communication, other
capabilities may also be needed. These could include Bluetooth, ZigBee, Near-field or a range of
other short-range communication methods. For positioning, GPS is often required as well.
3. Cloud-Based Capture & Consolidation
Gathered data is transmitted to a cloud-based service where the information coming in from the
IoT device is aggregated with other cloud-based data to provide useful information for the end
user. The data being consolidated can be information from other internet sources as well as from
others subscribing with similar IoT devices. Most often, there will be some data processing
required to provide useful information that is not necessarily obvious in the raw data.
4. Delivery of Information
The last step is the delivery of useful information to the end user. That may be a consumer, a
commercial or an industrial user. It may also be another device in the M2M workflow. The goal
in a consumer use case is to provide the information in as simple and transparent a method as
possible. It requires execution of a well thought out, designed and executed user interface that
provides an optimized experience across multiple device platforms – tablets, smartphones,
desktop – across multiple operating systems – iOS, Android, Windows, etc.

Hardware components;
The hardware utilized in IoT systems includes devices for a remote dashboard, devices for
control, servers, a routing or bridge device, and sensors. These devices manage key tasks and
functions such as system activation, action specifications, security, communication, and
detection to support-specific goals and actions.
IoT − Sensors
The most important hardware in IoT might be its sensors. These devices consist of energy
modules, power management modules, RF modules, and sensing modules. RF modules manage
communications through their signal processing, WiFi, ZigBee, Bluetooth, radio transceiver,
duplexer, and BAW.

The sensing module manages sensing through assorted active and passive measurement devices.
Here is a list of some of the measurement devices used in IoT –

[Link] Devices

1. accelerometers temperature sensors

2. magnetometers proximity sensors

3. gyroscopes image sensors

4. acoustic sensors light sensors

5. pressure sensors gas RFID sensors

6. humidity sensors micro flow sensors

Wearable Electronics
Wearable electronic devices are small devices worn on the head, neck, arms, torso, and feet.

Smartwatches not only help us stay connected, but as a part of an IoT system, they allow access
needed for improved productivity.

Current smart wearable devices include −

 Head − Helmets, glasses

 Neck − Jewelry, collars
 Arm − Watches, wristbands, rings
 Torso − Clothing, backpacks
 Feet − Socks, shoes

Smart glasses help us enjoy more of the media and services we value, and when part of an IoT
system, they allow a new approach to productivity.

Standard Devices
The desktop, tablet, and cellphone remain integral parts of IoT as the command center and
remotes.
 The desktop provides the user with the highest level of control over the system and its
settings.
  The tablet provides access to the key features of the system in a way resembling the
desktop, and also acts as a remote.
 The cellphone allows some essential settings modification and also provides remote
functionality.
Other key connected devices include standard network devices like routers and switches.

ARM cortex-A class processor

The ARM Cortex-A is a group of 32-bit and 64-bit RISC ARM processor cores licensed
by Arm Holdings. The cores are intended for application use. The group consists of 32-bit
cores: ARM Cortex-A5, ARM Cortex-A7, ARM Cortex-A8, ARM Cortex-A9, ARM Cortex-
A12, ARM Cortex-A15, ARM Cortex-A17 MPCore, and ARM Cortex-A32, and 64-bit
cores: ARM Cortex-A34, ARM Cortex-A35, ARM Cortex-A53, ARM Cortex-A55, ARM
Cortex-A57, ARM Cortex-A72, ARM Cortex-A73, ARM Cortex-A75, ARM Cortex-A76, ARM
Cortex-A77, ARM Cortex-A78, ARM Cortex-A510 and ARM Cortex-A710.
The 32-bit ARM Cortex-A cores, except for the Cortex-A32, implement the ARMv7-A profile of
the ARMv7 architecture. The main distinguishing feature of the ARMv7-A profile, compared to
the other two profiles, the ARMv7-R profile implemented by the ARM Cortex-R cores and the
ARMv7-M profile implemented by most of the ARM Cortex-M cores, is that only the ARMv7-A
profile includes a memory management unit (MMU). Many modern operating systems require a
MMU to run.
The 64-bit ARM Cortex-A cores as well as the 32-bit ARM Cortex-A32 implement the ARMv8-
A profile of the ARMv8 architecture.
ARM license
ARM Holdings neither manufactures nor sells CPU devices based on its own designs, but rather
licenses the processor architecture to interested parties. ARM offers a variety of licensing terms,
varying in cost and deliverables. To all licensees, ARM provides an integratable hardware
description of the ARM core, as well as complete software development toolset, and the right to
sell manufactured silicon containing the ARM CPU.
Silicon customization
Integrated device manufacturers (IDM) receive the ARM
processor IP as synthesizable RTL (written in Verilog). In this form, they have the ability to
perform architectural level optimizations and extensions. This allows the manufacturer to
achieve custom design goals, such as higher clock speed, very low power consumption,
instruction set extensions, optimizations for size, debug support, etc. To determine which
components have been included in an ARM IC chip, consult the manufacturer datasheet and
related documentation.
Instruction sets
The Cortex-A5 / A7 / A8 / A9 / A12 / A15 / A17 cores implement the ARMv7-A
architecture. The Cortex-A32 / A34 / A35 / A53 / A57 / A72 / A73 cores implement the
ARMv8-A architecture. The Cortex-A55 / A65 / A75 / A76 / A77 / A78 cores implement the
ARMv8.2-A architecture. The Cortex-A510 and A710 cores implement the ARMv9-A
architecture.

64-bit

Year Core

2012 Cortex-A53

2012 Cortex-A57

2015 Cortex-A35

2015 Cortex-A72

2016 Cortex-A34

2016 Cortex-A73

2017 Cortex-A55

2017 Cortex-A75

2018 Cortex-A76

2018 Cortex-A65AE

2018 Cortex-A76AE

2019 Cortex-A77

2020 Cortex-A78
 2021 Cortex-A510

2021 Cortex-A710

ARM cortex-M class processor

The ARM Cortex-M is a group of 32-bit RISC ARM processor cores licensed by Arm
Holdings. These cores are optimized for low-cost and energy-efficient integrated circuits, which
have been embedded in tens of billions of consumer devices.] Though they are most often the
main component of microcontroller chips, sometimes they are embedded inside other types of
chips too. The Cortex-M family consists of Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M3,
Cortex-M4, Cortex-M7, Cortex-M23, Cortex-M33, Cortex-M35P, Cortex-M55. The Cortex-M4 /
M7 / M33 / M35P / M55 cores have an FPU silicon option, and when included in the silicon
these cores are sometimes known as "Cortex-Mx with FPU" or "Cortex-MxF", where 'x' is the
core variant.

The ARM Cortex-M family are ARM microprocessor cores which are designed for use
in microcontrollers, ASICs, ASSPs, FPGAs, and SoCs. Cortex-M cores are commonly used as
dedicated microcontroller chips, but also are "hidden" inside of SoC chips as power management
controllers, I/O controllers, system controllers, touch screen controllers, smart battery
controllers, and sensors controllers.
The main difference from the Cortex-A core is that there is no memory management
unit (MMU). A full-fledged operating system does not normally run on this class of processor.
Though 8-bit microcontrollers were very popular in the past, Cortex-M has slowly been chipping
away at the 8-bit market as the prices of low-end Cortex-M chips have moved downward.
Cortex-M have become a popular replacements for 8-bit chips in applications that benefit from
32-bit math operations, and replacing older legacy ARM cores such as ARM7 and ARM9.
License
Arm Holdings neither manufactures nor sells CPU devices based on its own designs, but rather
licenses the processor architecture to interested parties. Arm offers a variety of licensing terms,
varying in cost and deliverables. To all licensees, Arm provides an integratable hardware
description of the ARM core, as well as complete software development toolset and the right to
sell manufactured silicon containing the ARM CPU.
Silicon customization
Integrated Device Manufacturers (IDM) receive the ARM
Processor IP as synthesizable RTL (written in Verilog). In this form, they have the ability to
perform architectural level optimizations and extensions. This allows the manufacturer to
achieve custom design goals, such as higher clock speed, very low power consumption,
instruction set extensions (including floating point), optimizations for size, debug support, etc.
To determine which components have been included in a particular ARM CPU chip, consult the
manufacturer datasheet and related documentation.
Some of the silicon options for the Cortex-M cores are:

 SysTick timer: A 24-bit system timer that extends the functionality of both the processor and
the Nested Vectored Interrupt Controller (NVIC). When present, it also provides an
additional configurable priority SysTick interrupt. Though the SysTick timer is optional, it is
very rare to find a Cortex-M microcontroller without it. If a Cortex-M33 microcontroller has
the Security Extension option, then it has two SysTicks, one Secure and one Non-secure.
 Bit-Band: Maps a complete word of memory onto a single bit in the bit-band region. For
example, writing to an alias word will set or clear the corresponding bit in the bit-band
region. This allows every individual bit in the bit-band region to be directly accessible from a
word-aligned address. In particular, individual bits can be set, cleared, or toggled from C/C+
+ without performing a read-modify-write sequence of instructions. Though the bit-band is
optional, it is less common to find a Cortex-M3 and Cortex-M4 microcontroller without it.
Some Cortex-M0 and Cortex-M0+ microcontrollers have bit-band.
 Memory Protection Unit (MPU): Provides support for protecting regions of memory through
enforcing privilege and access rules. It supports up to eight different regions, each of which
can be split into a further eight equal-size sub-regions.
 Tightly-Coupled Memory (TCM): Low-latency RAM that is used to hold critical routines,
data, stacks. Other than cache, it is typically the fastest RAM in the microcontroller.

Cortex-M0 processor Instruction set

The Arm Cortex-M0 processor is one of the smallest Arm processors available.

The Cortex-M0 has an exceptionally small silicon area, low power and minimal code footprint,
enabling developers to achieve 32-bit performance at an 8-bit price point, bypassing the step to
16-bit devices. The ultra-low gate count of the processor enables its deployment in analog and
mixed signal devices.

Architecture- Armv6-M

Bus Interface- AMBA 3 AHB-Lite, Von Neumann bus architecture

ISA Support- Thumb or Thumb-2 subset

ISA options- Options of single cycle or area optimized 32-x32 multiplier

Pipeline- 3-stages

SysTick timer- Optional SysTick (24-bit)

Interrupts- Integrated Nested Vectored Interrupt Controller (NVIC) supporting 1 to 32 physical
interrupts and Non-maskable Interrupt (NMI), 4 priority levels per interrupt.

Wakeup Interrupt Controller- Optional WIC for waking up the processor from state retention
power gating or when all clocks are stopped.

The implemented device provides:

A low gate count processor that features:

 The ARMv6-M Thumb instruction set.

 Thumb-2 technology
 Optionally, an ARMv6-M compliant 24-bit SysTick timer.
 A 32-bit hardware multiplier. This can be the standard single-cycle multiplier, or
a 32-cycle multiplier that has a lower area and performance implementation.
 The system interface supports either little-endian or byte invariant big-endian data
accesses.
 The ability to have deterministic, fixed-latency, interrupt handling.
 Load/store-multiples and multicycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling.
 C Application Binary Interface compliant exception [Link] is the ARMv6-
M, C Application Binary Interface (C-ABI) compliant exception model that enables
the use of pure C functions as interrupt handlers.
 Low power sleep-mode entry using Wait For Interrupt (WFI), Wait For
Event (WFE) instructions, or the return from interrupt sleep-on-exit feature.

 NVIC that features:

 1, 2, 4, 8, 16, 24, or 32 external interrupt inputs, each with four levels of priority

 dedicated Non-Maskable Interrupt (NMI) input

  support for both level-sensitive and pulse-sensitive interrupt lines

 optional Wake-up Interrupt Controller (WIC), providing ultra-low power sleep

mode support.

 Optional debug support:

 Zero to four hardware breakpoints.

 Zero to two watchpoints.

 Program Counter Sampling Register (PCSR) for non-intrusive code profiling, if

at least one hardware data watchpoint is implemented.

 Single step and vector catch capabilities.

 Support for unlimited software breakpoints using BKPT instruction.

 Non-intrusive access to core peripherals and zero-waitstate system slaves through

a compact bus matrix. A debugger can access these devices, including memory, even
when the processor is running.

 Full access to core registers when the processor is halted.

 Optional, low gate-count CoreSight compliant debug access through a Debug

Access Port (DAP) supporting either Serial Wire or JTAG debug connections.

 Bus interfaces:

 single 32-bit AMBA-3 AHB-Lite system interface that provides simple

integration to all system peripherals and memory

 single 32-bit slave port that supports the DAP.

Cortex-M0 processor Instruction set;

Note:

 angle brackets, <>, enclose alternative forms of the operand

 braces, {}, enclose optional operands and mnemonic parts

 the Operands column is not exhaustive.

For more information on the instructions and operands, see the instruction descriptions.
Intrinsic functions:
ISO/IEC C code cannot directly access some Cortex-M0 instructions. This section describes
intrinsic functions that can generate these instructions, provided by the CMSIS and that might be
provided by a C compiler. If a C compiler does not support an appropriate intrinsic function, you
might have to use inline assembler to access the relevant instruction.

The CMSIS provides the following intrinsic functions to generate instructions that ISO/IEC C
code cannot directly access:
The CMSIS also provides a number of functions for accessing the special registers
using MRS and MSR instructions:

Operands

An instruction operand can be an ARM register, a constant, or another instruction-

specific parameter. Instructions act on the operands and often store the result in a
destination register. When there is a destination register in the instruction, it is usually
specified before the other operands.

Operands
An instruction operand can be an ARM register, a constant, or another instruction-specific
parameter. Instructions act on the operands and often store the result in a destination register.
When there is a destination register in the instruction, it is usually specified before the other
operands.

Restrictions when using PC or SP

Many instructions are unable to use, or have restrictions on whether you can use, the PC or SP
for the operands or destination register. See instruction descriptions for more information.

Shift Operations
Register shift operations move the bits in a register left or right by a specified number of bits,
the shift length.
Register shift can be performed directly by the instructions ASR, LSR, LSL,and ROR and the
result is written to a destination [Link] permitted shift lengths depend on the shift type and
the instruction, see the individual instruction description. If the shift length is 0, no shift occurs.
Register shift operations update the carry flag except when the specified shift length is 0. The
following sub-sections describe the various shift operations and how they affect the carry flag. In
these descriptions, Rm is the register containing the value to be shifted, and n is the shift length.

ASR

Arithmetic shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right
by n places, into the right-hand 32-n bits of the result, and it copies the original bit[31] of the
register into the left-hand n bits of the result.

You can use the ASR operation to divide the signed value in the register Rm by 2n, with the result
being rounded towards [Link] the instruction is ASRS the carry flag is updated
to the last bit shifted out, bit[n-1], of the register Rm.
Note
 If n is 32 or more, then all the bits in the result are set to the value of bit[31]
of Rm.
 If n is 32 or more and the carry flag is updated, it is updated to the value of
bit[31] of Rm.

LSR

Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right
by n places, into the right-hand 32-n bits of the result, and it sets the left-hand n bits of the result
to 0. You can use the LSR operation to divide the value in the register Rm by 2n, if the value is
regarded as an unsigned [Link] the instruction is LSRS, the carry flag is updated to the
last bit shifted out, bit[n-1], of the register Rm.
Note
 If n is 32 or more, then all the bits in the result are cleared to 0.
 If n is 33 or more and the carry flag is updated, it is updated to 0.
LSL

Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left
by n places, into the left-hand 32-n bits of the result, and it sets the right-hand n bits of the result
to 0.

You can use the LSL operation to multiply the value in the register Rm by 2n, if the value is
regarded as an unsigned integer or a two's complement signed integer. Overflow can occur
without warning.

When the instruction is LSLS the carry flag is updated to the last bit shifted out, bit[32-n], of the
register Rm. These instructions do not affect the carry flag when used with LSL #0.
Note
 If n is 32 or more, then all the bits in the result are cleared to 0.
 If n is 33 or more and the carry flag is updated, it is updated to 0.

ROR
Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places,
into the right-
hand 32-n bits of the result, and it moves the right-hand n bits of the register into the left-
hand n bits of the result. When the instruction is RORS the carry flag is updated to the last bit
rotation, bit[n-1], of the register Rm.
Note
 If n is 32, then the value of the result is same as the value in Rm, and if the carry flag is
updated, it is updated to bit[31] of Rm.
 ROR with shift length, n, greater than 32 is the same as ROR with shift length n-32.
Address alignment

An aligned access is an operation where a word-aligned address is used for a word, or multiple
word access, or where a halfword-aligned address is used for a halfword access. Byte accesses
are always aligned.

There is no support for unaligned accesses on the Cortex-M0 processor. Any attempt to perform
an unaligned memory access operation results in a HardFault exception.

PC-relative expressions
A PC-relative expression or label is a symbol that represents the address of an instruction or
literal data. It is represented in the instruction as the PC value plus or minus a numeric offset.
The assembler calculates the required offset from the label and the address of the current
instruction. If the offset is too big, the assembler produces an error.

ARM and thumb instruction set

ARM instructions are 32 bits wide. Thumb instructions are 16 or 32-bits wide.
The ARM instruction set is a set of 32-bit instructions providing a comprehensive range of
operations.ARMv4T and later define a 16-bit instruction set called Thumb. Most of the
functionality of the 32-bit ARM instruction set is available, but some operations require more
instructions. The Thumb instruction set provides better code density, at the expense of
performance.

ARMv6T2 introduces Thumb-2 technology. This is a major enhancement to the Thumb

instruction set by providing 32-bit Thumb instructions. The 32-bit and 16-bit Thumb instructions
together provide almost exactly the same functionality as the ARM instruction set. This version
of the Thumb instruction set achieves the high performance of ARM code along with the benefits
of better code density.

ARMv7 includes Thumb-2 technology. ARMv7-M only supports the Thumb instruction set.
Therefore, interworking instructions in ARMv7-M must not attempt to change to ARM state.
ARMv7-R supports both ARM and Thumb instruction sets.
ARMv7 defines the Thumb Execution Environment (ThumbEE). The ThumbEE instruction set is
based on Thumb, with some changes and additions to make it a better target for dynamically
generated code, that is, code compiled on the device either shortly before or during execution.