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TCA9546A
SCPS205A – APRIL 2014 – REVISED FEBRUARY 2015

TCA9546A Low Voltage 4-Channel I2C and SMBus Switch with Reset Function
1 Features 2 Applications
•
1 1-of-4 Bidirectional Translating Switches • Servers
• I2C Bus and SMBus Compatible • Routers (Telecom Switching Equipment)
• Active-Low Reset Input • Factory Automation
• Three Address Pins, Allowing up to Eight • Products With I2C Slave Address Conflicts (e.g.
TCA9546A Devices on the I2C Bus Multiple, Identical Temp Sensors)
• Channel Selection Via I2C Bus, in Any
Combination 3 Description
• Power-up With All Switch Channels Deselected The TCA9546A is a quad bidirectional translating
switch controlled via the I2C bus. The SCL/SDA
• Low RON Switches upstream pair fans out to four downstream pairs, or
• Allows Voltage-Level Translation Between channels. Any individual SCn/SDn channel or
1.8-V, 2.5-V, 3.3-V, and 5-V Buses combination of channels can be selected, determined
• No Glitch on Power-up by the contents of the programmable control register.
• Supports Hot Insertion An active-low reset (RESET) input allows the
• Low Standby Current TCA9546A to recover from a situation in which one of
the downstream I2C buses is stuck in a low state.
• Operating Power-Supply Voltage Range of 1.65 V Pulling RESET low resets the I2C state machine and
to 5.5 V causes all the channels to be deselected, as does the
• 5.5 V Tolerant Inputs internal power-on reset function.
• 0 to 400-kHz Clock Frequency The pass gates of the switches are constructed such
• Latch-Up Performance Exceeds 100 mA Per that the VCC pin can be used to limit the maximum
JESD 78 high voltage, which will be passed by the TCA9546A.
• ESD Protection Exceeds JESD 22 This allows the use of different bus voltages on each
pair, so that 1.8-V, 2.5-V, or 3.3-V parts can
– 4000-V Human-Body Model (A114-A) communicate with 5-V parts without any additional
– 1500-V Charged-Device Model (C101) protection. External pull-up resistors pull the bus up
to the desired voltage level for each channel. All I/O
pins are 5.5-V tolerant.

Device Information (1)

DEVICE NAME PACKAGE BODY SIZE (NOM)
TSSOP (16) 5.00 mm x 4.40 mm
TCA9546A
SOIC (16) 9.90 mm x 3.91 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

4 Simplified Application Diagram

VCC Channel 0
SDA SD0 Slaves A0, A1...AN
I2C or SMBus SCL SC0
Master
Channel 1
(e.g. Processor) SD1
RESET Slaves B0, B1...BN
SC1

TCA9546A
Channel 2
SD2 Slaves C0, C1...CN
A0
SC2
A1
A2
Channel 3
GND
SD3 Slaves D0, D1...DN
SC3

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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SCPS205A – APRIL 2014 – REVISED FEBRUARY 2015 [Link]

Table of Contents
1 Features .................................................................. 1 9.2 Functional Block Diagram ....................................... 10
2 Applications ........................................................... 1 9.3 Feature Description................................................. 11
3 Description ............................................................. 1 9.4 Device Functional Modes........................................ 11
9.5 Programming........................................................... 11
4 Simplified Application Diagram............................ 1
9.6 Control Register ...................................................... 14
5 Revision History..................................................... 2
10 Application and Implementation........................ 16
6 Pin Configuration and Functions ......................... 3
10.1 Application Information.......................................... 16
7 Specifications......................................................... 4
10.2 Typical Application ................................................ 16
7.1 Absolute Maximum Ratings .................................... 4
11 Power Supply Recommendations ..................... 19
7.2 ESD Ratings.............................................................. 4
11.1 Power-On Reset Requirements ........................... 19
7.3 Recommended Operating Conditions ..................... 4
7.4 Thermal Information .................................................. 4 12 Layout................................................................... 21
12.1 Layout Guidelines ................................................. 21
7.5 Electrical Characteristics.......................................... 5
12.2 Layout Example .................................................... 21
7.6 I2C Interface Timing Requirements.......................... 6
7.7 Switching Characteristics......................................... 6 13 Device and Documentation Support ................. 22
7.8 Interrupt and Reset Timing Requirements............... 7 13.1 Trademarks ........................................................... 22
7.9 Typical Characteristics .............................................. 7 13.2 Electrostatic Discharge Caution ............................ 22
13.3 Glossary ................................................................ 22
8 Parameter Measurement Information .................. 8
9 Detailed Description ............................................ 10 14 Mechanical, Packaging, and Orderable
Information ........................................................... 22
9.1 Overview ................................................................. 10

5 Revision History
Changes from Original (April 2014) to Revision A Page

• Added D package to the datasheet. ...................................................................................................................................... 1

• Changed Handling Ratings table to ESD Ratings. ................................................................................................................ 4
• Added D package to the Thermal Information table. ............................................................................................................. 4

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6 Pin Configuration and Functions

D OR PW PACKAGE
(TOP VIEW)

A0 1 16 VCC
A1 2 15 SDA
RESET 3 14 SCL
SD0 4 13 A2
SC0 5 12 SC3
SD1 6 11 SD3
SC1 7 10 SC2
GND 8 9 SD2

Pin Functions
PIN
NO. DESCRIPTION
NAME
D, PW
A0 1 Address input 0. Connect directly to VCC or ground.
A1 2 Address input 1. Connect directly to VCC or ground.
RESET 3 Active low reset input. Connect to VCC or VDPUM (1) through a pull-up resistor, if not used.
SD0 4 Serial data 0. Connect to VDPU0 (1) through a pull-up resistor.
SC0 5 Serial clock 0. Connect to VDPU0 (1) through a pull-up resistor.
SD1 6 Serial data 1. Connect to VDPU1 (1) through a pull-up resistor.
SC1 7 Serial clock 1. Connect to VDPU1 (1) through a pull-up resistor.
GND 8 Ground
SD2 9 Serial data 2. Connect to VDPU2 (1) through a pull-up resistor.
SC2 10 Serial clock 2. Connect to VDPU2 (1) through a pull-up resistor.
SD3 11 Serial data 3. Connect to VDPU3 (1) through a pull-up resistor.
SC3 12 Serial clock 3. Connect to VDPU3 (1) through a pull-up resistor.
A2 13 Address input 2. Connect directly to VCC or ground.
SCL 14 Serial clock line. Connect to VDPUM (1) through a pull-up resistor.
SDA 15 Serial data line. Connect to VDPUM (1) through a pull-up resistor.
VCC 16 Supply power

(1) VDPUX is the pull-up reference voltage for the associated data line. VDPUM is the master I2C master reference voltage and VDPU0-VDPU3
are the slave channel reference voltages.

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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.5 7 V
(2)
VI Input voltage range –0.5 7 V
II Input current ±20 mA
IO Output current ±25 mA
Continuous current through VCC ±100 mA
Continuous current through GND ±100 mA
Ptot Total power dissipation 400 mW
TA Operating free-air temperature range –40 85 °C
Tstg Storage temperature range -65 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±1500
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.

7.3 Recommended Operating Conditions (1)

MIN MAX UNIT
VCC Supply voltage 1.65 5.5 V
SCL, SDA 0.7 × VCC 6
VIH High-level input voltage V
A2–A0, RESET 0.7 × VCC VCC + 0.5
SCL, SDA –0.5 0.3 × VCC
VIL Low-level input voltage V
A2–A0, RESET –0.5 0.3 × VCC
TA Operating free-air temperature –40 85 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

7.4 Thermal Information

TCA9546A
THERMAL METRIC (1) D PW UNIT
16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 92.3 122.3
RθJCtop Junction-to-case (top) thermal resistance 52.3 56.6
RθJB Junction-to-board thermal resistance 50.1 57.4 °C/W
ψJT Junction-to-top characterization parameter 17.7 10.9
ψJB Junction-to-board characterization parameter 49.8 66.8

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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7.5 Electrical Characteristics (1)

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP (2) MAX UNIT
Power-on reset voltage, VCC VI = VCC or
VPORR No load, 1.2 1.5 V
rising GND (3)
Power-on reset voltage, VCC VI = VCC or
VPORF No load, 0.8 1
falling (4) GND (3)
5V 3.6
4.5 V to 5.5 V 2.6 4.5
3.3 V 1.9
3 V to 3.6 V 1.6 2.8
Vpass Switch output voltage VSWin = VCC, ISWout = –100 μA V
2.5 V 1.4
2.3 V to 2.7 V 1.0 1.8
1.8 V 0.8
1.65 V to 1.95 V 0.5 1.1
VOL = 0.4 V 3 7
IOL SDA 1.65 V to 5.5 V mA
VOL = 0.6 V 6 10
SCL, SDA ±1
SC3–SC0, SD3–SD0 ±1
II VI = VCC or GND (3) 1.65 V to 5.5 V μA
A2–A0 ±1
RESET ±1
5.5 V 50
VI = VCC or GND (3) 3.6 V 20
fSCL = 400 kHz IO = 0
tr,max = 300 ns 2.7 V 11
1.65 V 6
Operating mode
5.5 V 35
VI = VCC or GND (3) 3.6 V 14
fSCL = 100 kHz IO = 0
tr,max = 1 µs 2.7 V 5
1.65 V 2
ICC μA
5.5 V 1.6 2
VI = GND (3) 3.6 V 1.0 1.3
Low inputs
IO = 0 2.7 V 0.7 1.1
1.65 V 0.4 0.55
Standby mode
5.5 V 1.6 2
VI = VCC 3.6 V 1.0 1.3
High inputs
IO = 0 2.7 V 0.7 1.1
1.65 V 0.4 0.55
SCL or SDA input at 0.6 V,
1.65 V to 5.5 V 2 15
Supply-current Other inputs at VCC or GND (3)
ΔICC SCL, SDA μA
change SCL or SDA input at VCC – 0.6 V,
1.65 V to 5.5 V 2 15
Other inputs at VCC or GND (3)
A2–A0 4.5 6
Ci VI = VCC or GND (3) 1.65 V to 5.5 V pF
RESET 4.5 5.5
Cio(OFF) SCL, SDA 15 19
(5) VI = VCC or GND (3) Switch OFF 1.65 V to 5.5 V pF
SC3–SC0, SD3–SD0 6 8

(1) For operation between specified voltage ranges, refer to the worst-case parameter in both applicable ranges.
(2) All typical values are at nominal supply voltage (1.8-V, 2.5-V, 3.3-V, or 5-V VCC), TA = 25°C.
(3) RESET = VCC (held high) when all other input voltages, VI = GND.
(4) The power-on reset circuit resets the I2C bus logic with VCC < VPORF.
(5) Cio(ON) depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON.
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Electrical Characteristics(1) (continued)

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP (2) MAX UNIT
4.5 V to 5.5 V 4 10 16
VO = 0.4 V IO = 15 mA
3 V to 3.6 V 5 13 20
RON Switch on-state resistance Ω
2.3 V to 2.7 V 7 16 45
VO = 0.4 V IO = 10 mA
1.65 V to 1.95 V 10 25 70

7.6 I2C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5)
STANDARD MODE FAST MODE
I2C BUS I2C BUS UNIT
MIN MAX MIN MAX
fscl I2C clock frequency 0 100 0 400 kHz
tsch I2C clock high time 4 0.6 μs
2
tscl I C clock low time 4.7 1.3 μs
tsp I2C spike time 50 50 ns
tsds I2C serial-data setup time 250 100 ns
tsdh I2C serial-data hold time 0 (1) 0 (1) μs
ticr I2C input rise time 1000 20 + 0.1Cb (2)
300 ns
2 (2)
ticf I C input fall time 300 20 + 0.1Cb 300 ns
tocf I2C output fall time 10-pF to 400-pF bus 300 20 + 0.1Cb (2)
300 ns
2
tbuf I C bus free time between stop and start 4.7 1.3 μs
tsts I2C start or repeated start condition setup 4.7 0.6 μs
tsth I2C start or repeated start condition hold 4 0.6 μs
2
tsps I C stop condition setup 4 0.6 μs
tvdL(Data) Valid-data time (high to low) (3) SCL low to SDA output low valid 1 1 μs
tvdH(Data) Valid-data time (low to high) (3) SCL low to SDA output high valid 0.6 0.6 μs
ACK signal from SCL low
tvd(ack) Valid-data time of ACK condition 1 1 μs
to SDA output low
2
Cb I C bus capacitive load 400 400 pF

(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), in order to
bridge the undefined region of the falling edge of SCL.
(2) Cb = total bus capacitance of one bus line in pF
(3) Data taken using a 1-kΩ pullup resistor and 50-pF load (see Figure 5)

7.7 Switching Characteristics

over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 5)
FROM TO
PARAMETER MIN MAX UNIT
(INPUT) (OUTPUT)

(1)
RON = 20 Ω, CL = 15 pF 0.3
tpd Propagation delay time SDA or SCL SDn or SCn ns
RON = 20 Ω, CL = 50 pF 1

(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).

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7.8 Interrupt and Reset Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER MIN MAX UNIT
tWL Pulse duration, RESET low 6 ns
(1)
trst RESET time (SDA clear) 500 ns
tREC(STA) Recovery time from RESET to start 0 ns

(1) trst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high,
signaling a stop condition. It must be a minimum of tWL.

7.9 Typical Characteristics

800 1.8
VCC = 5.5V
700 VCC = 3.3V 1.6
VCC = 1.65V

ICC, Standby Mode (µA)

600 1.4

500 1.2
VOL (mV)

400 1

300 0.8

200 0.6
25ºC (Room Temperature)
100 0.4 85ºC
-40ºC
0 0.2
0 2 4 6 8 10 12 1.5 2 2.5 3 3.5 4 4.5 5 5.5
IOL (mA) D003
VCC (V) D004

Figure 1. SDA Output Low Voltage (VOL) vs Load Current Figure 2. Standby Current (ICC) vs Supply Voltage (VCC) at
(IOL) at Three VCC Levels Three Temperature Points
6 30
25ºC (Room Temperature)
5.8 85ºC
-40º 25
5.6
5.4
20
CIO(OFF) (pF)

RON (Ohm)

5.2
5 15
4.8
10
4.6
4.4 25ºC (Room Temperature)
5
4.2 85ºC
-40ºC
4 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V) D006
VCC (V) D001

Figure 3. Slave channel (SCn/SDn) capacitance (Cio(OFF)) vs. Figure 4. ON-Resistance (RON) vs Supply Voltage (VCC) at
Supply Voltage (VCC) at Three Temperature Points Three Temperatures

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8 Parameter Measurement Information

VCC

RL = 1 kΩ

SDn, SCn
DUT

CL = 50 pF
(See Note A)

I2C PORT LOAD CONFIGURATION

Two Bytes for Complete

Device Programming

Stop Start Address R/W Data Data Stop

Address Address ACK ACK
Condition Condition Bit 7 Bit 0 Bit 7 Bit 0 Condition
Bit 6 Bit 1 (A) (A)
(P) (S) (MSB) (LSB) (MSB) (LSB) (P)

BYTE DESCRIPTION
1 I2C address + R/W

2 Control register data

tscl tsch

0.7 × VCC
SCL
0.3 × VCC
tvd(ACK)
ticr tsts
or tvdL
tbuf ticf
tsp tvdH
0.7 × VCC
SDA
0.3 × VCC
ticf ticr tsdh tsps
tsth tsds Repeat
Start Stop
Start or Repeat
Condition Condition
Start Condition

VOLTAGE WAVEFORMS
A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
tr/tf ≤ 30 ns.
C. The outputs are measured one at a time, with one transition per measurement.

Figure 5. I2C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms

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Parameter Measurement Information (continued)

Start ACK or Read Cycle
SCL

SDA
30%

trst

RESET 50%
tREC
tWL

Figure 6. Reset Timing

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9 Detailed Description

9.1 Overview
The TCA9546A is a 4-channel, bidirectional translating I2C switch. The master SCL/SDA signal pair is directed to
four channels of slave devices, SC0/SD0-SC3/SD3. Any individual downstream channel can be selected as well
as any combination of the four channels.
The device offers an active-low RESET input which resets the state machine and allows the TCA9546A to
recover should one of the downstream I2C buses get stuck in a low state. The state machine of the device can
also be reset by cycling the power supply, VCC, also known as a power-on reset (POR). Both the RESET function
and a POR will cause all channels to be deselected.
The connections of the I2C data path are controlled by the same I2C master device that is switched to
communicate with multiple I2C slaves. After the successful acknowledgment of the slave address (hardware
selectable by A0 and A1 pins), a single 8-bit control register is written to or read from to determine the selected
channels.
The TCA9546A may also be used for voltage translation, allowing the use of different bus voltages on each
SCn/SDn pair such that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts. This is achieved by using
external pull-up resistors to pull the bus up to the desired voltage for the master and each slave channel.

9.2 Functional Block Diagram

TCA9546A
5
SC0

SC1 7

SC2 10

SC3 12

SD0 4

SD1 6

SD2 9

SD3 11

Switch Control Logic

GND 8

VCC 16
3 Power-On Reset
RESET

14 1
SCL A0
Input Filter 2 A1
15 I2C Bus Control
SDA 13 A2

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9.3 Feature Description

The TCA9546A is a 4-channel, bidirectional translating switch for I2C buses that supports Standard-Mode (100
kHz) and Fast-Mode (400 kHz) operation. The TCA9546A features I2C control using a single 8-bit control register
in which the four least significant bits control the enabling and disabling of the 4 switch channels of I2C data flow.
Depending on the application, voltage translation of the I2C bus can also be achieved using the TCA9546A to
allow 1.8-V, 2.5-V, or 3.3-V parts to communicate with 5-V parts. Additionally, in the event that communication on
the I2C bus enters a fault state, the TCA9546A can be reset to resume normal operation using the RESET pin
feature or by a power-on reset which results from cycling power to the device.

9.4 Device Functional Modes

9.4.1 RESET Input
The RESET input is an active-low signal that may be used to recover from a bus-fault condition. When this signal
is asserted low for a minimum of tWL, the TCA9546A resets its registers and I2C state machine and deselects all
channels. The RESET input must be connected to VCC through a pull-up resistor.

9.4.2 Power-On Reset

When power is applied to VCC, an internal power-on reset holds the TCA9546A in a reset condition until VCC has
reached VPOR. At this point, the reset condition is released, and the TCA9546A registers and I2C state machine
are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, VCC must
be lowered below V POR to reset the device.

9.5 Programming
9.5.1 I2C Interface
The I2C bus is for two-way two-line communication between different ICs or modules. The two lines are a serial
data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup
resistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is not
busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high
period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see Figure 7).

SDA

SCL

Data Line Change

Stable; of Data
Data Valid Allowed

Figure 7. Bit Transfer

Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the
clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is
defined as the stop condition (P) (see Figure 8).

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Programming (continued)

SDA

SCL
S P

Start Condition Stop Condition

Figure 8. Definition of Start and Stop Conditions

A device generating a message is a transmitter; a device receiving is the receiver. The device that controls the
message is the master, and the devices that are controlled by the master are the slaves (see Figure 9).
SDA

SCL

Master Slave Master I2C

Transmitter/ Slave Transmitter/ Master Transmitter/ Multiplexer
Receiver Receiver Receiver Transmitter Receiver

Slave

Figure 9. System Configuration

The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one acknowledge (ACK) bit. The transmitter must release the SDA
line before the receiver can send an ACK bit.
When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a master
must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The
device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable
low during the high pulse of the ACK-related clock period (see Figure 10). Setup and hold times must be taken
into account.

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Programming (continued)

Data Output
by Transmitter

NACK

Data Output
by Receiver

ACK

SCL From
Master 1 2 8 9

Start Clock Pulse for ACK

Condition

Figure 10. Acknowledgment on the I2C Bus

Data is transmitted to the TCA9546A control register using the write mode shown in Figure 11.
Slave Address Control Register

S 1 1 1 0 A2 A1 A0 0 A X X X X B3 B2 B1 B0 A P
SDA

Start Condition R/W ACK From Slave ACK From Slave Stop Condition

Figure 11. Write Control Register

Data is read from the TCA9546A control register using the read mode shown in Figure 12.
Slave Address Control Register

SDA S 1 1 1 0 A2 A1 A0 1 A 0 0 0 0 B3 B2 B1 B0 NA P

Start Condition R/W ACK From Slave NACK From Master Stop Condition

Figure 12. Read Control Register

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9.6 Control Register

9.6.1 Device Address
Following a start condition, the bus master must output the address of the slave it is accessing. The address of
the TCA9546A is shown in Figure 13. To conserve power, no internal pullup resistors are incorporated on the
hardware-selectable address pins, and they must be pulled high or low.
Slave Address

1 1 1 0 A2 A1 A0 R/W

Fixed Hardware
Selectable

Figure 13. TCA9546A Address

The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,
while a logic 0 selects a write operation.

9.6.2 Control Register Description

Following the successful acknowledgment of the slave address, the bus master sends a byte to the TCA9546A,
which is stored in the control register (see Figure 14). If multiple bytes are received by the TCA9546A, it will save
the last byte received. This register can be written and read via the I2C bus.
Channel Selection Bits
(Read/Write)

7 6 5 4 3 2 1 0

X X X X B3 B2 B1 B0

Channel 0
Channel 1
Channel 2
Channel 3

Figure 14. Control Register

9.6.3 Control Register Definition

One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register (see
Table 1). This register is written after the TCA9546A has been addressed. The four LSBs of the control byte are
used to determine which channel or channels are to be selected. When a channel is selected, the channel
becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn lines are in
a high state when the channel is made active, so that no false conditions are generated at the time of
connection. A stop condition always must occur right after the acknowledge cycle.

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Control Register (continued)

Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status) (1)
B7 B6 B5 B4 B3 B2 B1 B0 COMMAND
0 Channel 0 disabled
X X X X X X X
1 Channel 0 enabled
0 Channel 1 disabled
X X X X X X X
1 Channel 1 enabled
0 Channel 2 disabled
X X X X X X X
1 Channel 2 enabled
0 Channel 3 disabled
X X X X X X X
1 Channel 3 enabled
No channel selected,
0 0 0 0 0 0 0 0
power-up/reset default state

(1) Several channels can be enabled at the same time. For example, B3 =0, B2 = 1, B1 = 1, B0 = 0 means that channels 0 and 3 are
disabled, and channels 1 and 2 are enabled. Care should be taken not to exceed the maximum bus capacity.

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10 Application and Implementation

10.1 Application Information
Applications of the TCA9546A will contain an I2C (or SMBus) master device and up to four I2C slave devices.
The downstream channels are ideally used to resolve I2C slave address conflicts. For example, if four identical
digital temperature sensors are needed in the application, one sensor can be connected at each channel: 0, 1, 2,
and 3. When the temperature at a specific location needs to be read, the appropriate channel can be enabled
and all other channels switched off, the data can be retrieved, and the I2C master can move on and read the next
channel.
In an application where the I2C bus will contain many additional slave devices that do not result in I2C slave
address conflicts, these slave devices can be connected to any desired channel to distribute the total bus
capacitance across multiple channels. If multiple switches will be enabled simultaneously, additional design
requirements must be considered (See Design Requirements and Detailed Design Procedure).

10.2 Typical Application

A typical application of the TCA9546A will contain anywhere from 1 to 5 separate data pull-up voltages, VDPUX ,
one for the master device (VDPUM) and one for each of the selectable slave channels (VDPU0 – VDPU3). In the
event where the master device and all slave devices operate at the same voltage, then the pass voltage, Vpass =
VDPUX. Once the maximum Vpass is known, Vcc can be selected easily using Figure 16. In an application where
voltage translation is necessary, additional design requirements must be considered (See Design Requirements).
Figure 15 shows an application in which the TCA9546A can be used.
VDPUM = 1.65 V to 5.5 V
VCC = 3.3 V
VDPU0 = 1.65 V to 5.5 V
16
VCC
15 4
SDA SDA SD0
I2C/SMBus 14 5 Channel 0
SCL SCL SC0
Master
3 VDPU1 = 1.65 V to 5.5 V
RESET

SD1 6
7 Channel 1
SC1

VDPU2 = 1.65 V to 5.5 V

TCA9546A

9
SD2
10 Channel 2
SC2

VDPU3 = 1.65 V to 5.5 V

13
A2
2
A1 11
1 SD3
A0 Channel 3
8 12
GND SC3

Figure 15. TCA9546A Typical Application Schematic

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Typical Application (continued)

10.2.1 Design Requirements
The A0, A1, and A2 pins are hardware selectable to control the slave address of the TCA9546A. These pins may
be tied directly to GND or VCC in the application.
If multiple slave channels will be activated simultaneously in the application, then the total IOL from SCL/SDA to
GND on the master side will be the sum of the currents through all pull-up resistors, Rp.
The pass-gate transistors of the TCA9546A are constructed such that the VCC voltage can be used to limit the
maximum voltage that is passed from one I2C bus to another.
Figure 16 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using
data specified in the Electrical Characteristics section of this data sheet). In order for the TCA9546A to act as a
voltage translator, the Vpass voltage must be equal to or lower than the lowest bus voltage. For example, if the
main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or below 2.7 V
to effectively clamp the downstream bus voltages. As shown in Figure 16, Vpass(max) is 2.7 V when the TCA9546A
supply voltage is 4 V or lower, so the TCA9546A supply voltage could be set to 3.3 V. Pull-up resistors then can
be used to bring the bus voltages to their appropriate levels (see Figure 15).

10.2.2 Detailed Design Procedure

Once all the slaves are assigned to the appropriate slave channels and bus voltages are identified, the pull-up
resistors, Rp, for each of the buses need to be selected appropriately. The minimum pull-up resistance is a
function of VDPUX, VOL,(max), and IOL:
VDPUX - VOL(max)
Rp(min) =
IOL (1)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL =
400 kHz) and bus capacitance, Cb:
tr
Rp(max) =
0.8473 ´ Cb (2)
2
The maximum bus capacitance for an I C bus must not exceed 400 pF for fast-mode operation. The bus
capacitance can be approximated by adding the capacitance of the TCA9546A, Cio(OFF), the capacitance of
wires/connections/traces, and the capacitance of each individual slave on a given channel. If multiple channels
will be activated simultaneously, each of the slaves on all channels will contribute to total bus capacitance.

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Typical Application (continued)

10.2.3 TCA9546A Application Curves

5 25
25ºC (Room Temperature) Standard-mode
85ºC Fast-mode
4 -40ºC 20

Rp(max) (kOhm)
3 15
Vpass (V)

2 10

1 5

0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0 50 100 150 200 250 300 350 400 450
VCC (V) D007
Cb (pF) D008
Standard-mode SPACE Standard-mode Fast-mode
(fSCL kHz, tr (fSCL kHz, tr) (fSCL= 100 kHz, tr = 1 µs) (fSCL= 400 kHz, tr= 300 ns)

Figure 16. Pass-Gate Voltage (Vpass) vs Supply Voltage Figure 17. Maximum Pull-Up resistance (Rp(max)) vs Bus
(VCC) at Three Temperature Points Capacitance (Cb)

1.8

1.6

1.4

1.2
Rp(min) (kOhm)

0.8

0.6

0.4

0.2 VDPUX > 2V

VDPUX <= 2
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VDPUX (V) D009
VOL = 0.2*VDPUX, IOL = 2 mA when VDPUX ≤ 2 V
VOL = 0.4 V, IOL = 3 mA when VDPUX > 2 V

Figure 18. Minimum Pull-Up Resistance (Rp(min)) vs Pull-Up Reference Voltage (VDPUX)

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11 Power Supply Recommendations

The operating power-supply voltage range of the TCA9546A is 1.65 V to 5.5 V applied at the VCC pin. When the
TCA9546A is powered on for the first time or anytime the device needs to be reset by cycling the power supply,
the power-on reset requirements must be followed to ensure the I2C bus logic is initialized properly.

11.1 Power-On Reset Requirements

In the event of a glitch or data corruption, TCA9546A can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
A power-on reset is shown in Figure 19.
VCC

Ramp-Down Ramp-Up

VCC_TRR

VCC drops below VPORF – 50 mV

Time
Time to Re-Ramp
VCC_FT VCC_RT

Figure 19. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC

Table 2 specifies the performance of the power-on reset feature for TCA9546A for both types of power-on reset.

Table 2. Recommended Supply Sequencing And Ramp Rates (1)

PARAMETER MIN TYP MAX UNIT
VCC_FT Fall time See Figure 19 1 100 ms
VCC_RT Rise time See Figure 19 0.1 100 ms
Time to re-ramp (when VCC drops below VPORF(min) – 50 mV or
VCC_TRR See Figure 19 40 μs
when VCC drops to GND)
Level that VCC can glitch down to, but not cause a functional
VCC_GH See Figure 20 1.2 V
disruption when VCC_GW = 1 μs
Glitch width that will not cause a functional disruption when
VCC_GW See Figure 20 10 μs
VCC_GH = 0.5 × VCC
VPORF Voltage trip point of POR on falling VCC See Figure 21 0.8 1.25 V
VPORR Voltage trip point of POR on rising VCC See Figure 21 1.05 1.5 V

(1) All supply sequencing and ramp rate values are measured at TA = 25°C

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Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 20 and Table 2 provide more
information on how to measure these specifications.
VCC

VCC_GH

Time

VCC_GW

Figure 20. Glitch Width and Glitch Height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the
registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based
on the VCC being lowered to or from 0. Figure 21 and Table 2 provide more details on this specification.
VCC

VPORR

VPORF

Time

POR

Time

Figure 21. VPOR

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12 Layout

12.1 Layout Guidelines

For PCB layout of the TCA9546A, common PCB layout practices should be followed but additional concerns
related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C
signal speeds. It is common to have a dedicated ground plane on an inner layer of the board and pins that are
connected to ground should have a low-impedance path to the ground plane in the form of wide polygon pours
and multiple vias. By-pass and de-coupling capacitors are commonly used to control the voltage on the VCC pin,
using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller
capacitor to filter out high-frequency ripple.
In an application where voltage translation is not required, all VDPUX voltages and VCC could be at the same
potential and a single copper plane could connect all of pull-up resistors to the appropriate reference voltage. In
an application where voltage translation is required, VDPUM, VDPU0, VDPU1, VDPU2, and VDPU3 may all be on the
same layer of the board with split planes to isolate different voltage potentials.
To reduce the total I2C bus capacitance added by PCB parasitics, data lines (SCn and SDn) should be a short as
possible and the widths of the traces should also be minimized (e.g. 5-10 mils depending on copper weight).

12.2 Layout Example

LEGEND
Partial Power Plane Polygonal To I2C Master
Copper Pour
VIA to Power Plane
VIA to GND Plane (Inner Layer)
VDPUM

By-pass/De-coupling
capacitors

VDPU0 GND VCC

To Slave Channel 0

A0 VCC
VDPU3
A1 SDA

To Slave Channel 3
RESET SCL
TCA9546A

SD0 A2

SC0 SC3

SD1 SD3
To Slave Channel 1

SC1 SC2

GND SD2 VDPU2

To Slave Channel 2

GND
VDPU1

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13 Device and Documentation Support

13.1 Trademarks
All trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation

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 PACKAGE OPTION ADDENDUM

[Link] 23-Apr-2015

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TCA9546ADR ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 TCA9546A
& no Sb/Br)
TCA9546APWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 PW546A
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check [Link] for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 23-Apr-2015

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 23-Apr-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TCA9546ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TCA9546APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 23-Apr-2015

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TCA9546ADR SOIC D 16 2500 367.0 367.0 38.0
TCA9546APWR TSSOP PW 16 2000 367.0 367.0 35.0

Pack Materials-Page 2
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