Advanced Computer Architecture Study Guide
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Braincain007Advanced Computer Architecture Study Guide
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Powered by AIThe MESI protocol manages cache coherency by ensuring that caches in multiprocessor systems have consistent views of the memory. It uses four states: Modified, Exclusive, Shared, and Invalid . A cache line can be in only one state at a time; for instance, 'Modified' indicates that a line has been altered and must be written back to main memory before another cache can share it. This protocol plays a vital role in parallel computing by maintaining consistency and integrity of data cached across multiple processors, thereby minimizing data conflicts and performance overhead due to cache synchronization issues .
Flynn's Taxonomy provides a framework for classifying computer architectures based on instruction and data streams, using categories such as SISD, SIMD, MISD, and MIMD . This classification is useful for understanding the parallelism and capabilities of different architectures. SIMD is often efficient for tasks that require the same operation on multiple data points, such as in image processing or SIMD operations in GPUs. MIMD, which allows different programs to run independently, is optimal for distributed systems and scenarios where tasks are not necessarily uniform. The choice of model is determined by the specific application needs, where workload diversity favors MIMD, and homogeneous tasks favor SIMD .
Pipelining increases instruction throughput by overlapping different stages of instruction processing, allowing multiple instructions to be processed at different stages simultaneously, resolving latency issues intrinsic in sequential processing . Multithreading creates multiple threads of a process that can run on different processors, exploiting latent parallelism in applications. Both techniques aim to maximize processor utilization and address scalability by increasing the efficiency with which processor resources are used, albeit pipelining focuses on linear instruction advancement, while multithreading improves task management and throughput .
Edge AI and heterogeneous computing face challenges such as limited computational resources, power constraints, and the need for efficient data processing locally on edge devices . Addressing these requires integrating specialized architectures like TPUs and NPUs that are optimized for low power consumption and high efficiency in AI computations. Moreover, advancements in AI model optimization techniques, such as quantization and pruning, help reduce model complexity and size. Modern architectures also employ hybrid systems with collaborative distributions between edge and cloud computing to optimize processing loads and resource utilization .
The Von Neumann architecture utilizes a single memory space for both data and instructions, which can lead to a bottleneck known as the 'Von Neumann bottleneck' due to the sequential processing of instructions and operations sharing the same data bus . In contrast, the Harvard architecture separates memory into two distinct regions for instructions and data, allowing simultaneous access to both, which can improve throughput and processing speed by eliminating the data instruction bottleneck . These distinctions affect system performance by influencing the speed and efficiency with which instructions can be executed.
Register renaming resolves data hazards by using additional physical registers to remove false data dependencies, such as Write After Write (WAW) and Write After Read (WAR) hazards, that might otherwise prevent instruction parallelism . By ensuring that different operations use separate instances or 'aliases' of registers, it allows processors to maintain high instruction throughput and prevent unnecessary stalls. This technique ensures that instructions proceed efficiently without being delayed by false dependencies imposed by the programming model, thus promoting optimization and exploiting ILP effectively .
Instruction-level parallelism (ILP) aims to improve processor performance by executing multiple instructions simultaneously. However, ILP is limited by data dependencies: Read After Write (RAW) involves waiting for data from a previous instruction before execution, Write After Write (WAW) concerns ensuring the correct sequence of write operations, and Write After Read (WAR) requires that a read operation is completed before a new write. These dependencies can stall pipelines, hence sophisticated techniques like Out-of-Order Execution and Speculative Execution are employed to anticipate and mitigate these stalls, thus maintaining high pipeline throughput and performance .
Functional parallelism focuses on decomposing tasks into multiple functions that can be processed concurrently, making it suitable for operations that can be broken down into distinct activities, like multitasking in operating systems . Data parallelism, on the other hand, involves distributing subsets of the same data across multiple processors to be processed in parallel, ideal for tasks like matrix operations in scientific computing . Modern systems often utilize functional parallelism in multi-core CPUs to enhance multitasking ability, while data parallelism is employed within GPUs to accelerate processing of large data sets through vectorization .
In VLIW architectures, the compiler has the crucial role of instruction scheduling and determining parallel execution at compile time, since the hardware does not have the capability to perform dynamic scheduling . This imposes a significant burden on compiler capabilities to extract parallelism, requiring advanced optimization techniques. In contrast, superscalar architectures rely more on hardware to dynamically schedule and issue multiple instructions per cycle, reducing the complexity required in the compiler and allowing it to concentrate more on other optimizations like instruction grouping . Thus, while both architectures seek to exploit ILP, VLIW places more optimization responsibility on the compiler, whereas superscalar processors distribute this across both software and hardware .
Quantum computing diverges from traditional models by employing quantum bits (qubits) that can exist in multiple states simultaneously, enabling massive parallelism and solving complex problems exponentially faster than classical computers. It offers applications in cryptography, optimization, and drug discovery . Neuromorphic computing mimics the neural structures of the human brain using spiking neural networks, aiming to process information more like a biological system. It excels in pattern recognition, sensory processing, and machine learning tasks. Both models represent significant shifts from traditional computing, utilizing fundamentally different principles to expand computational capacities and efficiencies .