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Verilog Modules and Testbenches

The document contains RTL code and testbenches for various digital circuits including a counter, a tohop gate, a 4-bit full adder, and an 8x1 multiplexer. Each module is defined with its inputs and outputs, and corresponding test modules apply different input combinations to verify functionality. Additionally, waveform dumps are included for simulation analysis.

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toann5106
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4 views9 pages

Verilog Modules and Testbenches

The document contains RTL code and testbenches for various digital circuits including a counter, a tohop gate, a 4-bit full adder, and an 8x1 multiplexer. Each module is defined with its inputs and outputs, and corresponding test modules apply different input combinations to verify functionality. Additionally, waveform dumps are included for simulation analysis.

Uploaded by

toann5106
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Lap1

Bài 1
RTL
module counter (
input wire clk,
input wire reset,
output reg [7:0] count
);
always @(posedge clk or posedge reset) begin
if (reset)
count <= 8'b00000000;
else
count <= count + 1;
end

endmodule

TEST

module test;
reg clk;
reg reset;
wire [7:0] count;
// Instantiate the counter
counter uut (
.clk(clk),
.reset(reset),
.count(count)
);
// Generate a clock signal: toggle every 5 time units
always #10 clk = ~clk;
initial begin
// Initialize signals
clk = 0;
reset = 1;
#20 reset = 0; // Release reset after 10 time units
#100 $finish; // Stop simulation after 100 time units
end
// Dump the variables to the waveform file for viewing
initial begin
$dumpfile("[Link]");
$dumpvars(0, test);
end
endmodule

RTL

module tohop_gate (
input wire a,
input wire b,
input wire c,
output wire x
);
assign x = (~a& b)+( b & c);
endmodule

TEST

module test;
reg a;
reg b;
reg c;
wire x;
// Instantiate the tohop_gate
tohop_gate uut (
.a(a),
.b(b),
.c(c),
.x(x)
);
initial begin
// Apply different input combinations
a = 0; b = 0; c = 1; #5;
a = 0; b = 0; c = 1; #5;
a = 0; b = 1; c = 1; #5;
a = 0; b = 1; c = 1; #5;
a = 1; b = 0; c = 0; #5;
a = 1; b = 0; c = 0; #5;
a = 1; b = 1; c = 0; #5;
a = 1; b = 1; c = 0; #5;
end
// Waveform dump
initial begin
$dumpfile("[Link]");
$dumpvars(0, test);
end
endmodule

lap 2
RTL
module full_adder_4bit (
input wire [3:0] a,
input wire [3:0] b,
input wire cin,
output wire [3:0] sum,
output wire cout
);
assign {cout, sum} = a + b + cin;
endmodule

TEST

module test;
reg [3:0] a, b;
reg cin;
wire [3:0] sum;
wire cout;

// Instantiate the 4-bit full adder


full_adder_4bit uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);

initial begin
// Test all combinations of inputs
a = 4'b1111; b = 4'b1011; cin = 1'b0; #10;
a = 4'b1001; b = 4'b1010; cin = 1'b1; #10;
a = 4'b0101; b = 4'b1010; cin = 1'b0; #10;
a = 4'b0011; b = 4'b0101; cin = 1'b1; #10;
$finish;
end

// Waveform dump
initial begin
$dumpfile("[Link]");
$dumpvars(0, test);
end
endmodule
Lap 3
Lap 4
RTL
module mux8x1 (
input wire [3:0] sel,
input wire [7:0] in,
output wire out
);
assign out = (sel == 3'b000) ? in[0] :
(sel == 4'b0010) ? in[1] :
(sel == 4'b0100) ? in[2] :
(sel == 4'b0101) ? in[3] :
(sel == 4'b1010) ? in[4] :
(sel == 4'b1001) ? in[5] :
(sel == 4'b1100) ? in[6] :
in[7];
endmodule
TEST
module test;
reg [3:0] sel;
reg [7:0] in;
wire out;
// Instantiate the 8x1 Mux
mux8x1 uut (
.sel(sel),
.in(in),.out(out)
);
initial begin
// Test different input combinations
sel = 4'b0000; in = 8'b10110010;
#10 sel = 4'b0010;
#10 sel = 4'b0100;
#10 sel = 4'b0101;
#10 sel = 4'b1010;
#10 sel = 4'b1001;
#10 sel = 4'b1100;
#10 sel = 4'b1101;
#10 $finish;
end
// Waveform dump
initial begin
$dumpfile("[Link]");
$dumpvars(0, test);
end
endmodule

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