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 Designing with 8-Bit Microcontroller – 8051

Factors to be considered in Microcontroller Selection

✔ Feature Set
✔ Speed of Operation
✔ Code Memory space
✔ Data Memory Space
✔ Development Support
✔ Availability
✔ Power Consumption
✔ Cost

2
 Designing with 8-Bit Microcontroller – 8051

Why 8051?
✔ Very versatile microcontroller featuring powerful Boolean processor
✔ Supports bit manipulation instructions for real time industrial control applications
✔ The standard 8051 architecture supports 6 interrupts (2 external interrupts, 2 timer
interrupts and 2 serial interrupts), two 16 bit timers/counters, 32 I/O lines and a
programmable full duplex serial interface
✔ The interrupts have two priority levels and each interrupt is allocated fixed 8 bytes of
code memory. This approach is very efficient in real time application.
✔ Though 8051 is invented by Intel, today it is available in the market from more than 20
vendors and with more than 100 variants of the original 8051 flavor, supporting CAN,
USB, SPI and TCP/IP interfaces, integrated ADC/DAC, LCD Controller and extended
number of I/O Ports.
✔ Another remarkable feature of 8051 is low cost
✔ The 8051 flash microcontroller (AT89C51) from Atmel is available in the market for less
than 1USD per piece. So imagine its cost for high volume purchase.

3
Designing with 8-Bit Microcontroller – 8051
The Standard 8051 Architecture

4
Designing with 8-Bit Microcontroller – 8051
The Standard 8051 – Pin Configuration for 40 Pin DIP model

5
 Designing with 8-Bit Microcontroller – 8051
The Standard 8051 Architecture Highlights
✔ Built around an 8bit CPU with Boolean processing capability
✔ Built-in oscillator driver unit
✔ 4K bytes of On-chip Program memory
✔ 128 bytes of internal Data memory
✔ 128 bytes of Special Function Register memory area
✔ 32 general purpose I/O lines organized into four 8bit bi-directional ports
✔ Two 16bit timer units
✔ A full duplex programmable UART for serial data transmission with configurable
baudrates
✔ Built around the ‘Harvard’ processor architecture
✔ The program and data memory of 8051 is logically separated and they physically reside
separately
✔ Separate address spaces are assigned for data memory and program memory
✔ 16bit wide address bus which can address code memory up to 64KB (216)
6
 Designing with 8-Bit Microcontroller – 8051
8051 Memory Organization – Code Memory

Pin EA\ = 1: Configures the chip to execute instructions from program memory up to 4K (program
memory location up to 0FFFH) from internal memory and 4K (program memory location
from 1000H) onwards from external memory
Pin EA\ = 0: Configures the chip to external program execution mode, where the entire code memory
(0000H to FFFFH) is executed from the external memory
7
 Designing with 8-Bit Microcontroller – 8051
8051 Memory Organization – External Program Memory Access

✔ Port 0 (P0) serves as the multiplexed lower 8bit address/data bus

✔ Port 0 emits the lower order address first and then acts as the input port for data transfer from the corresponding code
memory location
✔ The Address Latch Enable (ALE) signal is asserted when a valid address is available at the multiplexed address/data bus.
ALE signal is used for latching the lower order address
✔ Port 2 (P2) emits the higher order address
✔ The address from which the program instruction to be fetched is supplied by the 16bit register, Program Counter (PC), which
is part of the CPU
✔ The control signal for external program memory execution is PSEN\ (Program Strobe Enable). For internal program memory
fetches PSEN\ is not activated 8
 Designing with 8-Bit Microcontroller – 8051
8051 Memory Organization –Data Memory
✔ The basic 8051 architecture supports 128 bytes of internal data memory and 128
bytes of ‘Special Function Register’ Memory
✔ Special Function Register memory is not available for user for general data
memory applications
✔ The address range for internal user data memory is 00H to 7FH.
✔ Special Function Registers are residing at memory area 80H to FFH
✔ Supports interfacing of up to 64 Kbytes of external data memory
✔ RD\ and WR\ are the control signals for external data memory access
✔ Data Pointer’ (DPTR) register is the16bit register holding the address of external
data memory address to be accessed
✔ Data Pointer is made up of two 8bit registers, namely, DPL (holding the lower order
8bit) and DPH (holding the higher order 8bit)
✔ Port 0 emits the content of DPL and Port 2 emits the content of DPH in external
data memory operation
✔ Port 0 acts as the multiplexed address/data bus in external data memory operation
9
 Designing with 8-Bit Microcontroller – 8051
8051 Memory Organization – Internal Data Memory

✔ Internal data memory addresses are always one byte long and it can accommodate up to 256 bytes of internal data
memory (Ranging from 0 to 255)
✔ The addressing techniques used in 8051 can accommodate 384 bytes using a simple memory addressing technique.
The technique is: Direct addressing of data memory greater than 7FH will access one memory space, namely
Special Function Register memory and indirect addressing of memory address greater than 7FH will access another
memory space, the upper 128 bytes of data memory
✔ These techniques will work only if the upper data memory is physically implemented in the chip
✔ The basic version of 8051 does not implement the upper data memory physically
✔ The 8052 family implements the upper data memory physically in the chip and so the upper 128 memory is also
available for the user as general purpose memory, if accessed through indirect addressing 10
 Designing with 8-Bit Microcontroller – 8051
8051 Memory Organization – External Data Memory Access

✔ Port 0 (P0) serves as the multiplexed lower 8bit address/data bus

✔ Port 0 emits the lower order address first and then acts as the input port for data transfer from the corresponding data
memory location
✔ The Address Latch Enable (ALE) signal is asserted when a valid address is available at the multiplexed address/data bus.
ALE signal is used for latching the lower order address
✔ Port 2 (P2) emits the higher order address
✔ The address from which the external data memory is to be read/write is supplied by the 16bit register, Data Pointer (DPTR),
which is part of the CPU
✔ The control signal for external program memory execution is RD\ and WR\
11
 Designing with 8-Bit Microcontroller – 8051

8051 Memory Organization – Paged Data Memory Addressing

✔ In Paged mode addressing, the memory is arranged like the lines of a note book.
It contains pages and a fixed no. of lines/page
✔ A specific line in the page can be accessed by knowing its page number and the
line number
✔ Memory can also be arranged like a note book where the page number is defined
by the address bits of the higher order address and a byte within that page by the
lower order address bits
✔ For eg. The entire 64KB address range of 8051 can be viewed as 256 pages (0 to
255) with 256 (0 to 255) bytes in each page
✔ The higher order address bits (A8 to A15) select the page (A8 to A15 = 0000000
for Page 0; A8 to A15 = 11111111 for Page 255) and the lower order address bits
(A0 to A7) selects a memory location in a page (A0 to A7 = 00000000 for
memory location 0; A0 to A7 = 11111111 for memory location 255)

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 Designing with 8-Bit Microcontroller – 8051
8051 Memory Organization – The Von-Neumann Memory Model

✔ Combines the code memory and data memory address space into a single shared address space of 64KB
✔ The Code memory execution is always external
✔ A RAM chip holds the code memory and data memory
✔ The read signal to the RAM chip is generated by the ANDing the data memory read (RD\) signal and Program memory read
(PSEN\) signal
✔ The write signal to the RAM is generated by the WR\ signal of the processor
✔ Helpful in evaluation boards which allows the modification of code memory on a need basis without reprogramming the
code memory
13
 Designing with 8-Bit Microcontroller – 8051
8051 Memory Organization – Lower 128 Byte internal data memory (RAM)
Organization

✔ The lowest 32bytes of RAM (00H to 1FH) are grouped into 4 banks of 8 registers each. These registers are known
as R0 to R7 registers which are used as temporary data storage registers during program execution
✔ The next 16bytes of RAM with address 20H to 2FH is a bit addressable memory area. It accommodates 128 bits
(16bytes x 8), which can be accessed by direct bit addressing. The address of bits ranges from 00H to 7FH
✔ The byte wise storage and bitwise storage in the area 20H to 2FH shares a common physical memory area and it
cannot be used for both byte storage and bit storage simultaneously
✔ The upper 80 bytes of RAM (30H to 7FH) is organized as general purpose RAM
14
 Designing with 8-Bit Microcontroller – 8051
8051 Memory Organization – Bit & Byte wise storage in memory area 20H to
2FH

B0, B1, B3 …B7 represents the bit addresses

15
 Designing with 8-Bit Microcontroller – 8051
8051 Memory Organization – The Upper 128 bytes RAM (Special Function
Registers)

✔ The upper 128bytes of RAM when accessed by direct addressing, accesses the Special Function
Registers (SFRs)
✔ SFRs include Port latches, Status and control bits, Timer Control and Value registers, CPU Registers,
Stack Pointer, Accumulator etc
✔ Some of the SFR registers are only byte level accessible and some of them are both byte wise and
bitwise accessible. SFRs with address ends in 0H and 8H are both bit level and byte level accessible
✔ In the standard 8051 architecture, among the 128 bytes, only a few bytes are occupied by the SFR
and the rest are left unused and are reserved for future implementation
✔ SFR memory is not available to the user for general purpose scratch pad RAM usage
✔ The users can modify the contents of some of the SFR according to the program requirements
16
✔ Some of the SFRs are Read only where others provide Read/Write access
 Designing with 8-Bit Microcontroller – 8051
The 8051 Registers: CPU Registers
❑ Accumulator (ACC) (SFR-E0H)
Accumulator is the most important CPU register which acts as the heart of all CPU related Arithmetic operations.
Accumulator is an implicit operand in most of the arithmetic operations. Accumulator is a bit addressable register.

❑ B Register (SFR-F0H)
B register is a CPU register that acts as an operand in multiply and division operations. It also stores the remainder in
division and MSB in multiplication Instruction. B can also be used as general purpose register for programming.

❑ Program Status Word (PSW) (SFR-D0H)

The Program Status Word is an 8 bit, bit addressable Special Function register signaling the status of Accumulator
related operations and register bank selector for the scratch pad registers R0 to R7

17
 Designing with 8-Bit Microcontroller – 8051
The 8051 Registers: CPU Registers – Program Status Word

18
 Designing with 8-Bit Microcontroller – 8051
The 8051 Registers: Register bank Selection for Scratchpad Registers

✔ The power-on reset value for the bits RS1 and RS2 are 0 and the default register bank for
scratchpad registers R0 to R7 is 0
✔ The address range for R0 to R7 is 00H to 07H.
✔ A programmer can change the register bank by changing the values of RS1 and RS0

CLR RS0 ; Clear bit RS1

SETB RS1 ; Set bit RS1. Bank 2 is selected

19
 Designing with 8-Bit Microcontroller – 8051
The 8051 Registers: CPU Registers
❑ Data Pointer (DPTR) (DPL: SFR-82H, DPH: SFR-83H))
Data pointer (DPTR) is a combination of two 8bit register namely DPL (Lower 8bit holder
of DPTR) and DPH (Higher order 8bit holder of DPTR). DPTR is used for holding the
16bit address of the external memory to be read or written in external data memory
operations. DPH and DPL can be used as two independent 8bit general purpose registers
for application programming

❑ Program Counter (PC)

Program Counter (PC) is a 16bit register holding the address of the code memory to be
fetched. It is an integral part of the CPU and it is hidden from the programmer (It is not
accessible to the programmer)

❑ Stack Pointer (SP) (SFR-81H)

Stack Pointer (SP) is an 8bit register holding the current address of stack memory. Stack
memory is used for storing the Program counter address, other memory and register values
during a sub routine/function call. On power on reset the stack pointer register value is set
as 07H 20
 Designing with 8-Bit Microcontroller – 8051
The 8051 Registers: Scratchpad Registers
✔ The scratchpad registers R0 to R7 is located in the lower 32 bytes of internal RAM.
✔ It can be on one of the four banks, which is selected by the Register selector bits RS0
and RS1 of the PSW register
✔ On power on reset, by default, RS0 and RS1 are 0 and the default bank selected is
bank 0
✔ There are eight scratchpad registers and they are named as R0, R1…R7
✔ As the bank number changes the register address also offsets by the memory address
bank Number multiplied by 8
✔ Though the register bank can be selected between 0 and 3, there will be only one
active register bank at a time and it depends on the RS0 and RS1 bits of Program
Status Word (PSW)
✔ Registers R0 to R7 are used as general purpose working registers
✔ R0 and R1 also handle the role of index addressing or indirect addressing register
(@R0 and @R1 instructions)
✔ R0 and R1 can also be used for external memory access in place of DPTR, if the
memory address is 8 bit wide ((MOVX A, @R0)) 21
 Designing with 8-Bit Microcontroller – 8051
The Oscillator Unit

✔ All 8051 family microcontrollers contain an on-chip oscillator. This contains all necessary
oscillator driving circuits
✔ The only external component required is a ceramic crystal resonator
✔ The 8051 on chip oscillator circuit provides external interface option through two pins of the
microcontroller, namely, XTAL1 and XTAL2
✔ If an external ceramic resonator is used for clock generation, it should be connected across the
XTAL1 and XTAL2 pins of the microcontroller with two external capacitors
✔ Capacitors with values 15pF, 22pF, 33pF etc are used with the crystal resonator
✔ If an external stand alone oscillator unit is used, the output signal of the oscillator unit should be
connected to the pin XTAL1 of the chip and the pin XTAL2 should be left unconnected for a
CMOS type microcontroller (80C51) 22
 Designing with 8-Bit Microcontroller – 8051
The Execution Speed

✔ The execution speed of the processor is directly proportional to the oscillator clock frequency
✔ During program execution the instructions stored in the code memory is fetched, decoded and
corresponding action is initiated
✔ Each Instruction fetching consists of a number of Machine cycles
✔ The Instruction set of 8051 contains single cycle to four machine cycle instructions
✔ Each machine cycle is made up of a sequence of states called T states. The original 8051
Processor’s machine cycle consists of 6 T states and is named S1, S2, S3…S6
✔ Each T states in turn consist of two oscillator periods (Clock cycles) and so one machine cycle
contains 12 clock cycles
✔ For a one machine cycle instruction to execute, it takes 12 clock cycles. If the System clock
frequency is 12MHz, it takes 1microsecond (1µs) time to execute one machine cycle 23
 Designing with 8-Bit Microcontroller – 8051

Ports

✔ Port is a group of Input/ Output (I/O) lines

✔ Each port has its own port control unit, port driver and buffers
✔ The original version of 8051 supports 32 I/O lines grouped into 4 I/O Ports,
consisting of 8 I/O lines per port.
✔ The ports are named as Port 0, Port 1, Port 2 and Port 3
✔ One output driver and one input buffer is associated with each I/O line.
✔ All four ports are bi-directional and an 8bit latch (Special Function Register) is
associated with each port

24
 Designing with 8-Bit Microcontroller – 8051
Port 0

✔ Bi-directional port, which is used as multiplexed address/data bus in external data

memory/program memory operations
✔ Port 0 is designed in a way to operate in different modes. It acts as an I/O port in normal mode of
operation and acts as multiplexed address data bus in external data memory/program memory
operations
✔ Each pin of Port 0 possesses a bit latch which is part of the Special Function Register (SFR) for
Port 0, P0.
✔ The latch is a D Flip flop and it clocks in a logic value (either logic 1 or logic 0) from the internal
bus when a write to the corresponding latch signal is issued by the internal control unit
✔ The output drivers of Port 0 are formed by two FETs. Out of which the top FET functions as the
internal port pull-up 25
 Designing with 8-Bit Microcontroller – 8051
Port 0

✔ The pull-up FET driver for Port 0 is active only when the address line is
emitting 1s during external memory operations.
✔ The pull-up FET will be off on all other conditions and the Port 0 pins which
are used as output pins will become open drain (Open Collector for TTL logic)
✔ On writing a 1 to the corresponding port bit SFR latch, the bottom FET is
turned off and the pin floats and it enters in a high impedance state
✔ A logic 1 should be written to the corresponding Port 0 SFR latch to make the
corresponding Port 0 pin as input pin
✔ For proper functioning of Port 0 pin, an external pull-up resistor should be
connected to the corresponding Port 0 pin
✔ During external memory operations, 1s are written into P0 SFR
Port 0 SFR (P0) (SFR- 80H)

26
 Designing with 8-Bit Microcontroller – 8051
Port 1

✔ bi-directional port which is used as general purpose I/O Port

✔ Port 1 pin contains an internal pull-up resistor. The internal pull up for Port 1 is fixed and weak
✔ To make the Port 1 pins as input line, the corresponding SFR latch bit for Port 1 should be kept as 1
✔ Writing a 1 into any of the P1 SFR bit latch turns off the output driver FET and produces logic high
at the corresponding port pin
✔ When Port 1 pins are configured as inputs (by writing a 1 to the corresponding Port 1 SFR bit latch)
the pins are pulled high and they can source current when an externally connected device pulls the
port pin to low, signaling a logic 0 at the corresponding input line and places logic 0 to the internal
bus in response to a ‘Read Pin’ command
✔ If the externally connected device forces logic high, the ‘Read Pin’ control signal generated by a
‘Read Pin’ related command (E.g. MOV A,P1, MOV C,P1.0 etc) places logic high into the internal
bus. 27
 Designing with 8-Bit Microcontroller – 8051
Port 1
Port 1 SFR (P1) (SFR- 90H)

✔ Port 1 SFR is a bit addressable Special Function Register that acts as the bit
latch for each pins of Port 1
✔ The Reset value of Port 1 SFR is FFH (All bit latches set to 1).

28
 Designing with 8-Bit Microcontroller – 8051
Port 2

✔ Bi-directional I/O port designed to operate in two different modes

✔ Acts as general purpose I/O port in normal operational mode and acts as higher order address bus in
external data memory/program memory operations
✔ Port 2 emits the higher order byte of external memory address if the address is 16 bits wide
✔ During 16 bit wide external memory operations the base drive for the O/p driver FET is internally
switched to the Address line. If the address line is emitting a 1, the O/p driver FET is turned off and
the logic 1 is reflected on the O/p pin. If the Address line is emitting a 0, the O/p driver FET is
turned on and the logic 0 is reflected at the corresponding pin
✔ The content of Port 2 SFR remains unchanged during external memory access and it holds the
previous content as such
✔ If Port 2 is in external memory operation it cannot be used as general purpose I/O line.
29
 Designing with 8-Bit Microcontroller – 8051
Port 2
Port 2 SFR (P2) (SFR- A0H)

✔ Port 2 SFR is a bit addressable Special Function Register that acts as the bit
latch for each pins of Port 2
✔ The Reset value of Port 2 SFR is FFH (All bit latches set to 1).

30
 Designing with 8-Bit Microcontroller – 8051
Port 3

✔ Bi-directional I/O port which can act as general purpose I/O port and also configurable for
implementing alternative functions
✔ Port 3 is identical to Port 1 in operation
✔ All the settings that need to be done for configuring Port 1 as Input/ Output port is applicable to Port
3 also.
✔ Port 3 supports alternate Input/ Output functions
✔ The alternate I/O functions will come into action only if the corresponding SFR bit latch is set to
logic 1
Port 3 SFR (P3) (SFR- B0H)

31
 Designing with 8-Bit Microcontroller – 8051

Port 3 – Alternate Functions

32
 Designing with 8-Bit Microcontroller – 8051
Ports – ‘Read Pin’ & ‘Read Latch’ Operations
✔ The ‘Port Read’ Operations fall into
✔ ‘Read Latch’
✔ ‘Read Pin’
✔ The ‘Read Latch’ operation reads the content of the corresponding port latch
✔ The read ‘Port Latch’ operation is triggered by the control signal ‘Read Latch’.
✔ The ‘Read Latch’ control signal is generated internally on executing an instruction
implementing the ‘Read Latch’ operation
✔ The ‘Read-Modify-Write’ instructions which reads the port, modifies it and re-write
it to the port, operates on the port latch instead of port pins
✔ The ‘Read Pin’ operation reads the status of a port pin when the corresponding port
pin is configured as input pin
✔ The read ‘Port Pin’ operation is triggered by the control signal ‘Read Pin’
✔ The ‘Read Pin’ control signal is generated internally on executing an instruction
implementing the ‘Read Pin’ operation. MOV A, Px, MOV C, Px.y are examples for
‘Read Pin’ instructions
33
 Designing with 8-Bit Microcontroller – 8051
Ports – Port pin Interfacing

(a) Current Sourcing, (b) Current Sinking (c) Ideal Port pin interface for 8051

34
 Designing with 8-Bit Microcontroller – 8051
Ports – Port pin Interfacing

Design an 8051 microcontroller based system for displaying the binary numbers from 0 to 255 using 8
LEDs as per the specifications given below
– Use Atmel’s AT89C51/52 or AT89S8252 (Flash microcontroller with In System Programming
(ISP) support) for designing the system.
– Use a 12MHZ crystal resonator for generating the necessary clock signal for the controller.
– Use on-chip program memory for storing the program instructions.
– The 8 LEDs are connected to the port pins P2.0 to P2.7 of the microcontroller and are
arranged in a single row with the LED connected to P2.0 at the right most position (LSB) and
the LED connected to P2.7 at the left most position (MSB).
– The LEDs are connected to the port pins through pull-up resistors of 470 ohms and will
conduct only when the corresponding port pin is at logic 0.
– Each LED represents the corresponding binary bit of a byte and it reflects the logic levels of
the bit through turning ON and OFF the LED (The LED is turned on when the bit is at logic 1
and off when the LED is at logic 0).
– The counting starts from 0 (All LEDs at turned OFF state) and increments by one. The
counter is incremented at the rate of 5 seconds.
– When the counter is at 255 (0FFH, All LEDs are in the turn ON state), the next increment
resets the counter to 00H and the counting process is repeated. 35
 Designing with 8-Bit Microcontroller – 8051
Ports – Port pin Interfacing

36
 Designing with 8-Bit Microcontroller – 8051
Ports – Port pin Interfacing

37
 Designing with 8-Bit Microcontroller – 8051
ORG 0000H ; Reset vector
JMP 0050H ; Jump to code mem location 0050H
ORG 0003H ; External Interrupt 0 ISR location
RETI ; Simply return. Do nothing
ORG 000BH ; Timer 0 Interrupt ISR location
RETI ; Simply return. Do nothing
ORG 0013H ; External Interrupt 1 ISR location
RETI ; Simply return. Do nothing
ORG 001BH ; Timer 1 Interrupt ISR location
RETI ; Simply return. Do nothing
ORG 0023H ; Serial Interrupt ISR location
RETI ; Simply return. Do nothing
ORG 0050H ; Start of Program Execution
MOV P2, #0FFH ; Turn off all LEDs
CLR EA ; Disable All interrupts
MOV SP, #08H ; Set stack at memory location 08H
MOV R7,#00H ; Set counter Register R7 to zero.
REPEAT: CALL DELAY ; Wait for 5 seconds
INC R7 ; Increment binary counter
MOV A, R7 ;
CPL A; The LED's are turned on when corresponding bit is 0
MOV P2, A ; Display the count on LEDs connected at Port 2
JMP REPEAT ; Repeat counting
;####################################################################
;Routine for generating 5 seconds delay
;Delay generation is dependent on clock frequency
;####################################################################
DELAY: MOV R2, #50
LOOP1: MOV R1, #200
LOOP2: MOV R0, #248
LOOP3: DJNZ R0, LOOP3
DJNZ R1, LOOP2
DJNZ R2, LOOP1
RET
38
END ; END of Assembly Program
 Designing with 8-Bit Microcontroller – 8051
The 8051 Interrupt System
The basic 8051 and its ROMless counterpart 8031AH supports five interrupt
sources; namely two external interrupts, two timer interrupts and the serial
interrupt. The serial interrupt is an ORed combination of the two serial
interrupts; Receive Interrupt (RI) and Transmit Interrupt (TI)
Enabling Interrupts
The interrupt system of 8051 can be enabled or disabled totally under software
control. This is achieved by setting or clearing the global interrupt enable bit of
the Special Function Register Interrupt Enable (IE). Also each interrupt can be
enabled or disabled individually by setting or clearing the corresponding
interrupt enable bit in the SFR Interrupt Enable.
Interrupt Enable (IE) Register (SFR- A8H)

39
 Designing with 8-Bit Microcontroller – 8051
The 8051 Interrupt System - Interrupt Enable (IE) Register

40
 Designing with 8-Bit Microcontroller – 8051
The 8051 Interrupt System – Setting Interrupt Priorities
By default the 8051 architecture supports two levels of priority. The first priority
level is determined by the settings of the Interrupt Priority (IP) register. The
second level is determined by the internal hardware polling sequence. The
internal polling sequence based priority determination comes into action if two
or more interrupt requests of equal priority occurs simultaneously

Interrupt Priority (IP) Register (SFR- B8H)

41
 Designing with 8-Bit Microcontroller – 8051
The 8051 Interrupt System - Interrupt Priority (IP) Register

42
 Designing with 8-Bit Microcontroller – 8051
The 8051 Interrupt System – What happens when an Interrupt occurs
On identifying the interrupt request number, the following actions are generated by
the processor
1. Complete the execution of instruction in progress
2. The Program Counter (PC) content which is the address of the next instruction
in code memory which will be executed in normal program flow is pushed
automatically to the stack. Program Counter Low byte (PCL) is pushed first and
Program Counter High (PCH) byte is pushed next
3. Clear the corresponding interrupt flags if the interrupt is a timer or external
interrupt (only for transition activated (edge triggered) configuration)
4. Set interrupt in progress flip flop
5. Generate a long call (LCALL) to the corresponding Interrupt Service Routine
address in the code memory (Known as vectoring of Interrupt)

43
 Designing with 8-Bit Microcontroller – 8051
The 8051 Interrupt System – Interrupt Vectors
Each interrupt is assigned an Interrupt Vector in the code memory location. The
Interrupt Service Routine (ISR) for an interrupt should be placed at the
corresponding interrupt vector in the code memory. Each interrupt vector is
assigned fixed 8 bytes of memory. The ISR should confine within this 8 bytes

44
 Designing with 8-Bit Microcontroller – 8051
The 8051 Interrupt System – Different conditions blocking an Interrupt
It is not necessary that an interrupt should be serviced immediately on request. The
following situations can block an interrupt request or delay the servicing of an
interrupt request in 8051 architecture.
1. All interrupts are globally disabled by clearing the Enable All (EA) bit of
Interrupt Enable register.
2. The interrupt is individually disabled by clearing its corresponding enable bit in
the Interrupt Enable Register (IE).
3. An Interrupt of higher priority or equal priority is already in progress.
4. The current polling machine cycle is not the final cycle in the execution of the
instruction in progress (To ensure that the instruction in progress will be
completed before vectoring to the interrupt service routine. In this state the
LCALL generation to the ISR location is postponed till the completion of the
current instruction).
5. The instruction in execution is RETI or a write to the IE/IP Register. (Ensures
the interrupt related instructions will not make any conflicts) 45
 Designing with 8-Bit Microcontroller – 8051
The 8051 Interrupt System – Some general info on Interrupts
✔ If two interrupt requests of different priority levels are received simultaneously,
the request of higher priority interrupt is serviced.
✔ If interrupt requests of the same priority level are received simultaneously, the
order in which the interrupt flags are polled internally is served first. First
polled first served. (Also known as internal polling sequence)
✔ A low-priority interrupt can always be interrupted by a high priority interrupt.
✔ A low-priority interrupt in progress can never be interrupted by another low
priority interrupt.
✔ A high priority interrupt in progress cannot be interrupted by a low priority
interrupt or an interrupt of equal priority.

46
 Designing with 8-Bit Microcontroller – 8051
The 8051 Interrupt System – Returning from an Interrupt
✔ An Interrupt Service Routine should end with a RETI instruction as the last executable
instruction for the corresponding ISR
✔ Executing the RETI instruction informs the interrupt system that the service routine for
the corresponding interrupt is finished and it clears the corresponding priority-X (X=1
High priority) interrupt in progress flag by clearing the corresponding flip flop
✔ This enables the system to accept any interrupts with low priority or equal priority of
the interrupt which was just serviced
✔ Executing the RETI instruction POPs (retrieves) the Program Counter (PC) content from
Stack and the program flow is brought back to the point where the interruption occurred

✔ In operation RETI is similar to RET where RETI indicates return from an Interrupt
Service Routine and RET indicates return from a normal routine
✔ RET instruction only POPs the content of the Program Counter register and brings the
program flow back to the point where the interruption occurred

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 Designing with 8-Bit Microcontroller – 8051
The 8051 Interrupt System – Internal Polling Sequence for Interrupt Flags

Configuring External Interrupts

✔8051 supports two external interrupts namely External interrupt 0 and External
interrupt 1
✔The external interrupt can be configured as either level triggered or edge triggered
✔The interrupt configuring bits IT0 (For External Interrupt 0) and IT1 (For External
Interrupt 1) acts as the interrupt configuration bits
✔IT0 = 1 – Falling edge triggered; IT0 = 0 – Low level triggered

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 Designing with 8-Bit Microcontroller – 8051
The 8051 Timer Units
✔ The Standard 8051architecture supports two 16 bit hardware Timers that can be configured to
operate in either timer mode or external event counting mode.
✔ The Timers are named as Timer 0 and Timer 1.
✔ If the timers are configured in Timer function mode, the corresponding timer register is
incremented once in each machine cycle. Since one machine cycle consist of six T-States (12
clock cycles), the timer increment rate is 1/12th of the oscillator frequency (fosc/12)
✔ If the timer unit is configured for counter mode, the timer register is incremented in response
to a one to zero transition at the corresponding external port pin for counter mode
✔ The external input pins are sampled during S5P2 of each machine cycle. If the sample shows
a high in S5P2 of one machine cycle and a low in any of the next sampling time, the counter
register is incremented by one
✔ The count is updated only at S3P1 of the machine cycle following the machine cycle in which
the transition is detected
✔ It takes a minimum of two machine cycles to identify a 1 to 0 transition (2 machine cycle
corresponds to 24 clock periods). So the maximum count rate for external events is fosc/24,
where fosc is the oscillator frequency (Clock frequency).

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 Designing with 8-Bit Microcontroller – 8051
The 8051 Timer Units – Configuring Timers
Timer 0 and Timer 1 can be configured as Timer unit or counter unit by using
Timer/Counter mode select bit of the special function register Timer/Counter Mode
Control (TMOD). Timer 0 and Timer 1 can be operated in four different modes. The
mode selection is done by the timer mode select bits of TMOD register

Timer/Counter Mode Control Register (TMOD) (SFR- 89H)

Timer 1 Configuration Timer 0 Configuration

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 Designing with 8-Bit Microcontroller – 8051
The 8051 Timer Units – Configuring Timers
Timer/Counter Mode Control Register (TMOD) (SFR- 89H)

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 Designing with 8-Bit Microcontroller – 8051
The 8051 Timer Units – Timer Modes

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Designing with 8-Bit Microcontroller – 8051
Timer/Counter Control Register (TCON) (SFR- 88H)

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 Designing with 8-Bit Microcontroller – 8051
The 8051 Timer Units – Timer/Counter in Mode 0
Timer/Counter-0 and Timer/Counter-1 in mode 0 acts as a 13 bit timer/counter. The 13bit
register is formed by all 8bits of TH0 and the lower 5bits of TL0 for Timer/Counter-0
(All 8 bits of TH1 and the lower 5bits of TL1 for Timer/Counter-1)

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 Designing with 8-Bit Microcontroller – 8051
The 8051 Timer Units – Timer/Counter in Mode 1
Mode 1 operation of Timer (Counter) 0/ Timer (Counter) 1 is similar to that of mode 0
except the timer register size. The Timer register is 16bit wide in mode 1. The
timer/counter mode selection is done by the bit C/T of the register TMOD

If Timer 0 is configured as a timer and if the corresponding run control bit for Timer 0 (TR0 in
Timer Control Unit (TCON)) is set, registers TL0 & TH0 functions as 16bit register and starts
incrementing from its current value. The timer register is incremented by one on each machine
cycle. When the Timer register rolls over from all 1s to all 0s (FFFFH to 0000H), the corresponding
timer overflow flag TF0, present in TCON register is set. If the Timer 0 interrupt is in the enabled
state and no other conditions block the Timer 0 interrupt, Timer 0 interrupt is generated and is
vectored to its corresponding vector address 000BH.
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 Designing with 8-Bit Microcontroller – 8051
The 8051 Timer Units – Timer/Counter in Mode 2 (Autoreload)
Timer (Counter) 0/ Timer (Counter) 1 in mode 2 acts as 8bit timer/counter (TL0 for Timer
(Counter) 0 and TL1 for Timer (Counter) 1) with auto reload on the timer/counter
register overflow (TL0 or TL1).

If Timer 0 is configured as timer and if the corresponding run control bit for Timer 0 (TR0 in Timer
Control Unit (TCON)) is set, register TL0 functions as 8bit register and starts incrementing from its
current value. The timer register is incremented by one on each machine cycle. When the Timer
register rolls over from all 1s to all 0s (FFH to 00H), the corresponding timer overflow flag TF0,
present in TCON register is set and TL0 is reloaded with the value from TH0. TH0 remains
unchanged. If Timer 0 interrupt is in the enabled state and no other conditions block the Timer 0
interrupt, it is vectored to the corresponding vector address 000BH
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 Designing with 8-Bit Microcontroller – 8051
The 8051 Timer Units – Timer/Counter in Mode 3
Timer/Counter 0 in mode 3 functions as two separate 8bit Timers/Counters. TL0 acts as the
timer/counter register for Timer/Counter 0 and TH0 acts as the timer/counter register for
Timer/Counter 1. TL0 uses the Timer 0 control bits namely TR0, GATE, C/T, INT0 and
TF0. TL0 can run in either counter/timer mode by setting or clearing the C/T bit.
Counter operation is controlled by GATE, INT0 pin, T0 pin and TR0 bit as explained
earlier. But the operation is similar to that of Timer 0 in mode 3. In mode 3, TH0
supports only timer function and does not support counter function. TH0 counts only the
machine cycles, not external events.
The actual Timer 1 (TH1 TL1), when configured to run in mode 3, by using the Timer 1
configuration bits, stops its functioning and simply holds its count.

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 Designing with 8-Bit Microcontroller – 8051
The 8051 Serial Port
✔ The standard 8051 supports a full duplex (simultaneous data transmission and reception),
receive buffered (supports the pipelining system of the reception of second byte before the
previously received byte is read from the receive buffer) standard serial interface for serial
data transmission
✔ The Special Function Register SBUF provides a common interface to both serial reception
and transmission registers
✔ The serial reception and transmission register exist physically as two separate registers but
they are accessed by a read/write to the SBUF register
✔ The Serial communication module contains a Transmit control unit and a Receive control
unit.
✔ The transmit control unit is responsible for handling the serial data transmission and receive
control unit is responsible for handling all serial data reception related operations
✔ The Serial Port supports interrupts for indicating Serial data reception (Receive Interrupt RI)
and transmission (Transmit Interrupt TI)
✔ The Serial Port can be operated in four different modes. The mode selection is configured by
setting or clearing the SM0 and SM1 bits of the Special Function Register Serial Port Control
SCON.
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 Designing with 8-Bit Microcontroller – 8051
Serial Port Control Register (SCON) (SFR- 98H)
SCON is a bit addressable Special Function Register holding the Serial Port Control related
bits.

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 Designing with 8-Bit Microcontroller – 8051
The 8051 Serial Port
Serial Port Control Register (SCON) (SFR- 98H)

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 Designing with 8-Bit Microcontroller – 8051
The 8051 Serial Port
Serial Communication Modes

Mode 0:
The Mode 0 operation of serial port is same as that of the operation of a clocked shift
register. In Mode 0 operation Pin RXD (Port Pin P3.0) is used for transmitting and
receiving serial data and Pin TXD (Port Pin P3.1) outputs the shift clock. 8 data bits are
transmitted in this mode with LSB first. The baudrate is fixed for this mode and it is
1/12th of the oscillator frequency. Mode 0 is half duplex, meaning it supports only
unidirectional communication at a time. It can be either transmission or reception.

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 Designing with 8-Bit Microcontroller – 8051
The 8051 Serial Port - Serial Communication Modes
Mode 1:
In Mode 1, serial data pin TXD transmits the serial data and pin RXD receives the
serial data. Mode 1 is a full duplex mode, meaning it supports simultaneous
reception and transmission of serial data. 10 bits are transmitted or received in
Mode 1. The 10 bits are formed by the start bit, 8 data bits and one stop bit. The
stop bit on reception is moved to RB8 bit of SCON

Mode 1 Baudrate:
The baudrate is variable and it can be configured for different bauds
Baudrate = ((2SMOD) x Timer 1 Overflow rate) / (16 x 2)
Baudrate = 2SMOD x fOSC / ( (12 x [256-TH1]) x 16 x 2)
Timer 1 is configured in Auto-reload mode with Timer 1 interrupt disabled
SMOD is the baudrate doubler bit present in SFR PCON
TH1 is the Auto-reload count for Timer 1
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fOSC is the Crystal frequency in use
 Designing with 8-Bit Microcontroller – 8051
The 8051 Serial Port - Serial Communication Modes
Mode 1 – Commonly used Baudrates

Mode 1 baudrate 9600 is the most compatible to communicate with PC’s COM port The
communication parameter setting is: Baud =9600, 1 Start Bit, 8 Data Bits, 1 Stop bit, No
Hardware Flow Control

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 Designing with 8-Bit Microcontroller – 8051
The 8051 Serial Port - Serial Communication Modes
Mode 2 & 3:
11 bits are transmitted in Mode 2 & 3. The 11 bits are formed by the 8 data bits, 1 start bit (0), 1 stop
bit (1) and a programmable bit that acts as the 9th data bit. Mode 2 & 3 are full duplex and serial
data is transmitted through the pin TXD and reception is carried out through the pin RXD. TB8 bit
of SCON register is transmitted as the 9th bit. TB8 is programmable; it can be set to either 1 or 0.
TB8 bit can be used as a parity bit for transmission. The parity bit of PSW reflects the parity of
Accumulator content. If the data byte to be sent is the Accumulator content, the parity bit of PSW
can be directly moved to TB8 bit of SCON for transmitting it as the 9th data bit, which will give the
functionality of a parity enabled serial data transmission. On reception of serial data, the 9 th data bit
is moved into the RB8 bit of SCON register. If the serial reception is also parity enabled, RB8 can
be used for checking the parity of the received byte.

Mode 2 & 3 Baudrate:

Mode 2 baudrate is fixed and is given as 2SMOD x fOSC / 64
Depending on the SMOD bit, it can be either fOSC / 64 or fOSC / 32

Mode 3 baudrate is same as of Mode 1

2SMOD x fOSC / ( (12 x [256-TH1]) x 16 x 2)

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 Designing with 8-Bit Microcontroller – 8051
The 8051 Serial Port – Multi-processor Communication

✔ Multiprocessor/controller communication implements communication between

multiple processors/controllers connected to the same serial interface bus
✔ Each processor is assigned an address which is set in firmware
✔ One of the processor/controller acts as the master controller and the other controllers
act as slave controllers
✔ Mode 2 & 3 of 8051 serial transmission supports multiprocessor communication if the
SM2 bit present in the SCON register is set for each controller
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 Designing with 8-Bit Microcontroller – 8051
The 8051 Reset Circuitry
✔ Reset is necessary to bring the different internal register
values and associated internal hardware circuitry to a
known state
✔ Before putting the 8051 controller into operation a reset
should be applied to the controller
✔ Applying a reset loads the registers with default known
values and loads the program counter (PC) with 0000H.
This ensures that the program execution starts from the
start of the code memory (0000H) and stack will reset to
the memory location 07H
✔ The reset signal must be kept active until all the three of
the following conditions are met
1. The power supply must be in the specified range
2. The oscillator must reach a minimum oscillation
level to ensure a good noise to signal ratio and a
correct internal duty cycle generation
3. The reset pulse width duration must be at least two
machine cycles (24 Clock periods) when
conditions 1 and 2 are met
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 Designing with 8-Bit Microcontroller – 8051
The 8051 Power down Modes
✔ CMOS version of 8051 Supports two Power saving modes namely ‘IDLE’ and ‘Power Down’
✔ The Power saving modes can be enabled by configuring the power saving bits present in the
Power Control (PCON) special Function Register

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 Designing with 8-Bit Microcontroller – 8051
The 8051 Power down Modes
❑ IDLE Mode
Activated by setting the bit PCON.0 of the SFR Power Control register (PCON). The
Instruction setting the PCON.0 bit pushes the processor into an idle state where the internal
clock to the processor is temporarily suspended. Before putting the CPU into idle state, the
various CPU statuses like Stack Pointer (SP), Program Counter (PC), Program Status
Word (PSW) and Accumulator and all other register values are preserved as such. All port
pins will hold the logical states they had at the moment at which the idle mode is activated
by setting the PCON.0 bit. ALE and PSEN remains at logic high during Idle Mode. The
interrupt, Timer and Serial port sections continue functioning

✔The Idle mode is terminated by asserting any enabled interrupt or by applying a reset
signal at the RST pin
✔The interrupt can be any one of the external interrupt (INT0 or INT1) or Serial Interrupt.
On asserting the interrupt, the IDL bit (PCON.0) is cleared and the interrupt routine is
serviced
✔Resetting the processor clears the IDL bit (PCON.0) directly and at this point the processor
resumes program execution from where it left off, that is, at the instruction which
immediately follows the one that invoked the Idle Mode.
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 Designing with 8-Bit Microcontroller – 8051
The 8051 Power down Modes
❑ Power Down Mode
When the PD bit (PCON.1) is set by an Instruction, the Power down mode is activated.
The CPU stops executing instructions; clock signal to all internal hardware including timer
unit, Interrupt system and CPU is terminated. The contents of internal RAM and SFR are
maintained. All ports continue emitting their respective SFR contents. ALE and PSEN
signals are held at low. Power down mode can only be terminated through hardware Reset.
All SFRs are brought into their reset values. However the on-chip RAM retains their
contents to that of the values when the Power down mode is entered. The supply voltage
Vcc to the controller can be brought down to as low as 2V when the controller is in power
down mode. However before terminating the Power down mode with a hardware reset, the
supply voltage Vcc should be brought into the normal operating level.

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 Designing with 8-Bit Microcontroller – 8051
On Circuit Emulation (ONCE) Mode

✔ The On Circuit Emulation (ONCE) Mode helps in testing and debugging the
system without removing the microcontroller from the circuit
✔ The ONCE mode is invoked through the steps:
1. Pulling the ALE pin while the controller is in reset and PSEN is high
2. Holding the ALE pin low as Reset is de-activated
✔ In ONCE mode, Port 0 pins stays in the floating state and other Port pins, ALE
and PSEN are pulled high weakly internally
✔ The oscillator circuit remains active
✔ With these conditions an emulator or another controller can be used for driving
the circuit
✔ Normal operation of the target controller can be restored by applying a normal
reset

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 Designing with 8-Bit Microcontroller – 8051
The 8052 Microcontroller

✔ The 8052 microcontroller is a member of the 8051 family

✔ 8052 (DIP Version) is pin to pin compatible with the standard 8051 microcontroller
✔ The 8052 architecture implements the upper 128 bytes of user data RAM physically on
the chip and application programmers can access this memory through indirect
addressing, whereas the standard 8051 architecture doesn’t implement the upper 128
bytes of data RAM physically on the chip
✔ 8052 also implements an additional 16bit timer (Timer 2) and thus the total number of
timers available in 8052 is three, whereas the standard 8051 architecture implements
only two timers.
✔ T2CON is the SFR register implemented in 8052 for controlling the timer 2 operations
✔ The 16bit timer register is formed by the register pair TH2 and TL2
✔ Timer 2 supports interrupt and the interrupt vector location for Timer 2 is 002BH
✔ Timer 2 supports a special mode of operation called ‘Capture Mode’ and when the timer
is in capture mode the contents of TH2 and TL2 is captured to the capture SFR
RCAP2H and RCAP2L respectively when a 1 to 0 transition is detected at the P1.1 pin
of the microcontroller. The timer 2 interrupt is also generated if the timer 2 interrupt is in
the enabled state.
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