United International University
Dept. of Computer Science & Engineering (CSE)
Trimester: Spring 2024
CSE1326: Digital Logic Design Laboratory
Lab Report
0 1 1 2 4 2 0 4 9 9
ID:
Name: Avijit Biswas
Section: D
Group No: 3
Experiment No: 9
Experiment Name:
Arbitrary sequence counter, for both J-K and D flip-flop
Date of Performance: 1 5 0 6 2 0 2 5
Date of Submission: 1 9 0 6 2 0 2 5
I thereby certify that this lab report is prepared by me only. I did not copy any part of this from
anybody, and did not let other copy any part of my report.
Avijit
Signature of the Teaching Assistant Signature of the Student
Objectives:
1. Construct a 3-bit arbitrary counter using D flip-flops based on a user-defined counting
sequence.
2. Implement a 3-bit arbitrary counter using J-K flip-flops with customized state transitions.
3. Understand the design approach and functionality of arbitrary counters in comparison to
standard binary counters.
4. Analyze the state diagram and excitation table needed to implement non-sequential counting
patterns.
Theory:
Arbitrary Counter: An arbitrary counter is a digital circuit that follows a custom, user-defined
counting sequence instead of the standard binary or decimal order. It can be designed to skip certain
states or follow any specific pattern (e.g., 0 → 3 → 1 → 7 → 2), making it suitable for specialized
applications like digital locks, custom control systems, or communication protocols where unique
state transitions are required.
D Flip-Flop: A D flip-flop is a sequential logic element that captures and stores one bit of data. On
a specific clock edge (rising or falling), the value at the D input is transferred to the Q output.
Otherwise, it maintains its previous state. Due to its edge-triggered behavior, it is widely used in
registers, memory units, and other synchronous digital systems.
J-K Flip-Flop: A J-K flip-flop is a versatile sequential circuit with two inputs, J and K, which
determine the output behavior on a clock edge. Depending on the input values, it can set, reset, hold,
or toggle its output (with toggling occurring when J = K = 1). Its flexibility makes it useful in
applications such as ripple counters and frequency dividers, offering more complex control
compared to D flip-flops.
Apparatus:
Name Specification Quantity
IC 7476 3
IC 7174 3
IC 7408 Multiple
IC 7432 Multiple
Trainer Board - 1
Wire 5V -
Logisim Win 2.7.1 -
Table 1: Apparatus
Experimental Detail:
Design an arbitrary counter to follow the sequence: 3 → 2 → 7 → 1 → 5 → 0 → 3. If the counter
reaches 4, it should reset to 3, and if it reaches 6, it should reset to 2.
Arbitrary Counter State Diagram:
Arbitrary Counter State Table:
Present State Next State Inputs
Qa(t) Qb(t) Qc(t) Q2’D Q1’D Q0’D J2 K2 J1 K1 J0 K0
2 1 0
0 0 0 0 1 1 0 x 1 x 1 x
0 0 1 1 0 1 1 x 0 x x 0
0 1 0 1 1 1 1 x x 0 1 x
0 1 1 0 1 0 0 x x 0 x 1
1 0 0 0 1 1 x 1 1 x 1 x
1 0 1 0 0 0 x 1 0 x x 1
1 1 0 0 1 0 x 1 x 0 0 x
1 1 1 0 0 1 x 1 x 1 x 0
K-map:
D2
Q2/Q1Q0 00 01 11 10
0 0 1 0 1
1 0 0 0 0
D1
Q2/Q1Q0 00 01 11 10
0 1 0 1 1
1 1 0 0 1
D0
Q2/Q1Q0 00 01 11 10
0 1 1 0 1
1 1 0 1 0
J2
Q2/Q1Q0 00 01 11 10
0 0 1 0 1
1 x x x x
J2=Q1Q2 + Q1Q2'
K2
Q2/Q1Q0 00 01 11 10
0 x x x x
1 1 1 1 1
K2=Qb’Qc+QaQb
J1
Q2/Q1Q0 00 01 11 10
0 1 0 x x
1 1 0 x x
J1= Q2'
K1
Q2/Q1Q0 00 01 11 10
0 x x 0 0
1 x x 1 0
K1=Q0Q2
J0
Q2/Q1Q0 00 01 11 10
0 1 x x 1
1 1 x x 0
J0= Q0' + Q1'
K0
Q2/Q1Q0 00 01 11 10
0 x 0 1 x
1 x 1 0 x
K0= Q0'Q1 + Q0Q1'
Circuit Diagram:
Figure 1: Arbitrary Counter using D flip flop
Figure 2: Arbitrary Counter using J-K flip flop