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Computer Architecture and Algorithms Guide

The document discusses various computer architecture concepts including the use of general register and stack organized computers, in-order vs. out-of-order execution, and methods to improve Mean Time To Failure (MTTF). It also includes a programming task to simulate a single-digit decimal adder and an explanation of a checksum algorithm for data integrity in transmission. Additionally, it covers Rate Monotonic Scheduling (RMS) for thread priority assignment in real-time applications and poses a question regarding the schedulability of a system with three threads.

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7 views1 page

Computer Architecture and Algorithms Guide

The document discusses various computer architecture concepts including the use of general register and stack organized computers, in-order vs. out-of-order execution, and methods to improve Mean Time To Failure (MTTF). It also includes a programming task to simulate a single-digit decimal adder and an explanation of a checksum algorithm for data integrity in transmission. Additionally, it covers Rate Monotonic Scheduling (RMS) for thread priority assignment in real-time applications and poses a question regarding the schedulability of a system with three threads.

Uploaded by

markangelloyd
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

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i. Using a general register computer with 3 address constructions
ii. Using a stack organized computer with zero address operation instructions.
30. Differentiate in-order execution from out-of-order execution.
31. Write the three ways to improve MTTF.
32. Using your favorite programming language, develop a simulation of a single- digit decimal adder that
operates in the same manner as in Babbage's Analytical Engine. First, prompt the user for two digits in the
range 0-9: the addend and the accumulator. Display the addend, the accumulator, and the carry, which is
initially zero. Perform a series of cycles as follows:
a. If the addend is zero, display the values of the addend, accumulator, and carry and terminate the
program.
b. Decrement the addend by one and increment the accumulator by one.
c. If the accumulator incremented from nine to zero, increment the carry.
d. Go back to step a.
Test your code with these sums: 0+0, 0+1, 1+0, 1+2, 5+5, 9+1, and 9+9.
33. When transferring blocks of data over an error-prone transmission medium, it is common to use a checksum
to determine whether any data bits were lost or corrupted during transmission. The checksum is typically
appended to the transferred data record. One checksum algorithm uses these steps:
a. Add all of the bytes in the data record together, retaining only the lowest 8 bits of the sum.
b. The checksum is the two's complement of the 8-bit sum.
c. Append the checksum byte to the data record.
After receiving a data block with the appended checksum, the processor can determine whether the
checksum is valid by simply adding all of the bytes in are the record, including the checksum, together.
The checksum is valid if the lowest 8 bits of the sum zero. Implement this checksum algorithm using 6502
assembly language. The data bytes begin at the memory location stored in addresses $10-$11 and the
number of bytes (including the checksum byte) is provided as an input in the X register. Set the A register
to 1 if the checksum is valid, and to 0 if it is invalid.
34. Rate monotonic scheduling (RMS) is an algorithm for assigning thread priorities in preemptive, hard, real-
time applications in which threads execute periodically. RMS assigns the highest priority to the thread with
the shortest execution period, the next-highest priority to the thread with the next-shortest execution period,
and so on. An RMS system is schedulable, meaning all tasks are guaranteed to meet their deadlines
(assuming no inter-thread interactions or other activities such as interrupts cause processing delays) if the
following condition is met:

This formula represents the maximum fraction of available processing time that can be consumed by n
threads. In this formula, Ci is the maximum execution time required for thread i, and Ti is the execution
period of thread i.
Is the following system composed of three threads schedulable?

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