Gate Level Modeling Examples in Verilog

The document contains Verilog code for a full adder and a 4-bit full adder module. The full adder computes the sum and carry-out from two input bits and a carry-in. The 4-bit full adder uses four instances of the full adder to compute the sum and carry-out for 4-bit inputs.

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Gate Level Modeling Examples in Verilog

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rahulsinha5771

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2/12/25, 9:03 PM -> Click Here For Videogate_level_modeling_examples.

v
Lectures ; YT @AnishSaha_
E:\Youtube - Anish Saha\PrepFusion\Verilog\Verilog Codes\2. GATE Level Modeling\2. Gate Level modelling
examples\gate_level_modeling_examples.v

1
2
3 module fulladd (sum, c_out, a, b, c_in);
4 output sum, c_out;
5 input a, b, c_in;
6 wire s1, c1, c2;
7
8 xor (s1, a, b);
9 xor (sum, s1, c_in);
10 and (c1, a, b);
11 and (c2, s1, c_in);
12 or (c_out, c1, c2);
13 endmodule
14
15
16 module fulladd4 (sum, c_out, a, b, c_in);
17 output [3:0] sum;
18 output c_out;
19 input [3:0] a, b;
20 input c_in;
21 wire c1, c2, c3;
22
23 fulladd fa0(sum[0], c1, a[0], b[0], c_in);
24 fulladd fa1(sum[1], c2, a[1], b[1], c1);
25 fulladd fa2(sum[2], c3, a[2], b[2], c2);
26 fulladd fa3(sum[3], c_out, a[3], b[3], c3);
27 endmodule
28

-> Click Here For Video Lectures ; YT @AnishSaha_

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Gate Level Modeling Examples in Verilog

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Gate Level Modeling Examples in Verilog

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2/12/25, 9:03 PM -> Click Here For Videogate_level_modeling_examples.

-> Click Here For Video Lectures ; YT @AnishSaha_

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