Problem Set #7
1. Ben Bitdiddle has designed the circuit in the Figure to compute a registered four-input XOR
function. Each two-input XOR gate has a propagation delay of 100 ps and a contamination delay of
55 ps. Each flip-flop has a setup time of 60 ps, a hold time of 20 ps, a clock-to-Q maximum delay of
70 ps, and a clock-to-Q minimum delay of 50 ps.
tcd 50=
tpd =
100
tsefup 60
worst
=
tnold =
20
tcaq = 50
_ tpcaq : 7 O
lbest T : 3 tpdt
( tpcqttsetup
300 + 70 + 60 430ps
(a) If there is no clock skew, what is the maximum operating frequency of the circuit?
= =
8 = =
. ☆
ops
2 3 . GHz
(b) How much clock skew can the circuit tolerate if it must operate at 2 GHz?
f =
,EI
1 =
5o0 ps
,
Tu -tsuew 2
tpcattpd ftsetup tsetup 500 70 3tsaews Tc tpca tpd - -
= - -
00 -
60 =
7 ops
(c) How much clock skew can the circuit tolerate before it might experience a hold time. violation?
tskewtthold ≤ tacqt tcd tskew≤ taqttcd- thold =
50 t 50 yo
-
=
Bops
(d) Alyssa P. Hacker points out that she can redesign the combinational logic between the.
registers to be faster and tolerate more clock skew. Her improved circuit also uses three two-
input XORs, but they are arranged differently. What is her circuit? What is its maximum
frequency if there is no clock skew? How much clock skew can the circuit tolerate before it
might experience a hold time violation?
=← λ
)D yIhest
/worsy . ≥tpcqt2tpd t thok : o 200 - 60=33ops 7 +
34 Hz
j~
[ + 8
TC 330
7 ps
) □ 2) tskewtthold E I
:
tcqttd tskewEtaqttd
- thold= 50+ 100 -→0
D
= 3 obs
2. A field programmable gate array (FPGA) uses configurable logic blocks (CLBs) rather than logic
gates to implement combinational logic. The Xilinx Spartan 3 FPGA has propagation and
contamination delays of 0.61 and 0.30 ns, respectively, for each CLB. It also contains flip-flops with
propagation and contamination delays of 0.72 and 0.50 ns, and setup and hold times of 0.53 and 0 ns,
respectively.
(a) If you are building a system that needs to run at 40 MHz, how many consecutive CLBs can.
you use between two flip-flops? Assume there is no clock skew and no delay through wires
1
between CLBs. f Tc :
Tc I 25 ns =
-
0 9a + h + o 61 + 0. 5325 . 30
C 25ns t
=
t tpan ttsetup
+ = : . + 0 61 n) ns >
1 . n 38 9 .
1
ocof
. ,
(b) Suppose that all paths between flip-flops pass through at least one CLB. How much clock.
skew can the FPGA have without violating the hold time?
tskew f hhold ≤ tccqttea [. best case : one ch β )
=>tskew ≤ thold
tcqttd -
: 0 . 5 o + 0 . 30 -
ω = 0 , 0ons
3. For the following circuit, min and max delays of inverter are 1ns and 3ns, respectively. It’s !!!"
and !#!" are 5ns and 8ns, and setup and hold times are 4ns and 2ns, respectively. What’s max
frequency of operation of circuit?
tcdzins
inv
[ tpd = 3ns
taq=
( rco =
ns
tsetup : Ans
tnold = ans
T. 2 tsetup + tpd ttpcq 4 + 3+ δ 15ns
= =
f =
Fc ≤ ns
I5
G7 MHz
4. For the following circuit, min and max delays of comb ckt are 2ns and 4ns, respectively. !!!" and
!#!" of flip-flop are 5ns and 10ns, and setup and hold times are 8ns and 3ns, respectively. What are
safe regions for changes in X?
T . : tpc t
@ tpdttsetnp
=
tcqttpd
I tsetapITc -
)
ons
=
40 [ 10 +4 )
-
:
26 Ms
k
Tcly
l ly llly
ns
1
⑲
15 z thold ≤ tccqy tcd
"
3Ms =
5+3
=
7 ns ok
nnsafe