1.

Which register in 8086 is used to store the offset address of the next instruction to be
executed?
A) CS
B) IP
C) SP
D) BP
Answer: B
Bloom: Remember
2. In minimum mode, which pin indicates the status of the memory or I/O operation?
A) M/IO
B) S0, S1
C) ALE
D) DEN
Answer: A
Bloom: Understand
3. If the 8086 is configured in maximum mode, which signal is used for bus arbitration?
A) HOLD
B) RQ/GT
C) HLDA
D) INTA
Answer: B
Bloom: Apply
4. When the 8086 multiplexes address and data lines, which signal is used to latch the
address?
A) DEN
B) ALE
C) READY
D) BHE
Answer: B
Bloom: Apply
5. Given a timing diagram with T1, T2, T3, and T4 states, at which state does the 8086
sample the READY signal?
A) T1
B) T2
C) T3
D) T4
Answer: B
Bloom: Analyze

... (Continue up to 20 MCQs with similar analytical and applied focus, covering bus cycles,
minimum/maximum modes, timing, latching, and system configuration)

Topic 2: Addressing Modes and Instruction Set

(20 MCQs)

Sample MCQs:
 21. Which addressing mode is used in the instruction MOV AX, [BX+SI]?
A) Direct
B) Register
C) Register Indirect
D) Based Indexed
Answer: D
Bloom: Understand
22. If DS=2000H, SI=0100H, and the instruction is MOV AL, [SI], which physical address
is accessed?
A) 2000H
B) 2100H
C) 20100H
D) 200100H
Answer: C
Bloom: Apply
23. Which instruction will set the direction flag in 8086?
A) STD
B) CLD
C) STI
D) CLI
Answer: A
Bloom: Remember
24. Analyze the effect of INC [BX] on the flags. Which flag is NOT affected?
A) Zero
B) Carry
C) Sign
D) Parity
Answer: B
Bloom: Analyze
25. Given the instruction MOV AL, 25H, what addressing mode is used?
A) Immediate
B) Direct
C) Register
D) Indexed
Answer: A
Bloom: Remember

... (Continue up to 40 MCQs, focusing on effective address calculation, instruction decoding,

and analyzing instruction effects on registers and flags)

Topic 3: Assembly Language Programming and Array

Operations
(20 MCQs)

Sample MCQs:
 41. Given an array starting at offset 0100H, how do you access the 5th element (byte
array) using SI?
A) MOV AL, [SI+4]
B) MOV AL, [SI+5]
C) MOV AL, [SI+10]
D) MOV AL, [SI+8]
Answer: A
Bloom: Apply
42. Which instruction sequence sums all elements of a 10-element array in 8086?
A) Use a loop with ADD AL, [SI], increment SI, decrement counter
Bloom: Analyze
43. What will be the value of CX after the following code if CX initially is 5?

LOOP1: DEC CX
JNZ LOOP1

A) 0
B) 1
C) 5
D) -1
Answer: A
Bloom: Apply

44. If you want to reverse an array in memory, which addressing mode is best suited for
accessing both ends of the array?
A) Immediate
B) Direct
C) Based Indexed
D) Register Indirect
Answer: D
Bloom: Analyze
45. Given a subroutine to multiply two numbers, which registers should be preserved to
avoid data loss?
A) AX, BX
B) SI, DI
C) All used registers
D) Only AX
Answer: C
Bloom: Evaluate

... (Continue up to 60 MCQs, covering array sum, search, sort, stack usage, parameter
passing, and subroutine analysis)

Topic 4: I/O Processing, String Operations, and Interrupts

(20 MCQs)

Sample MCQs:
 61. Which instruction is used to input a byte from a port in 8086?
A) IN AL, port
B) OUT AL, port
C) MOV AL, port
D) LDA port
Answer: A
Bloom: Remember
62. What is the function of the 8089 I/O processor?
A) Directly controls the CPU
B) Offloads I/O tasks from the CPU
C) Handles arithmetic operations
D) Manages memory refresh
Answer: B
Bloom: Understand
63. Which string instruction compares two strings byte by byte?
A) MOVS
B) CMPS
C) SCAS
D) LODS
Answer: B
Bloom: Apply
64. If the direction flag is set, what is the effect on string operations?
A) Operate from lower to higher addresses
B) Operate from higher to lower addresses
C) No effect
D) Only affects arithmetic instructions
Answer: B
Bloom: Analyze
65. Which interrupt has the highest priority in 8086?
A) NMI
B) INTR
C) INT 0
D) INT 7
Answer: A
Bloom: Remember

... (Continue up to 80 MCQs, covering I/O ports, 8089 DMA, string manipulation, interrupt
priorities, vectoring, and interrupt service routines)

Topic 5: Arithmetic Coprocessors (8087) and Multiprocessor

Configurations
(20 MCQs)

Sample MCQs:
 81. Which instruction is used to add two floating-point numbers using the 8087
coprocessor?
A) FADD
B) ADD
C) FADDP
D) FADD and FADDP
Answer: D
Bloom: Remember
82. How does the 8086 communicate with the 8087 coprocessor?
A) Using separate buses
B) Through the system bus and instruction prefixing
C) Using interrupts
D) Through the stack
Answer: B
Bloom: Understand
83. Which configuration allows multiple processors to share the same system bus?
A) Daisy chaining
B) Multiplexing
C) Bus arbitration
D) Bus mastering
Answer: D
Bloom: Analyze
84. What happens if two 8086 CPUs try to access the same memory at the same time in a
multiprocessor system?
A) Both succeed
B) Bus arbitration decides which proceeds
C) Memory is corrupted
D) Both are halted
Answer: B
Bloom: Analyze
85. What is the main advantage of using an arithmetic coprocessor like the 8087?
A) Faster I/O
B) Increased floating-point performance
C) More interrupts
D) Larger address space
Answer: B
Bloom: Evaluate

Topic 1: Intel 16-bit Processor Architecture, System Bus, and

Timing

Q1.

The 8086 can operate in both minimum and maximum mode. Consider a system where
multiple processors share the bus. Which mode should be used, and what is the main
hardware difference in bus control between the two modes?
A) Minimum mode; bus control is internal
B) Maximum mode; bus control is handled by an external bus controller
C) Minimum mode; bus control is via the 8086’s S0, S1, S2 lines
D) Maximum mode; bus control is handled by the 8086 alone

Answer: B
Discussion:
In maximum mode, the 8086 is designed for multiprocessor systems. Here, bus control
signals (like RQ/GT) are managed by an external bus controller (8288), allowing multiple
processors to arbitrate for the bus. In minimum mode, the 8086 generates control signals
itself, suitable for single-processor systems.
Bloom’s Level: Analyze

Q2.

During a read cycle in 8086 minimum mode, at which state (T1, T2, T3, T4) is the
address/data bus switched from address to data, and why is the ALE signal important at this
point?

A) T1; ALE latches the address

B) T2; ALE enables data output
C) T3; ALE disables address output
D) T4; ALE enables data input

Answer: A
Discussion:
In T1, the 8086 puts the address on the multiplexed address/data bus and asserts ALE
(Address Latch Enable). This allows external latches to store the address before the bus
switches to data mode in T2. This demultiplexing is crucial for correct memory or I/O access.
Bloom’s Level: Analyze

Q3.

Given a timing diagram, how would you distinguish between a memory read and a memory
write cycle on the 8086? List at least two bus signals and their states for each operation.

A) M/IO = 1 for read, 0 for write; RD = 1 for read, WR = 1 for write

B) M/IO = 1 for both; RD = 0 for read, WR = 0 for write
C) M/IO = 1 for both; RD = 0 for read, WR = 1 for write
D) M/IO = 1 for memory, 0 for I/O; RD = 0 for read, WR = 0 for write

Answer: D
Discussion:
M/IO distinguishes memory (1) from I/O (0) cycles. RD (active low) is asserted (0) during a
read, and WR (active low) is asserted (0) during a write. Thus, a memory read: M/IO=1,
RD=0, WR=1; memory write: M/IO=1, RD=1, WR=0.
Bloom’s Level: Analyze

Topic 2: Addressing Modes and Instruction Set

Q4.

Given DS=2000H, BX=0100H, and the instruction MOV AL, [BX+05H], what physical
address is accessed, and what addressing mode is used?

A) 200105H; based indexed

B) 200105H; based with displacement
C) 200105H; register indirect
D) 200005H; direct

Answer: B
Discussion:
The instruction uses based with displacement addressing: the effective address is
BX+05H=0105H. The physical address is DS:BX+05H = 2000H*10H + 0105H = 200105H.
Bloom’s Level: Apply

Q5.

Analyze the effect of the instruction INC [SI] on the flag register. Which flags are affected
and why?

A) All flags
B) All except Carry
C) Only Zero and Sign
D) None

Answer: B
Discussion:
INC affects all flags except the Carry flag. It updates Zero, Sign, Parity, Auxiliary Carry, and
Overflow depending on the result. Carry is not affected because incrementing cannot
generate a carry out of the most significant bit.
Bloom’s Level: Analyze

Q6.
If you want to copy a block of memory from one location to another using string instructions,
which registers must be initialized, and which direction flag setting is required for forward
copy?

A) SI, DI, CX; DF=0

B) AX, BX, CX; DF=1
C) SI, DI, CX; DF=1
D) SI, DI; DF=0

Answer: A
Discussion:
SI (source index), DI (destination index), and CX (counter) must be initialized. For forward
copy (auto-increment), the Direction Flag (DF) must be cleared (DF=0) so SI and DI
increment after each operation.
Bloom’s Level: Apply

Topic 3: Assembly Language Programming and Array Operations

Q7.

Given an array of 10 bytes starting at offset 0200H, write the 8086 assembly code to sum all
elements. Which addressing mode is primarily used, and why?

A) Direct addressing
B) Immediate addressing
C) Register indirect addressing
D) Based indexed addressing

Answer: C
Discussion:
The typical code is:

MOV SI, 0200H

MOV CX, 0AH
MOV AL, 00H
LOOP: ADD AL, [SI]
INC SI
DEC CX
JNZ LOOP

Here, [SI] uses register indirect addressing to access array elements.

Bloom’s Level: Apply

Q8.
Suppose you need to reverse an array in memory. What is the best way to access both ends of
the array, and how would you implement the swap in assembly?

A) Use SI for start, DI for end, swap [SI] and [DI], increment SI, decrement DI
B) Use AX and BX, swap [AX] and [BX]
C) Use only SI, incrementing through the array
D) Use stack operations

Answer: A
Discussion:
For reversing, initialize SI to the start and DI to the end of the array. Swap the contents at [SI]
and [DI], then increment SI and decrement DI until they meet. This is efficient and uses
register indirect addressing.
Bloom’s Level: Apply

Q9.

In a subroutine that modifies registers AX, BX, and CX, which registers should be saved on
the stack at the start and restored at the end to preserve the calling program’s state?

A) Only AX
B) AX, BX, and CX
C) Only BX and CX
D) None

Answer: B
Discussion:
Any register modified by a subroutine and needed by the caller must be saved (PUSHed) at
entry and restored (POPped) before return. This preserves program correctness.
Bloom’s Level: Evaluate

Topic 4: I/O Processing, String Operations, and Interrupts

Q10.

The 8089 I/O processor can offload data transfer from the CPU. What is the main advantage
of using the 8089, and how does it communicate with the 8086?

A) Handles arithmetic operations; via the data bus

B) Handles I/O and DMA; via system bus and dedicated control signals
C) Handles interrupts; via INTR line
D) Handles string operations; via string bus
Answer: B
Discussion:
The 8089 acts as a DMA (Direct Memory Access) controller, freeing the CPU for
computation. It communicates with the 8086 via the system bus and uses dedicated control
signals for coordination.
Bloom’s Level: Analyze

Q11.

Given the string instruction REP MOVSB, what happens if CX=0000H at the start?

A) One byte is moved

B) No bytes are moved
C) An error occurs
D) CX is set to 1

Answer: B
Discussion:
REP MOVSB repeats MOVSB while CX ≠ 0. If CX=0, the instruction does nothing.
Bloom’s Level: Analyze

Q12.

During an interrupt, what sequence of operations does the 8086 perform before branching to
the interrupt service routine (ISR)?

A) Pushes IP and CS, then loads new IP and CS from vector

B) Pushes only IP, then jumps
C) Does nothing
D) Pushes all registers

Answer: A
Discussion:
The 8086 pushes the current IP and CS onto the stack to save the return address, then loads
new values from the interrupt vector table.
Bloom’s Level: Analyze

Topic 5: Arithmetic Coprocessors (8087) and Multiprocessor Configurations

Q13.
What is the role of the 8087 coprocessor in a system with an 8086 CPU, and how do the two
communicate during a floating-point operation?

A) 8087 handles all instructions; via separate bus

B) 8087 handles only integer math; via control signals
C) 8087 handles floating-point instructions; CPU and coprocessor fetch and decode
instructions in parallel, but only 8087 executes floating-point instructions
D) 8087 acts as a DMA controller

Answer: C
Discussion:
The 8087 is a numeric coprocessor. The 8086 fetches and decodes instructions; if it is a
floating-point instruction, both 8086 and 8087 decode it, but only the 8087 executes it. They
synchronize using a special protocol, sharing the system bus.
Bloom’s Level: Analyze

Q14.

In a multiprocessor configuration using 8086 CPUs, what mechanism ensures that only one
processor accesses the system bus at a time?

A) Priority encoder
B) Bus arbitration using RQ/GT lines
C) Interrupt controller
D) Timer circuit

Answer: B
Discussion:
The RQ/GT (Request/Grant) lines are used for bus arbitration, ensuring only one processor or
DMA controller uses the bus at a time, preventing conflicts.
Bloom’s Level: Analyze

Q15.

When using the 8087 coprocessor, what happens if a floating-point instruction is encountered
but the coprocessor is not present in the system?

A) The 8086 executes it

B) The instruction is ignored
C) The system hangs or generates an undefined opcode exception
D) The instruction is converted to integer

Answer: C
Discussion:
If the 8087 is absent, the 8086 will treat the floating-point instruction as an undefined opcode,
causing a fault or system hang, depending on the system design.
Bloom’s Level: Analyze

Q1. Array Summation and Flag Analysis

Given the following code:

MOV SI, 0200H

MOV CX, 05H
MOV AL, 00H
LOOP1: ADD AL, [SI]
INC SI
LOOP LOOP1

If the array at DS:0200H is {02, 04, 06, 08, 0A}, what is the value in AL and the status of the
Zero and Carry flags after execution?

A) AL = 24H, Zero=0, Carry=0

B) AL = 24H, Zero=1, Carry=0
C) AL = 24H, Zero=0, Carry=1
D) AL = 1E, Zero=0, Carry=0

Answer: A
Discussion:
Sum: 2+4+6+8+10=30 (1EH). But in hex: 02+04=06, +06=0C, +08=14, +0A=1E. So
AL=1EH (not 24H). Zero flag is cleared (AL≠0), Carry is not set (sum < 256).
Corrected Answer: D
Bloom’s Level: Analyze

Q2. String Copy with Direction Flag

Code:

CLD
MOV CX, 04H
MOV SI, 1000H
MOV DI, 2000H
REP MOVSB

If the source (DS:1000H) contains {11, 22, 33, 44}, what will be the contents of ES:2000H
after execution, and what does the CLD instruction ensure?

A) {44, 33, 22, 11}; increments SI/DI

B) {11, 22, 33, 44}; increments SI/DI
C) {11, 22, 33, 44}; decrements SI/DI
D) {44, 33, 22, 11}; decrements SI/DI

Answer: B
Discussion:
CLD clears the direction flag, so SI and DI increment after each MOVSB. The data is copied
in order from source to destination.
Bloom’s Level: Analyze

Q3. Loop and Conditionals

Code:

MOV CX, 0005H

MOV AX, 0000H
L1: ADD AX, CX
LOOP L1

What is the value of AX after execution?

A) 0x000F
B) 0x0014
C) 0x000A
D) 0x0019

Answer: B
Discussion:
Loop runs 5 times, adding CX each time as it decrements:
AX = 0 + 5 + 4 + 3 + 2 + 1 = 15 (0x000F).
But actually, after first iteration: AX=5, then AX=9, then 12, then 14, then 15.
So, 0+5=5, 5+4=9, 9+3=12, 12+2=14, 14+1=15 (0x000F).
Correct Answer: A
Bloom’s Level: Analyze

Q4. Subroutine and Stack Effect

Code:

MOV AX, 1234H

PUSH AX
CALL SUB1
POP BX
...
SUB1: MOV AX, 5678H
RET

What is the value in BX after execution?

A) 1234H
B) 5678H
C) The return address
D) Undefined
Answer: A
Discussion:
PUSH AX stores 1234H on the stack. CALL SUB1 pushes the return address, but POP BX
after returning from SUB1 pops the value 1234H into BX (the stack unwinds in LIFO order).
Bloom’s Level: Analyze

Q5. Addressing Mode Analysis

Code:

MOV AX, [BX+SI]

If BX=0100H, SI=0020H, DS=2000H, what is the physical address accessed, and what
addressing mode is used?

A) 200120H; Based Indexed

B) 200120H; Register Indirect
C) 200100H; Direct
D) 200020H; Based

Answer: A
Discussion:
Physical address = DS16 + (BX+SI) = 2000H10H + 0100H+0020H = 20000H+120H =
20120H. The mode is Based Indexed.
Bloom’s Level: Apply

Q6. Stack Pointer Analysis

Code:

MOV SP, 4000H

PUSH AX
PUSH BX
POP CX

If AX=1111H, BX=2222H, what is the value of CX and SP after execution?

A) CX=2222H, SP=3FFEH
B) CX=1111H, SP=3FFEH
C) CX=2222H, SP=3FFCH
D) CX=1111H, SP=4000H

Answer: A
Discussion:
PUSH AX (SP=3FFEH, [3FFEH]=1111H), PUSH BX (SP=3FFCH, [3FFCH]=2222H), POP
CX (CX=2222H, SP=3FFEH).
Bloom’s Level: Analyze

Q7. Flag Effect Analysis

Code:

MOV AL, 80H

ADD AL, 80H

Which flags are set after execution?

A) Carry, Zero
B) Sign, Overflow, Carry, Parity
C) Sign, Parity
D) Zero, Parity

Answer: B
Discussion:
80H + 80H = 100H (0x00, with carry).

 Carry: set (overflow beyond 8 bits)

 Sign: cleared (result is 0)
 Overflow: set (adding two positives gives negative in signed arithmetic)
 Parity: set (0x00 has even parity)
Correction: Sign is not set (result is 0). So, Carry, Overflow, Parity.
Bloom’s Level: Analyze

Suppose you are designing a system that requires both high-speed floating-point
operations and multi-threaded task execution. You can choose between adding an 8087
coprocessor to an 8086 CPU or building a multiprocessor system with two 8086 CPUs
(no 8087). Which configuration is better for scientific computation, and why?

 A) 8086 + 8087, because the 8087 provides dedicated floating-point hardware

B) Dual 8086, because two CPUs can run more instructions in parallel
C) 8086 + 8087, because floating-point software emulation is faster
D) Dual 8086, because the 8087 cannot work independently
 Answer: A
Discussion:
The 8087 coprocessor is specifically designed to accelerate floating-point operations,
which are common in scientific computing. While dual 8086 CPUs can execute more
instructions in parallel, without hardware floating-point support, floating-point tasks
will be much slower.
Bloom’s Level: Evaluate


 Q2.
 Given a multiprocessor system with two 8086 CPUs sharing memory, what is the
main challenge in maintaining data consistency, and which technique best addresses
it?
 A) Bus arbitration; use priority encoders
B) Memory access speed; use faster RAM
C) Cache coherence; use bus snooping or locking mechanisms
D) Instruction set compatibility; use the same assembler
 Answer: C
Discussion:
In multiprocessor systems, cache coherence is a major challenge—ensuring that all
CPUs see the most recent value of shared data. Bus snooping and locking mechanisms
are standard solutions.
Bloom’s Level: Evaluate


 Q3.
 You are tasked with improving the numeric performance of an 8086-based system.
You can either: (1) optimize software routines for floating-point math, or (2) add an
8087 coprocessor. Which approach offers the best performance improvement, and
what trade-offs must be considered?
 A) Software optimization, because it’s cheaper and flexible
B) Add 8087, because hardware acceleration is significantly faster
C) Both are equivalent
D) Software optimization, because the 8087 only supports integers
 Answer: B
Discussion:
Adding an 8087 coprocessor will yield much greater performance for floating-point
operations than software routines. The trade-off is cost and complexity of hardware
integration, but for numeric performance, hardware acceleration is superior.
Bloom’s Level: Evaluate


 Q4.
 A designer must choose between a tightly coupled multiprocessor system (shared
memory) and a loosely coupled system (distributed memory) for a real-time industrial
application. Which should be chosen and why?
 A) Tightly coupled, for fast communication and synchronization
B) Loosely coupled, for better fault tolerance
C) Tightly coupled, because it uses less hardware
D) Loosely coupled, because it is easier to program
 Answer: A
Discussion:
Tightly coupled systems provide faster inter-processor communication and easier
synchronization, which is critical for real-time applications. Loosely coupled systems
are better for fault tolerance but may not meet real-time constraints.
Bloom’s Level: Evaluate


 Q5.
  After integrating an 8087 coprocessor, a user notices that some legacy programs run
slower. Evaluate possible reasons and recommend a solution.
 A) The 8087 interferes with integer instructions; disable it
B) Legacy programs may not use 8087 instructions and may incur overhead;
recompile or update code to utilize 8087 features
C) The 8087 is incompatible; remove it
D) The 8087 is faulty; replace it
 Answer: B
Discussion:
Legacy programs written without 8087 instructions may not benefit from the
coprocessor, and in some cases, the additional hardware may introduce slight
overhead. The best solution is to update or recompile code to take advantage of the
8087’s floating-point instructions.
Bloom’s Level: Evaluate

Topic 1: Intel 16-bit Processor Architecture, System Bus, and Timing

Q1. (Apply)
The 8086 operates in minimum mode in a simple microcomputer. During a memory read
cycle, which signal is asserted to enable the external latch for address demultiplexing, and at
what timing state?

A) ALE during T1
B) RD during T3
C) WR during T2
D) DEN during T4

Answer: A
Explanation: ALE (Address Latch Enable) is asserted during T1 to latch the address from the
multiplexed bus.
Bloom: Apply

Q2. (Analyze)
Given a timing diagram with T1, T2, T3, T4, how can you distinguish between a memory
read and write operation using the status of M/IO, RD, and WR signals?

A) Both have RD low; only WR differs

B) M/IO=1, RD=0 for read; M/IO=1, WR=0 for write
C) M/IO=0 for memory; M/IO=1 for I/O
D) RD is always high in write cycles

Answer: B
Explanation: M/IO=1 for memory cycles; RD=0 for read, WR=0 for write.
Bloom: Analyze
Q3. (Evaluate)
You must design a system for high-speed data acquisition. Should you use the 8086 in
minimum or maximum mode, and why?

A) Minimum mode for single-processor simplicity

B) Maximum mode for better bus arbitration and expandability
C) Minimum mode for faster bus cycles
D) Maximum mode for reduced hardware

Answer: B
Explanation: Maximum mode supports advanced bus arbitration and is suited for complex,
high-speed, or multiprocessor systems.
Bloom: Evaluate

Topic 2: Addressing Modes and Instruction Set

Q4. (Apply)
If DS=2000H, SI=0030H, and the instruction is MOV AL, [SI+10H], what is the physical
address accessed?

A) 200040H
B) 200030H
C) 200010H
D) 200100H

Answer: A
Explanation: Effective offset = SI+10H = 0030H+10H = 0040H; physical = 2000H*10H +
40H = 20040H.
Bloom: Apply

Q5. (Analyze)
Which addressing mode is used in MOV AX, [BX+SI], and why is it useful for array
processing?

A) Register indirect; allows flexible base/indexing

B) Based indexed; supports 2D array addressing
C) Immediate; for constants
D) Direct; for absolute addresses

Answer: B
Explanation: Based indexed allows using two registers, useful for multi-dimensional arrays or
structures.
Bloom: Analyze

Q6. (Evaluate)
For code optimization, should you use immediate or register indirect addressing for repetitive
operations on large data arrays? Justify.

A) Immediate, for faster execution

B) Register indirect, for flexible memory access
C) Immediate, for less code
D) Register indirect, for smaller instruction size

Answer: B
Explanation: Register indirect is better for arrays, as it allows iteration and flexible memory
access.
Bloom: Evaluate

Topic 3: Assembly Language Programming and Array Operations

Q7. (Apply)
Given an array at DS:0200H = {01, 02, 03, 04}, what is the value of AL after this code?

MOV SI, 0200H

MOV CX, 4

MOV AL, 0

LOOP1: ADD AL, [SI]

INC SI

LOOP LOOP1

A) 10H
B) 0AH
C) 04H
D) 0CH

Answer: B
Explanation: 1+2+3+4=10 (0AH).
Bloom: Apply
Q8. (Analyze)
Given a subroutine that reverses an array, which registers must be preserved to avoid
corrupting the calling code, and why?

A) Only AX
B) All used registers
C) Only SI and DI
D) Only CX

Answer: B
Explanation: Any registers used in the subroutine should be saved/restored to prevent side
effects.
Bloom: Analyze

Q9. (Evaluate)
You need to sort a large array in assembly. Is it better to use bubble sort or insertion sort, and
why?

A) Bubble sort; easier to implement

B) Insertion sort; more efficient for nearly sorted data
C) Bubble sort; fewer instructions
D) Insertion sort; uses less memory

Answer: B
Explanation: Insertion sort is generally more efficient for small or nearly sorted arrays,
making it a better choice in assembly.
Bloom: Evaluate

Topic 4: I/O Processing, String Operations, and Interrupts

Q10. (Apply)
Which instruction copies a string of bytes from DS:SI to ES:DI, and how is the number of
bytes specified?

A) MOVSB; by setting CX
B) STOSB; by setting SI
C) LODSB; by setting DI
D) MOVSB; by setting AX

Answer: A
Explanation: MOVSB copies a byte from [DS:SI] to [ES:DI]; CX is the counter for REP
prefix.
Bloom: Apply
Q11. (Analyze)
An interrupt routine must save and restore registers. Why is this necessary, and what could
happen if not done?

A) To prevent stack overflow

B) To avoid corrupting main program state
C) To speed up the ISR
D) To enable nested interrupts

Answer: B
Explanation: Not saving/restoring registers may change values used by the main program,
causing bugs.
Bloom: Analyze

Q12. (Evaluate)
For high-speed disk I/O, should you use programmed I/O, interrupt-driven I/O, or DMA?
Justify your choice.

A) Programmed I/O; simplest

B) Interrupt-driven; best for all speeds
C) DMA; offloads CPU for high throughput
D) Programmed I/O; fastest for large blocks

Answer: C
Explanation: DMA allows data transfer without CPU intervention, maximizing throughput
for high-speed I/O.
Bloom: Evaluate

Topic 5: Arithmetic Coprocessors (8087) and Multiprocessor Configurations

Q13. (Apply)
When the 8086 and 8087 are connected, how does the CPU distinguish floating-point
instructions?

A) By opcode prefix
B) By special address lines
C) By hardware interrupt
D) By instruction queue

Answer: A
Explanation: The 8087 recognizes specific opcodes (ESC) and takes over for floating-point
instructions.
Bloom: Apply

Q14. (Analyze)
In a shared-memory multiprocessor system, what is the primary challenge when two CPUs
update the same variable, and how can it be resolved?

A) Bus contention; use faster memory

B) Data inconsistency; use locking mechanisms
C) Instruction set mismatch; use the same assembler
D) Power supply issues; use better regulators

Answer: B
Explanation: Locking ensures only one CPU updates the variable at a time, preventing race
conditions.
Bloom: Analyze

Q15. (Evaluate)
Given a choice between adding an 8087 coprocessor or a second 8086 CPU for numeric-
heavy scientific code, which provides greater performance and why?

A) 8087; dedicated floating-point hardware

B) 8086; better for multitasking
C) 8086; easier programming
D) 8087; more general-purpose

Answer: A
Explanation: The 8087 is designed for floating-point math, giving a much larger performance
boost for scientific workloads.
Bloom: Evaluate