ECT381- EMBEDDED SYSTEM DESIGN: MODULE-5

ABSTRACTION IN SOFTWARE DESIGN

Abstraction is a fundamental concept in software design that involves simplifying complex software
by modeling classes based on real-world or conceptual entities. It is a process of focusing on essential
properties while ignoring non-essential details. Abstraction provides a way to manage complexity and
build scalable, modular, and maintainable software systems.
Assembly-level abstraction
A programmer who writes at the assembly programming level works (almost) directly with the raw
machine instruction set, expressing the program in terms of instructions, addresses, registers, bytes
and words. Abstraction is important, then, at the assembly programming level, but all the responsibility
for supporting the abstraction and expressing it in terms of the machine primitives rests with the
programmer, who must therefore have a good understanding of those primitives and be prepared to
return frequently to think at the level of the machine.
High-level languages abstraction
A high-level language allows the programmer to think in terms of abstractions that are above the
machine level; indeed, the programmer may not even know on which machine the program will
ultimately run. Parameters such as the number of registers vary from architecture to architecture, so
clearly these must not be reflected in the design of the language.

The job of supporting the abstractions used in the high-level language on the target architecture falls
upon the compiler. Compilers are themselves extremely complex pieces of software, and the efficiency
of the code they produce depends to a considerable extent on the support that the target architecture
offers them to do their job.
DATA TYPES IN ARM
➢ 8-bit signed and unsigned bytes.
➢ 16-bit signed and unsigned half-words; these are aligned on 2-byte boundaries.
➢ 32-bit signed and unsigned words; these are aligned on 4-byte boundaries
FLOATING POINT DATA TYPES
Floating Point Data Types does not reserve a specific number of bits for the integer part or the
fractional part. Instead it reserves a certain number of bits for the number (called the mantissa or
significant) and a certain number of bits to say where within that number the decimal place sits (called
the exponent).

The floating number representation of a number has two part: the first part represents a signed fixed
point number called mantissa. The second part designates the position of the decimal (or binary) point
and is called the exponent. The fixed point mantissa may be fraction or an integer. Floating -point is

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always interpreted to represent a number in the following form:

m x re
Only the mantissa m and the exponent e are physically represented in the register (including their sign).
A floating-point binary number is represented in a similar manner except that is uses base 2 for the
exponent. A floating-point number is said to be normalized if the most significant digit of the mantissa
is 1.
The mantissa may be a fraction or an integer. The position of the radix point and the value of the radix
r are not included in the registers. For example, assume a fraction representation and a radix 10. The
decimal number 537.25 is represented in a register with m = 53725 and e = 3 and is interpreted to
represent the floating-point number
.53725 x 103
A floating-point number is said to be normalized if the most significant digit of the mantissa in
nonzero. So the mantissa contains the maximum possible number of significant digits. We cannot
normalize a zero because it does not have a nonzero digit. It is represented in floating-point by all 0’s
in the mantissa and exponent. Floating-point representation increases the range of numbers for a given
register.

Example −Suppose number is using 32-bit format: the 1 bit sign bit, 8 bits for signed exponent, and
23 bits for the fractional part. The leading bit 1 is not stored (as it is always 1 for a normalized number)
and is referred to as a “hidden bit”.

Then −53.5 is normalized as -53.5=(-110101.1)2=(-1.101011)x25 , which is represented as following

below,

Standard for Representing Floating Point Numbers

Single precision: 32 bits, consisting of...
Sign bit (1 bit)
Exponent (8 bits)
Mantissa (23 bits)
Double precision: 64 bits, consisting of…
Sign bit (1 bit)
Exponent (11 bits)

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Mantissa (52 bits)

IEEE Floating Point Representation

The Thumb bit in CPSR

ARM processors which support the Thumb instruction set can also execute the standard 32-bit ARM
instruction set, and the interpretation of the instruction stream at any particular time is determined by
bit 5 of the CPSR, the T bit. If T is set the processor interprets the instruction stream as 16-bit Thumb
instructions, otherwise it interprets it as standard ARM instructions.

The ‘T’ bit in the CPSR controls the interpretation of the instruction stream
❍ switch from ARM to Thumb (and back) by executing BX instruction
❍ exceptions also cause switch to ARM code

THE THUMB PROGRAMMER'S MODEL

The Thumb instruction set is a subset of the ARM instruction set and the instructions operate on a
restricted view of the ARM registers. The programmer's model is illustrated in Figure. The instruction
set gives full access to the eight 'Lo' general purpose registers r0 to r7, and makes extensive use of r13
to r15 for special purposes:
• r13 is used as a stack pointer.
• r14 is used as the link register.
• r15 is the program counter (PC).
These uses follow very closely the way these registers are used by the ARM instruction set, though
the use of r13 as a stack pointer in ARM code is purely a software convention, whereas in Thumb code
it is somewhat hard-wired. The remaining registers (r8 to r!2 and the CPSR) have only restricted

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access:
• A few instructions allow the 'Hi' registers (r8 to r15) to be specified.
• The CPSR condition code flags are set by arithmetic and logical operations and control conditional
branching.

Thumb-Arm Similarities:
➢ All Thumb instructions are 16 bits long. They map onto ARM instructions so they inherit many
properties of the ARM instruction set.
➢ The load-store architecture with data processing, data transfer and control flow instructions.
➢ Support for 8-bit byte, 16-bit half-word and 32-bit word data types where half-words are
aligned on 2-byte boundaries and words are aligned on 4-byte boundaries.
➢ A 32-bit unsegmented memory.
Thumb-ARM differences:
➢ Most Thumb instructions are executed unconditionally. (All ARM instructions are executed
conditionally.)
➢ Many Thumb data processing instructions use a 2-address format (the destination register is
the same as one of the source registers).
➢ (ARM data processing instructions, with the exception of the 64-bit multiplies, use a 3-address
format.)
➢ Thumb instruction formats are less regular than ARM instruction formats, as a result of the
dense encoding.
Thumb exceptions:
All exceptions return the processor to ARM execution and are handled within the ARM programmer's

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model. Since the T bit resides in the CPSR, it is saved on exception entry in the appropriate SPSR, and
the same return from exception instruction will restore the state of the processor and leave it executing
ARM or Thumb instructions according to the state when the exception arose.

THE ARM MEMORY INTERFACE:

The efficiency of the memory interface is an important determinant of the system performance, so
these principles must be well understood by the designer who wishes to develop a high-performance
system.
ARM bus signals:
The memory bus interface signals include the following:
➢ A 32-bit address bus, A[31:0], which gives the byte address of the data to be accessed.
➢ A 32-bit bidirectional data bus, D[31:0], along which the data is transferred.
➢ Signals that specify whether the memory is needed (mreq) and whether the address is
sequential (seq); these are issued in the previous cycle so that the memory control logic can
prepare appropriately.
➢ Signals that specify the direction (r/w) and size (b/w on earlier processors; mas[1:0] on later
processors) of the transfer.
➢ Bus timing and control signals (abe, ale, ape, dbe, lock, bl[3:0]).
Memory interface:

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The simplest form of memory interface is suitable for operation with ROM and static RAM (SRAM).
These devices require the address to be stable until the end of the cycle, which may be achieved by
disabling the address pipeline (tying ape low) on later processors or retiming the address bus
(connecting ale to mclk) on earlier processors. The address and data buses may then be connected
directly to the memory parts as shown in Figure 8 which also shows the output enable signals (RAMoe
and ROMoe) and the write enables (RAMwe).

This figure illustrates the connection of 8-bit memory parts, which are a standard configuration for
SRAMs and ROMs. Four parts of each type are required to form a 32-bit memory and an individual
device is connected to a single byte section of the bus. The notation on the figure shows the device's
bus numbering inside the device and the bus wires to which it is connected outside the device, so, for
example, the SRAM shown nearest the ARM has its pins D[7:0] connected to bus pins D[31:24]
which are connected to the ARM's pins D[31:24]. Since the bottom two address lines, A [1:0], are
used for byte selection, they are used by the control logic and not connected to the memory. Therefore
the address lines on the memory devices are connected to A [2] and upwards, the precise number used
depending on the size of the memory part.

Although the ARM performs reads of both bytes and words, the memory system can ignore the
difference (at the cost of some power wastage) and always simply supply a word quantity. The ARM
will extract the addressed byte and ignore the remainder of the word. Therefore the ROMs do not need
individual enables and using 16-bit devices causes no problems. Byte writes, however, do require
individual byte enables, so the control logic must generate four byte write enable controls. This makes
the use of wider RAMs difficult (and inefficient) unless they incorporate separate byte enables, since
writing an individual byte would require a read-modify-write memory operation. Since many
processors require support for writing bytes, it is likely that if RAMs do become available with a data
width greater than a byte, they will incorporate individual byte enables.
Control logic
The control logic performs the following functions:
➢ It decides when to activate the RAM and when to activate the ROM.
➢ It controls the byte write enables during a write operation.
➢ It ensures that the data is ready before the processor continues.

THE ADVANCED MICROCONTROLLER BUS ARCHITECTURE (AMBA)

The Advanced Micro controller Bus Architecture (AMBA) bus protocols is a set of interconnect
specifications from ARM that standardizes on chip communication mechanisms between various
functional blocks (or IP) for building high performance SOC designs. These designs typically have

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one or more micro controllers or microprocessors along with several other components — internal
memory or external memory bridge, DSP, DMA, accelerators and various other peripherals like USB,
UART, PCIE, I2C etc — all integrated on a single chip. The primary motivation of AMBA protocols
is to have a standard and efficient way to interconnecting these blocks with re-use across multiple
designs.

Following diagram (reference from the AMBA 2.0 spec) illustrates a traditional AMBA based SOC
design that uses three distinct buses for facilitating on-chip communications. These are the Advanced
High-Performance Bus (AHB), the Advanced System Bus (ASB), and the Advanced Peripheral Bus
(APB). The AHB is the backbone of the system and is designed specifically for high performance,
high-frequency components. This includes the connections of processors, on-chip memories, and
memory interfaces among others.

The ASB is an alternative to the AHB where some high-performance features are not needed. The
APB is a simplified interface designed for low bandwidth peripherals that do not require the high
performance of the AHB or the ASB. These include components like a UART, low-frequency GPIO,
and timers.

AMBA buses
Three buses are denned within the AMBA specification:
➢ The Advanced High-performance Bus (AHB) is used to connect high-performance system
modules. It supports burst mode data transfers and split transactions, and all timing is reference

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to a single clock edge.

➢ The Advanced System Bus (ASB) is used to connect high-performance system modules. It
supports burst mode data transfers.
➢ The Advanced Peripheral Bus (APB) offers a simpler interface for low-performance
peripherals.
Arbitration
A bus transaction is initiated by a bus master which requests access from a central arbiter. The arbiter
decides priorities when there are conflicting requests, and its design is a system specific issue. The
ASB only specifies the protocol which must be followed:
➢ The master, x, issues a request (AREQx) to the central arbiter.
➢ When the bus is available, the arbiter issues a grant (AGNTx) to the master.
Bus transfers
When a master has been granted access to the bus, it issues address and control information to indicate
the type of the transfer and the slave device which should respond.
Bus reset
The ASB supports a number of independent on-chip modules, many of which may be able to drive the
data bus (and some control lines). Provided all the modules obey the bus protocols, there will only be
one module driving any bus line at any time. Immediately after power-on, however, all the modules
come up in unknown states. It takes some time for a clock oscillator to stabilize after power-up, so
there may be no reliable clock available to sequence all the modules into a known state. In any case,
if two or more modules power-up trying to drive bus lines in opposite directions, the output drive
clashes may cause power supply crow-bar problems which may prevent the chip from powering up
properly at all. Correct ASB power-up is ensured by imposing an asynchronous reset mode that forces
all drivers off the bus independently of the clock.
Test interface
A possible use of the AMBA is to provide support for a modular testing methodology through the Test
Interface Controller. This approach allows each module on the AMBA to be tested independently by
allowing an external tester to appear as a bus master on the ASB.
Advanced Peripheral Bus
The ASB offers a relatively high-performance on-chip interconnect which suits processor, memory
and peripheral macrocells with some built-in interface sophistication. For very simple, low-
performance peripherals, the overhead of the interface is too high. The Advanced Peripheral Bus is a
simple, static bus which operates as a stub on an ASB to offer a minimalist interface to very simple
peripheral macrocells.

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Advanced High- Performance Bus

The AHB is intended to replace the ASB in very high performance systems. The following features differentiate
the AHB from the ASB:
➢ It supports split transactions, where a slave with a long response latency can free up the bus
for other transfers while it prepares its data for transmission.
➢ It uses a single clock edge to control all of its operations, aiding synthesis and design
verification.
➢ It uses a centrally multiplexed bus scheme rather than a bidirectional bus with tristate drivers.
➢ It supports wider data bus configurations of 64 or 128 bits.
Conditional Statements

Loop Statements

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For Loop Statements

While & do while Loop Statements

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Thumb Branch Instructions:

Thumb Software Interrupt Instruction:

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Thumb Data Processing Instructions:

The instruction is 16 bit wide. All operands are 32-bits wide and either come from registers or are
literals (‘immediate’ values). The result, if any, is 32-bits wide and goes into a register. Long multiplies
generate 64-bit results. All operand and result registers are independently specified. The data
processing instructions formats are given below:

Different types of Data Processing Operations are:

Arithmetic Operations

Bit-wise Logical Operations:

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Comparison Operations:

Shifted Register Operands:

Movement and Compare Instructions:

Thumb single register data transfer instructions:

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Thumb multiple register data transfer instructions:

Thumb breakpoint instruction:

Thumb implementation:
Thump instruction is 16 bit wide and ARM instruction is 32 bit wide. When a 16 bit Thump instruction
is given, the ARM processor is converting that instruction into a 32 bit ARM instruction before
processing. This can be done by a thump decompressor. The duty of Thump decompressor is to convert
16 bit instruction into a 32 bit instruction. The ARM processor is having a 32 bit decoder. If a Thump
instruction is received, it gets conveted to an equalent ARM instruction and then processed by
processor.

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The process of conversion is shown below:

Thumb applications:
❏ Thumb code properties:
❍ 70% of the size of ARM code
– 30% less external memory power
– 30% more instructions
❍ With 32-bit memory:

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– ARM code is 40% faster than Thumb code

❍ With 16-bit memory:
– Thumb code is 45% faster than ARM code
❏ For the best performance:
❍ use 32-bit memory and ARM code
❏ For best cost and power-efficiency:
❍ use 16-bit memory and Thumb code
❏ In a typical embedded system:
❍ use ARM code in 32-bit on-chip memory for small speed- critical routines
❍ use Thumb code in 16-bit off-chip memory for large non- critical control routines

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