ET Test 1 Solution
Section: Digital
1) Minimum number of DFF required to implement a synchronous counter, to
produce the sequence 0 - 1 - 2 - 1 - 3.
A. 1
B. 2
C. 3
D. 4
2) Let P and Q are the 8 bit registers used to represent the signed 2’s
complement notation. The arithmetic overflow occurs for the input data of
(P + Q) operation are:
A. P = 8F16, Q = 7F16
B. P = 7F16, Q = 4516
C. P = 8F16, Q = 0F16
D. P = FF16, Q = FE16
3) An 8-bit ripple carry adder is designed with 8 full adders. Tsum is the sum
delay and Tcy (10 ns) is the carry delay in one full adder. The worst time
needed to stabilize the result is 82ns. Then Tsum is? (Given Tsum > Tcy)
A. 9 ns
B. 10 ns
C. 11 ns
D. 12 ns
4) Which statement is true, reading the 4 variable Boolean function
A. To implement this function; 16 x 1 MUX is needed, without using
extra hardware.
B. Minimum two 8 x 1 MUXes are quired to implement this function.
C. One NOT gate and 8 x 1 MUX are needed to implement this
function.
D. Only 8 x 1 MUX is needed to implement this function without using
extra hardware.
5) Find the output of F0
x is the output for upper AND gate and y is the output for lower AND gate
6) Consider an excess-3 to BCD code converter as shown below, which
accepts excess-3 code as input and outputs the corresponding BCD code.
What is the output Y
A. A ⊕ B
B. C ⊕ B
C. C ⊕ D
D. A ⊕ D
7) What is the output Y?
A. (X1 + X2)’
B. X1 . X2’
C. X1’.X2
D. (X1 . X2)’
8) Consider a logic circuit that has a 4-bit binary number as an input and one
output. The output = ‘1’ if the input is a prime number > (one or zero).
Minimised boolean function F(A, B, C, D)?
A. BC'D + B'CD + A'B'D' + ACD
B. A'B'C'D' + BC'D + B'CD + A'CD
C. BD' + ABC + ACD' + B'C'D + AB'C'
D. BC'D + B'CD + A'B'D' + A'BD
9) Complete the above circuit by specifying the input ‘X’ by considering the
partial implementation of a 2 - bit counter using T-FF, following the
sequence 0 - 2 - 3 - 1 - 0 as shown below:
A. Q2'
B. Q2 + Q1
C. (Q2 ⊕ Q1)'
D. Q2 ⊕ Q1
10) Which of the following is not a degenerative logic?
A. NAND-AND
B. AND-AND
C. NOR-NAND
D. OR-OR
11) Find the sequence detected by the following detector?
A. 10101
B. 10110
C. 11001
D. 11101
SOLN: In a sequence detector’s FSM the representation followed is input/output
and output is 1 when a sequence is detected. Starting from (A) and moving
forward until output is ‘1’, we find 11101. So, the sequence detected is 11101.
12)If f(a, b, c) = a + b'c, then [f(a', b, c) . f(a, b, c') . {f(a, b, c)}']. Refer to image for
the same Boolean function
A. a' + b'
B. 0
C. (a + b + c)'
D. a + b +c
13)A boolean function f(a, b, c, d) is simplified to implement a hybrid logic under
practical assumptions of logic gates with non-zero propagation delay, which is
obtained by 3 - minterms. If the same function is implemented by ideal logic
gates, one module of the circuit has to be removed to decrease the circuit
complexity, but still the operation of the circuit can proceed under the same ideal
conditions. Let f(a, b, c, d) = ∑m(4, 12, 13, 15). Which of the following (portion of
circuit) can be removed from the practical circuit?
A.
B.
C. Both the combination of gates
D. None of the above
Hence the correct answer is none of the above.
14)The open loop transfer function of a system is: If the system
is in a unity feedback configuration, the lead compensator that can stabilize this
system is.
A.
B.
C.
D.
SOLN:
Put Gc(s) in the closed loop transfer function and select the option with the pools at the
left side of the s plane.
15) For the given circuit X = Y = 1, assume the propagation delay of XOR gate and
NOT gate = 5 ns. The frequency of steady - state oscillation of output z is?
A. 10 MHz
B. 20 MHz
C. 33 MHz
D. None of the above
16) If the cross-sectional area is 10-2cm2 with the length of p-region 0.2cm,
n-region length 0.1cm, ND is 1015cm-3 and NA is 1016cm-3 for a pn junction diode.
Then the series resistance offered by the junction.
A. 80Ω
B. 69Ω
C. 72Ω
D. 58Ω
SOLN:
To calculate the series resistance (Rs) of a PN junction diode, we consider the
resistance of the p-region and the n-region separately. The total series resistance
is the sum of the resistances of the p-type and n-type quasi-neutral regions:
Rs=Rp+Rn
Where:
𝐿
R= 𝑞.𝑢.𝑁.𝐴 ND=1015 cm−3 NA=1016 cm−3 μp ≈ 450 cm2/V
μn≈1350 cm2/V
Rp = 27.8 ohms Rn = 46.3 ohms
Rs = 74 ohms or near to 72 ohms
17) Consider a non-pipelined system which takes 60 ns to perform a task. The
same task can be performed in a K-segment pipeline with a pipeline cycle time of
10ns. For 100 tasks pipeline speed-up is around 5.66, then the value of K is
A. 4
B. 5
C. 6
D. 7
SOLN:
● Tnon-pipe= 100×60 = 6000ns
● Tpipe= (K+n−1)⋅cycle time => Tpipe = (K+100−1)⋅10 = (K+99)⋅10 ns
● Speedup = Tnon-pipe / Tpipe = 5.66
● K = 7
18) A 7-bit Hamming code with 4 data bits and 3 parity bits is received as
1110101. As compared with the transmitted code the error is in which bit
position? D7D6D5P4D3P2P1
A. Error in D6 position
B. Error in D3 position
C. Error in P2 position
D. Error in P4 position
SOLN:
P1 (position 1) checks bits: 1, 3, 5, 7 → bits = 1, 1, 1, 1 → sum = 4 → parity = 0
P2 (position 2) checks bits: 2, 3, 6, 7 → bits = 0, 1, 1, 1 → sum = 3 → parity =
P4 (position 4) checks bits: 4, 5, 6, 7 → bits = 0, 1, 1, 1 → sum = 3 → parity = 1
Now, build the syndrome (P4 P2 P1):
P4 parity wrong → 1
P2 parity wrong → 1
P1 parity correct → 0
So syndrome = 110 (binary) = 6 (decimal)
Final Answer: Error in position 6 → Error in D6 position
19) What will be the latency of a 4 - bit parallel in parallel out type shift register
made up with DFF with propagation delay of 3 ns and clock frequency of 200
MHz.
A. 5 ns
B. 8 ns
C. 15 ns
D. 20 ns
20) How many half adders (minimum) required to implement a 2x3 multiplier?
A. 1
B. 2
C. 4
D. 8
SOLN Process:
● The first product obtained from multiplying A0 with the multiplicand is
called as partial product 1.
● And the second product obtained from multiplying A1 with the multiplicand
is known as the partial product 2.
The structure of multiplication is explained below:
There are 6 product terms so to get all those 6 AND gates are required. To get
the addition of B1A0 and B0A1 we require one-half adder and this produces a
carry also. To get the addition of B2A0, B1A1 and C1 we require Full adder
because of 3 inputs and this also produces a carry. To get the B2A1 and C2 we
require one-half adder because of 2 inputs.
21) Consider the following circuit with source of PMOS with A and B as inputs
connected to VDD. What is the total number of minterms present in the output
expression of Y?
A. 1
B. 5
C. 7
D. 8
22) The transfer function of a servo system is . A first-order
compensator is designed in a unity feedback configuration so that the poles of
the compensated system are placed at -12j and -4. The transfer function of the
compensator system is
A.
B.
C.
D.
SOLN:
𝐺(𝑠)*𝐺𝑐(𝑠)
1+𝐺(𝑠)*𝐺𝑐(𝑠)
= Y(s) put options and the correct answer is B, by putting s = -4 and
-12j respectively in the characteristics equation: Gc(s) + s^2 + s.
23) In the figure the LED is Logic ‘1’ = 5V, logic ‘0’ = 0V
A. Emit light when X=0, Y=Z=1
B. Does not emit light when X=Y=Z=1
C. Does not emit light when X=0, Y=Z=1
D. None of the above
SOLN: When X = 0, Y = Z = 1, then
1. Borrow output is equal to 1.
2. Sum = 0 and Carry = 1.
3. Output of G1 = 1 and output of G2 = 1. subsequently , output of G3 is
also equal to 1.
4. Since, no potential difference is observed in such a case between
the LED diode, hence no light is emitted.
24) What is the simplified Boolean function at ‘F’?
A. a'
B. (a ⊕ b)'
C. d'
D. (abc)'
25) The logic circuit shown in the figure can be used as a:
A. NOT Gate
B. Buffer
C. Square Wave Generator
D. Astable Multivibrator
SOLN:
In the given image X is the input to I1 and S0 and, X’ is the input to I0. and Y0 is
connected to the XOR operation between X’ and output of MUX
Truth Table
X I0 I1 S0 MUX O/P Y0
0 1 0 0 1 0
1 0 1 1 1 1
Since Y0 = X for any input hence the circuit is a buffer.
Section: Analog
1. Which of the following is correct? considering the circuit shown below:
A. The Thevenin voltage seen from terminal a-b is 12V
B. The Thevenin voltage seen from terminal a-b is 15V
C. The Thevenin resistance seen from terminal a-b is 4Ω
D. None of the above
2. In the circuit shown, the Thevenin resistance seen from terminal a - b is?
A.
B.
C.
D. None of the above
3. The resonant frequency of the circuit below is? (IN RAD/S)
A. 5000
B. 2500
C. 1000
D. 500
4. For the circuit shown below, the transfer function Vout(s)/Vin(s)?
A.
B.
C.
D.None of the above
5. Two coupled coils with respective self-inductances L1 = 0.5H and L2 =
0.2H, have a coupling coefficient K = 0.5 and coil 2 has 1000 turns. If the
current in coil 1 is i1 = 5 sin 400t amperes, determine maximum flux setup
by coil 1.
A. 0.4 mWb
B. 0.5 mWb
C. 1.5 mWb
D. None of the above
6. For a sinusoidal signal x(t) = sin(t) having fourier transform X(w) the nature
of x(t) and value of x(0) respectively is?
A. Real and odd | x(0) = 0
B. Complex | x(0) = 1
C. Real and odd | x(0) = 2
D. Real | x(0)= −8/π2
SOLN: For an odd signal x(0) = 0
7. For The laplace transform of x(t) = cos(2t + pi/4)u(t) is?
A.
B.
C.
D.
SOLN:
8. A schmitt trigger with the upper threshold = 0V and hysteresis width of
0.2V, converts a 1 KHz sine wave of amplitude 4VPP into a square wave.
Calculate the time duration of the negative and positive portion of the output
waveform?
A.0.1 ms, 0.2ms
B. 0.48 ms, 0.52 ms
C. 0.52 ms, 0.48 ms
D.None of the above
9. A Colpitts oscillator has a coil with L = 120 uH, C1 = 300 pF and C2 = 1200
pF. Find the frequency of the oscillator and minimum gain required for the
amplifier to have sustained oscillations?
A. 1000 KHz and 4
B. 1854.6 KHz and 2
C. 937.8 KHz and 4
D.None of the above
10. For a silicon transistor, barrier potential at 25° C is 0.7V. Then the value
of the barrier potential at 65° C is?
A.0.7V
B. 0.8V
C. 0.6V
D.0V
11.Calculate the 3dB cutoff frequency due to 1uF capacitor given if β = 99, VT
= 25mV?
A.50 rad/s
B. 500 rad/s
C. 700 rad/s
D.1000 rad/s
12. For the BJT circuit shown, β = 50, VBE = 0.7V, then the required value
of resistance R to operate in the saturation region?
A.5KΩ
B. 2.8KΩ
C. 1.08KΩ
D.1KΩ
13. Determine the output voltage of a differential amplifier for the input
voltages of 300uV and 240uV. The differential gain of the amplifier is 5000
V/V and the value of CMRR is 100.
A.313.5mV
B. 31.35mV
C. 3.135mV
D.0V
14. For the oscillator circuit, the frequency of oscillations and required value
of RX, for sustained oscillations are:
A.1012 rad/s, 1/6 KΩ
B. 106 rad/s, 1/6 KΩ
C. 1012 rad/s, 24 KΩ
D.106 rad/s, 24 KΩ
15. In the frequency response of an amplifier, the frequency at 1KHz makes
the signal lose half of its maximum power. If the midband voltage gain is
80dB, then its unity gain frequency is?
A.1MHz
B. 10MHz
C. 100KHz
D.10KHz
16. In the circuit shown, the MOS is in the saturation region, having VT = 2V
and unCOX = 100uA/V2 and W/L = 10. Then the minimum value of VDD for
which the transistor remains in saturation mode (in volts)?
A.1.21V
B. 10V
C. 1.41V
D.2.5V
17. A zener diode is used as a 6V voltage regulator in the circuit shown. For
regulation the diode requires 5 mA of current. What is the load resistance
required for efficient operation of the circuit?
A.1.2 KΩ
B. 1 KΩ
C. 0.85 KΩ
D.0.4 KΩ
18. In the amplifier circuit, BJT has VBE = 0.6V, VCE, SAT = 0.2V, CPI = 10
pF, Cm = 5pF and β = 200 at a thermal voltage of 26 mV. Select the correct
option given below:
A.Mid frequency voltage gain in the circuit is 230.77.
B. Effective input capacitance looking into the base of BJT at
high frequencies is approximately 1170 pF.
C. Transconductance gm of the circuit is 1 mho.
D.None of the above
19. In the circuit shown below with matched transistors, beta is very high
|VBE| = 0.7 V. Then the value of the collector voltage of the Q3 transistor is
(in volts)?
A.3.58 V
B. 6.85V
C. 3.69 V
D.4.42 V
20. In the circuit shown below, M1 and M2 are identical MOSFETs with a
threshold voltage of 1V, transconductance parameter = 4 mA/V2. Then:
A.VGS of M1 is equal to VGS of M2 with I0 equal to 4 mA.
B. Current I0, in the circuit is 0 amperes
C. VGS of M1 is equal to VGS of M2 with I0 equal to 2 mA.
D.None of the above
21. For the given 3-stage oscillator circuit, the frequency to get sustained
oscillations is?
A.2.7KHz
B. 0.27KHz
C. 0.69KHz
D.6.9KHz
22. In the regulator circuit show, the power dissipation in the zener diode is
A.62mW
B. 100mW
C. 85mW
D.0mW
23. In the circuit shown, all BJTs are identical with β = 49, VBE = 0.7V.
The value of V0 is?
A.7.55V
B.1.3V
C.2.45V
D.8.7V
24.In the circuit shown, the range of RL for satisfactory operation of the
circuit?
A.RL > 100Ω
B. RL ≥ 50Ω
C. 50Ω < RL < 62.5Ω
D.50Ω < RL < 250Ω
25.In the circuit shown, Q1 and Q2 are matched transistors with VBE = 0.7 V, β
= 200. Then the ratio of I2 is to I1 is?
A.1
B. 0.99
C. 1.01
D.1.05