Seelam Chinna Venkata Narayana Reddy

VLSI Engineer | +91 9063958119 | cvnreddyseelam07@[Link] | [Link]

PROFILE
I am passionate about VLSI and eager to contribute my skills and knowledge in a dynamic and challenging work environment. With a strong foundation
in Front-End Design, Back-End Design, and Fabrication processes, I am detail-oriented and committed to delivering exceptional results. My goal is to
excel in VLSI while exploring the integration of AI/ML techniques to enhance the VLSI Design flow.
WORK EXPERIENCE
PDK Runset Developer (Physical Verification) Intern at STMicroelectronics July 2024- Present
• Implementing the 18 nm, 40nm, and 55nm Physical Verification Check (DRC) Codes with TVF/SVRF.
• Performing Co-validation checks for 18 nm, 40nm, and 55nm DRC Codes with Quality Assurance (QA) Cells or with Standard GDS Files.
Design and Verification Engineer Intern at SemiDesign November 2023- July 2024
• Implementing Turbo RISC V Integration with DMA Controller, honing RTL design and Verification expertise.
• Contributed to enhancing DMA 8257 controller architecture skills, gaining hands-on experience in Design and Verification.
RTL Design Intern at Maven Silicon August 2023-November 2023
• Implemented a RISC-V 32I project at Maven Silicon, honing expertise in Architectural Specification, RTL design, and Verification.
• Contributed to enhancing skills in RISC-V architecture, gaining hands-on experience in the intricacies of instruction set design.
Project Assistant at IIT Guwahati April 2023 -August 2023
• Developed a robust Data Security architecture using FPGA and SOC, bolstering data protection and system performance.
• Conducted thorough vulnerability assessments, implementing effective solutions to enhance system security.
SKILLS

• HDL/HVL:- Verilog, System Verilog, UVM (Newbie).

• EDA Tools:- Cadence (Layout XL, Virtuoso), Xilinx (Vivado), Mentor Graphics (Calibre, QuestaSim), Synopsys (Spyglass).
• Open Source Tools:- Bambu, Icarus, Covered, Yosys, Open STA, Open Road, Magic, K Layout.
• Protocols:- SPI, UART, I2C.
• Scripting Languages:- TCL, Python(Basics).
• Operating Systems:- Windows, Linux. Resume Format used for full-time Job hunt
EDUCATION

• BTech:- Vellore Institute of Technology, AP (ECE With VLSI Specialization with 8.98 CGPA). Aug 2021 -April 2025
• Class 11-12:- Vikas Junior College, AP (MPC with 97.2%). June 2019 -April 2021
• Class 10:- Sri Narayana Techno School (State Board with 9.8 CGPA) April 2018 -March 2019
PROJECTS

• Design & Verification of Turbo RISC-V 32 I Integration with DMA Controller.

• Low Power AI2C SoC for Long Distance and Multi-Slave Applications (IEEE Research paper).
• Open-source driven RTL-to-GDS Implementation of Single-Port RAM.
• Developed a common TVF/SVRF file for Physical Verification Checks of Plasma-Induced Gate Oxide Damage
CERTIFICATIONS

• NPTEL:- Verilog, VLSI Design Flow: RTL to GDS, Physical Design.

• Udmey:- System Verilog, UVM Newbie.
• Maven Silicon:- SOC Design, RISC V 32 I, Design Methodologies.
• Skill Nation:- Mastering The ChatGPT and other AI tools (Prompt Engineering).
• Purdue University:- Semiconductor Fabrication 101 Course.
ACHIEVEMENTS

• Published a Research paper in 𝐈𝐄𝐄𝐄-𝐀𝐈𝐒𝐏 𝟐𝟎𝟐𝟒. 2024 October

• Completion of #100daysofrtl in LinkedIn (21 k+ Followers & 2 M+ Impressions). 2023 December
• Winner of National Make-a-thon on ARM Processors. 2023 May
• Finalist in the National Code-a-thon on Verilog. 2023 April
 Seelam Chinna Venkata Narayana Reddy
Seelam Chinna Venkata Narayana Reddy
BTech in ECE(VLSI Specilization) at VIT-AP University

Resume format used for Internship Search

ch in ECE(VLSI Specilization) at VIT-AP University
About Me
Passionate about VLSI and seeking an opportunity to contribute
my skills and knowledge in a challenging work environment.
Strong understanding of digital and analog design, verification,
and synthesis. Detail-oriented and dedicated to delivering high-
My Contact quality [Link] to excel in the field of VLSI while exploring
the integration of Artificial Intelligence and Machine Learning
cvnreddyseelam07@[Link] techniques to enhance VLSI design and manufacturing
+91 9063958119 processes .
7-2,K Mangapuram, Andrapradesh
[Link]
vlsi-ai/
Projects
Skills Design & Verification of RISC V 32 I Integration with DMA 8237
RTL to GDS of CMOS Inverter IC using Cadence
Verilog Low Power RTL Design of Serial Communication Protocols
System Verilog FPGA based Car Parking embedded System
Python DroneShield : An Anti-Drone System using AIML
Prompt Engineering
Embedded C Work Experience
Physical Designing
Project Intern at IIT Guwahati May 2023 -Aug 2023
Education As an intern, I have developed Data Security Architecture
using FPGA and SOC, enhancing data protection and system
Vellore Institute of Technology, AP performance.
BTech,ECE (2021-2025) Internship at Maven siilicon Aug 2023 -Jan 2024
8.91 CGPA
As an intern, I have Implemented RISC-V 32I project at Maven
Vikas Junior College, AP
Silicon, enhancing skills in Architecture specifictions, RTL Design
Intermediate (2019-2021)
and Verification
97.2%
DV Engineer Intern at SemiDesign Jan 2023 -Present
Subjects learnt As an intern, I have Implemented DMA 8025 Controller, Which
Helps for Direct Acessing of memory And I have also verified it
ASIC,FPGA & SOC Design Flow
using system verilog and UVM Methodology
CMOS VLSI Design
Digital IC & Analog IC Design Certifications
Static Timing Analysis
Certificates of Verilog & RTL to GDS Course in NPTEL
Softwares learnt Certificate of System Verilog & UVM completion in Udemy
Xilinx Vivado Certified Expert in ChatGPT and other AI tools
Cadence Virtuso Certificate of Internship completion and SOC Course at
OpenSTA Maven Sillicon
Quartus Prime & Modelsim
Achievements
Strengths Finalist in the National Code-a-thon on Verilog (2023 Apr)
Critical Thinking Runner up in Make-a-thon on ARM Processors (2023 Apr)
Hard Working Winner in Code-a-thon on VLSI architectures (2023 Jul)
Communication Skills Completion of #100daysofrtl in LinkedIn (2023 Dec)