 addr1[20:17] + addr2[20:17]

 in1 | in2

Operands:

Operands can be any one of the data types. They can be constants, integers, real numbers, nets,
registers, times, bit-select etc.,
Example:
1. integer count, final-count;
final-count = count + 1
2. real a, b, c;
c = a - b; etc.,
Operators
Verilog has Ten different types of operators. They are
1. Arithmetic 6. Reduction
2. Logical 7. Shift operators
3. Relational 8. Concatenation
4. Equality 9. Replication
5. Bitwise logical 10. Conditional
1. Arithmetic Operators
There are two types of arithmetic operators:
 binary and
 Unary.
Binary arithmetic operators are
Example:
1. Multiply (*), If A = 4'b00ll; B = 4'b0l00; D = 6; E = 4; determine
2. divide (/),
a) A * B (Ans: 4'bll00)
3. add (+), b) D / E (Ans: Evaluates to 1)
4. subtract (-) and c) A + B (Ans: 4'b0lll)
5. modulus (%). d) B – A (Ans: 4'b000l)

If any operand bit has a value x, then the result of the entire expression is x.
Example:
in1 = 4'bl0lx;
in2 = 4'bl0l0;
sum = in1 + in2; // sum will be evaluated to the value 4'bx
Modulus operators produce the remainder from the division of two numbers.
Example:
13 % 3 // Evaluates to 1
16 % 4 // Evaluates to 0
-7 % 2 // Evaluates to -1, takes sign of the first operand
7 % -2 // Evaluates to +l, takes sign of the first operand

Unary operators
The operators + and - can also work as unary operators. They are used to specify the positive or
negative sign of the operand
Example:
-4 // Negative 4
+5 // Positive 5
2. Logical Operators
Logical operators are logical-and (&&), logical-or ( | | ) and logical-not ( ! ). Operators && and
| | are binary operators. Operator ! is a unary operator.
Logical operators follow the following conditions –
 Logical operators always evaluate to a l-bit value, 0 (false), 1 (true), or X
 If an operand is not equal to zero, it is equivalent to a logical 1 (true condition). If it is equal to
zero, it is equivalent to a logical 0 (false condition). If any operand bit is X or z, it is equivalent
to X (ambiguous condition).
Example:
I. A = 4’b0011; B = 4’b0000;
a) A && B // Evaluates to 0.
b) A || B // Evaluates to 1.
c) ! A / / Evaluates to 0.
d) !B// Evaluates to 1
II. A = 2'b0x; B = 2'bl0;
A && B // Evaluates to X.
III. (a = = 2) && (b = = 3) // Evaluates to 1 if both a = = 2 and b = = 3 are true.
// Evaluates to 0 if either is false.
3. Relational Operators
Relational operators are -
 greater-than (>),
 less-than (<)
 greater-than-or-equal-to (>= ) and
 less-than-or-equal-to (<=)
Example:
If A=4, B=3
X = 4'b1010, Y = 4'b1101, Z = 4'blxxx then evaluate
a) A <= B // Evaluates to a logical 0
 b) A > B // Evaluates to a logical 1
c) Y >= X // Evaluates to a logical 1
d) Y < Z // Evaluates to an X

4. Equality Operators
Equality operators are logical equality (==), logical inequality ( != =),case equality (===), and case
inequality (!= =) When used in an expression, equality operators return logical value 1 if true, 0 if
false. These operators compare the two operands bit by bit, with zero filling if the operands are of
unequal length.
Expression Description Possible Logical
Value
a == b a equal to b, result unknown if X or z in a or b 0, 1, X
a!=b a not equal to b, result unknown if X or z in a or b 0, 1, X
a===b a equal to b, including X and z 0, 1
a!== b a not equal to b, including X and z 0, 1

Problems:
A=4,B=3
X = 4’b1010 ; Y = 4’b1011;
Z = 4’b1xxz ; M = 4’b1xxz ; N = 4’b1xxx;

A == B // Results in logical 0
X != Y // Results in logical 1
X == Z // Results in X
Z === M //~esults in logical l (all bits match, including X and z)
z === N //~esults in logical 0 (least significant bit does not match)
M !== N // Results in logical 1

5. Bitwise Operators
Bitwise operators are
 negation (~),
 and(&),
 or ( | )
 xor ( ^ )
 xnor ( ^ ~ , ~^)).
Bitwise operators perform a bit-by-bit operation on two operands. They take each bit in one operand
and perform the operation with the corresponding bit in the other operand. If one operand is shorter
than the other, it will be bit extended with zeros to match the length of the longer operand.
Example:
X = 4’ b1010; Y = 4’ b1101; Z = 4’ b10x1;
~X // Negation. Result is 4'b0l0l
X&Y // Bitwise and. Result is 4'bl000
X|Y // Bitwise or. Result is 4'bllll
X^Y // Bitwise xor. Result is 4'b0lll
X ^~ Y // Bitwise xnor. Result is 4'bl000
X&Z // Result is 4'bl0x0

6. Reduction Operators

Reduction operators are

and (&), nor (~ | ),
nand( ~ &), xor ( ^ ), and
or ( | ), xnor (~ ^).
Reduction operators take only one operand. Reduction operators perform a bitwise operation on a
single vector operand and yield a l-bit result.
Example:
X = 4’ b1010
&X //Equivalent to 1 & 0 & 1 & 0. Results in l'b0
|X //equivalent to 1 | 0 | 1 | 0. Results in l'bl
^X //Equivalent to 1 ^ 0 A 1 ^ 0. Results in l'b0
7. Shift Operators
Shift operators are
 right shift ( >>) and
 left shift (<<).
These operators shift a vector operand to the right or the left by a specified number of bits

Example:
X = 4’b 1100

Y = X >> l; //Y is 4'[Link] right 1 bit.0 is filled in MSB position

Y = X << 1; //Y is 4'[Link] left 1 bit.0 filled in LSB position.
Y = X << 2; //Y is 4'[Link] left 2 bits.

8. Concatenation Operator
The concatenation operator ( {, ) provides a mechanism to append multiple operands. The operands
must be sized. Concatenations are expressed as operands within braces, with commas separating the
operands.
Example:
If A = l'bl, B = 2'b00, C = 2'b10, D = 3'bll0
Then what is
Y = {B , C} // Result Y is 4'b00l0
Y = {A , B , C , D , 3'b00l) // Result Y is 11'b10010110001
Y = {A , B[0], C[1] 1} // Result Y is 3'bl0l

9. Replication Operator
Repetitive concatenation of the same number can be expressed by using a replication constant. A
replication constant specifies how many times to replicate the number inside the brackets ( { } ).
Example:
Let reg A;
reg [1:0] B, C;
reg [2:0] D;
A = l'bl; B = 2'b00; C = 2'bl0; D = 3'bll0;
Y = { 4{A) } // Result Y is 4'bllll
Y = { 4{A} , 2{B} } // Result Y is 8'b11110000
Y = { 4{A} , 2{B} , C } // Result Y is 10'b1111000010

10. Conditional Operator

The conditional operator(? :) takes three operands.
Usage: condition-expr ? true-expr : false-expr ;
The condition expression (condition-expr) is first evaluated.
 If the result is true (logical 1),then the true-expr is evaluated.
 If the result is false (logical 0), then the false-expr is evaluated.
 If the result is X (ambiguous), then both true-expr and false-expr are evaluated and their results
are compared, bit by bit, to return for each bit position an X if the bits are different and the
value of the bits if they are the same
Conditional operations can be nested. Each true-expr or false-expr can itself be a conditional
operation.

Example:
Consider 4 – to – 1 multiplexer.
Let (A==3) and control are the two select signals of 4-to-1 multiplexer with n, m, y, x as the inputs and
out as the output signal.
Then assign out = (A == 3) ? ( control ? x : y ): ( control ? m : n) ;
Example:
Write the Verilog code for 4-to-1 Multiplexer, Using Conditional Operators
module multiplexer4-to-l (out, i0, il, i2, i3, sl, s0);
output out;
input i0, il, i2, i3;
input sl, s0;
assign out = sl ? ( S0 ? i3 : i2) : (SO ? il : i0);
endmodule ;

11. Precedence of operators :

Summary of operators in Verilog:

Examples:
Write Verilog code for 4-to-1 Multiplexer using data flow modelling

Method 1: using logic equation

S1 S0

S1n S0n
y0
i0

y1
i1 OUT

y2
i2
y3
D3

module mux4-to-l (out, i0, il, i2, i3, sl, s0);

output out;
input i0, il, i2, i3;
input sl, s0;

assign out = (~sl & ~s0 & i0) | (~sl & s0 & il) | (sl & ~s0 & i2) | (sl & s0 & i3) ;
endmodule.

Method 2: Using Conditional Operators

module multiplexer4-to-l (out, i0, il, i2, i3, sl, s0);
output out;
input i0, il, i2, i3;
input sl, s0;
assign out = sl ? ( S0 ? i3 : i2) : (SO ? il : i0);
endmodule

Write Verilog code for 4 Bit Full Adder using data flow modelling
Method 1: Using Dataflow Operators

module fulladd4 (sum, c-out, x, y, c-in);

output [3:0] sum;
output c-out;
input [3: 0] x, y;
input c-in;
assign {c-out, sum) = x + y + c-in;
endmodule

Method 2: full adder with carry look ahead

module fulladd4(sum, c-out, a, b, c-in);

output [3:0] sum;
output c-out;
input [3:0] a,b;
input c-in;

wire p0,g0, pl, g1, , p2, g2, , p3, g3;

wire c4, c3, c2, c1;
assign p0 = a[0] ^ b[0],
p1= a[1] ^ b[1],
p2 = a[2] ^ b[2],
p3= a[3] ^ b[3];

assign g0 = a[0] & b[0],

g1 = a[l] & b[1],
g2 = a[2] & b[2],
g3 = a[3] & b[3];

assign c1 = g0 | (p0 & c-in);

c2 = g1 | (p1 & g0) | (p1 & p0 & c-in);
c3 = g2 | (p2 & g1) | (p2 & p0 & c-in) | (p2 & p1 & p0 & c-in);
c4 = g3 | (p3 & g2) | (p3 & p2 & g1) | (p3 & p2 & p0 & c-in) | (p3 & p2 & p1 &
p0 & c-in);

assign sum[0] = p0 ^ c-in;

sum[1] = p1 ^ c1;
sum[2] = p2 ^ c2;
sum[3] = p3 ^ c3;

assign c-out = c4;

endmodule