Brief overview of Programmable Logic Devices:

Programmable logic devices such as PALs and FPGAs are required for implementation due to the
following reasons:
First, there is reasonable integration ability, allowing implementation of a significant amount of
functionality into one physical chip.
Second, there is the increased ability to change designs. Many of the programmable devices allow
easy reprogramming. In general, it is easier to change the design in case of errors or changes in
design specifications.
Currently, programmable logic comes in different types—
(1) devices that can be programmed only once and
(2) those that can be reprogrammed many times.

The following illustrates a classification of popular programmable logic devices. Programmable

logic can be considered to fall into field-programmable logic and factory-programmable logic.
The term field indicates that this type of device is programmed in the user’s “field” rather than
in a semiconductor fab. Often, many may refer to programmable logic to mean devices that are
field programmable. However, there are factory-programmable devices as well. These are
generic devices that can be programmed at the factory to meet customers’ requirements. The
programming technology uses an irreversible process; hence, programming can be done only
once. Examples of factory-programmable logic are mask-programmable gate arrays (MPGAs)
and read-only memories (ROMs).
PALs and PLAs contain arrays of gates. In the PLA, there is a programmable AND array and a
programmable OR array, allowing users to implement combinational functions in two levels of
gates. The PAL is a special case of a PLA, in that the OR array is fixed and only the AND array is
programmable.

Types of PLDs:

Simple Programmable Logic Devices (SPLDs):

Programmable Array Logic (PAL)
Programmable Logic Arrays (PLAs)
Programmable Read Only Memories (PROMs)

Complex Programmable Logic Devices (CPLDs):

Erasable Programmable Logic Device (EPLD)
Electrically Erasable Programmable Logic Device (EEPLD)

Field Programmable Gate Arrays (FPGAs):

SRAM Programmed FPGA
FLASH Programmed FPGA

Programmable logic devices basically contain an array of basic building blocks that can be used
to implement whatever functionality one desires. Different programmable devices differ in the
building blocks or the amount of programmability they provide.
Simple Programmable Logic Devices (SPLDs):

With the advent of CPLDs and FPGAs, the early-generation programmable logic devices, such as
ROMs, PALs, PLAs, and PLDs, can be collectively called simple programmable logic devices.

a. Read-Only Memories (ROM)

A read-only memory (ROM) consists of an array of semiconductor devices that are
interconnected to store an array of binary data. Once binary data is stored in the ROM, it can be
read out whenever desired, but the data that is stored cannot be changed under normal
operating conditions. If the combination ABC = 010 is applied to the input lines, the pattern
F0F1F2F3 = 0111 appears on the output lines. Each of the output patterns that is stored in the
ROM is called a word.
A ROM that has n input lines and m output lines contains an array of 2n words, and each word
is m bits long. The input lines serve as an address to select one of the 2n words.
 b. Programmable Logic Arrays:
A programmable logic array (PLA) performs the same basic function as a ROM. A PLA with n inputs
and m outputs can realize m functions of n variables. The internal organization of the PLA is
different from that of the ROM. The decoder is replaced with an AND array that realizes selected
product terms of the input variables. The OR array OR’s together the product terms needed to
form the output functions.
Next, we will realize the following functions using a PLA:

If we minimize each function separately, the result is

Eg.1. Find a minimum-row PLA to implement the following three functions:

Use Karnaugh maps to find common terms. Give the logic equations with common terms
underlined, the PLA table, and also a PLA diagram

Formulating the equations:

f = A’CD + ACD + A’BCD’

g = A’BC’D’ + AC’D + A’CD + (B’C’D or A’B’D)
h = A’BC’D’ + A’BCD’ + AD’ + ACD
 c. Programmable Array Logic (PAL):

The PAL (programmable array logic) is a special case of the programmable logic array in which
the AND array is programmable and the OR array is fixed. Because only the AND array is
programmable, the PAL is less expensive than the more general PLA, and the PAL is easier to
program.

This symbol represents an input buffer

A buffer is used since each PAL input must drive many AND gate inputs. When the PAL is
programmed, some of the interconnection points are programmed to make the desired
connections to the AND gate inputs. Connections to the AND gate inputs in a PAL are represented
by Xs as shown here:

As an example, we will use the PAL segment of the figure to realize the function. The Xs in the
following figure indicate that I1 and I’2 lines are connected to the first AND gate, and the I91 and
I2 lines are connected to the other gate.
When designing with PALs, we must simplify our logic equations and try to fit them into one (or
more) of the available PALs. Unlike the more general PLA, the AND terms cannot be shared
among two or more OR gates; therefore, each function to be realized can be simplified by itself
without regard to common terms. For a given type of PAL, the number of AND terms that feed
each output OR gate is fixed and limited.
As an example of programming a PAL, we will implement a full adder. The logic equations for
the full adder are as follows:

Sum = X’Y’Cin + X’YCin’ + XY’Cin’ + XYCin

Cout = XCin + YCin + XY

Complex Programmable Logic Devices (CPLD)

CPLDs are an extension of the PAL concept. In general, a CPLD is an IC that consists of a number
of PAL-like logic blocks together with a programmable interconnect matrix. CPLDs typically
contain 500 to 10,000 logic gates. Essentially, several PLDs are interconnected using a crossbar-
like switch and fabricated inside the same IC.
Xilinx CoolRunner XCR3064XL CPLD

Xilinx has two major series of CPLDs—the CoolRunner and the XC9500. The following figure
shows the basic architecture of a CoolRunner family CPLD, the Xilinx XCR3064XL. This CPLD has 4
function blocks, and each block has 16 associated macrocells

Architecture of Xilinx Coolrunner XCR3064XL CPLD

CPLD Implementation of a Parallel Adder with Accumulator:

Assume that we need to implement an adder with an accumulator, as in the following figure, in
a CPLD. The accumulator register needs one flip-flop for each bit. Each bit also needs to generate
the sum and carry bits corresponding to that bit.

One of the macrocells implements the sum function and an accumulator flip-flop. The other
macrocell implements the carry, which is fed back into the AND array. The Ad signal can be
connected to the enable input (CE) of each flip-flop via an AND gate (not shown). Each bit of the
adder requires eight product terms (four for the sum, three for the carry, and one for CE). For
each accumulator flip-flop.
Field Programmable Gate Arrays (FPGAs)

FPGAs are ICs that contain an array of identical logic blocks with programmable interconnections.
The user can program the functions realized by each logic block and the connections between
the blocks. FPGAs have revolutionized the way prototyping and designing is done in the world.
FPGAs provide several advantages over traditional gate arrays or mask programmable gate arrays
(MPGAs). FPGAs are standard off-the-shelf products. Manufacturing time reduces from months
to hours as one adopts FPGAs instead of MPGAs.

Organization of FPGAs:

● Programmable Logic Blocks

● Programmable Input/Output blocks
● Programmable routing resources
The “field” programmability in FPGAs is achieved by reconfigurable elements, which can be
programmed or reconfigured by the user. As mentioned, there are three major programmable
elements in FPGAs: the logic block, the interconnect, and the input/output block.
Programmable logic blocks are created by using multiplexers, look-up tables, and AND-OR or
NAND-NAND arrays.
One could classify them into four different basic architectures or topologies:
● Matrix-based (symmetrical array) architectures
● Row-based architectures
● Hierarchical PLD architectures
● Sea-of-gates architecture

Matrix-Based (Symmetrical Array) Architectures

The logic blocks in this type of FPGA are organized in a matrix-like fashion. The logic blocks in
these architectures are typically of a large granularity (capable of implementing 4-variable
functions or more). These architectures typically contain 8 x 8 arrays in the smaller chips and 100
x 100 or larger arrays in the bigger chips. The routing resources are interspersed between the
logic blocks.
Row-Based Architectures

These architectures were inspired by traditional gate arrays. The logic blocks in this architecture
are organized into rows. Thus, there are rows of logic blocks and routing resources. The routing
resources interspersed between the rows can be used to interconnect the various logic
blocks. Traditional mask-programmable gate arrays use very similar architectures.

Hierarchical Architectures

In some FPGAs, blocks of logic cells are grouped together by a local interconnect, and several
such groups are interconnected by another level of interconnect. For instance, in Altera APEX20
and APEX II FPGAs, 10 or so logic elements are connected to form what Altera calls a Logic Array
Block (LAB), and then several LABs are connected to form a MEGALAB. Thus, there is a hierarchy
in the organization of these FPGAs. These FPGAs contain clusters of logic blocks with localized
resources for interconnection.
Sea-of-gates Architecture

The sea-of-gates architecture is yet another manner to organize the logic blocks and interconnect
in an FPGA. The general FPGA fabric consists of a large number of gates, and then there is an
interconnect superimposed on the sea of gates. Plessey, a manufacturer that was in the FPGA
market in the mid-1990s, made FPGAs of this architecture. The basic cell used was a NAND gate,
in contrast to the larger basic cells used by manufacturers such as Xilinx.
FPGA Programming Technologies:

a. The SRAM Programming Technology

The SRAM programming technology involves creating reconfigurability by bits stored in static
RAM (SRAM) cells. The logic blocks, I/O blocks, and interconnects can be made programmable by
using configuration bits stored in SRAM.

An SRAM cell usually takes six transistors. Four cross-coupled transistors are required to create a
latch, and two additional transistors are used to control passing data bits into the latch. When
the Word Line is set to high, the values on the Bit Line will be latched into the cell. This is the
write operation. The read operation is performed by precharging the Bit Line and Bit Line9 to a
logic 1 and then setting Word Line to high. The contents stored in the cell will then appear on the
Bit Line.
 b. EPROM/EEPROM Programming Technology
In the EPROM/EEPROM programming technology, EPROM cells are used to control
programmable connections. Assume that EPROM/EEPROM cells are used instead of the SRAM
cells. A transistor with two gates—a floating gate and a control gate—is used to create an EPROM
cell. The following figure illustrates an EPROM cell.

EPROMs are slower than SRAM; hence, SRAM-based FPGAs can be programmed faster. EPROMs
also require more processing steps than SRAM. EPROM-based switches have high ON resistance
and high static power consumption. The EEPROM is similar to EPROM, but removal of the gate
charge can be done electrically.

c. The Antifuse programming technology

In some FPGAs, the programmable connections between different points are achieved by what
is called an “antifuse.” Contrary to fuse wires that blow open when high current passes through
them, the “antifuse” programming element changes from high resistance (open) to low
resistance (closed) when a high voltage is applied to it. Antifuses are often built using dielectric
layers between N1 diffusion and polysilicon layers or by amorphous silicon between metal layers.
Antifuses are normally OFF; permanently connected links are created when they are
programmed. The process is irreversible; hence, antifuse FPGAs are only one-time programmable
Antifuse technology has the advantage that the area consumed by the programmable switch is
small. Another advantage is that antifuse-based connections are faster than SRAM- and EEPROM-
based switches.

Programmable Interconnects:
A key element of an FPGA is the general-purpose programmable interconnect interspersed
between the programmable logic blocks. There are different types of interconnection resources
in all commercial FPGAs.
● General Purpose Interconnect
Many FPGAs use switch matrices that provide interconnections between routing wires
connected to the switch matrix. A switch matrix that supports every possible connection
from every wire to every other wire is very expensive. The connectivity is often limited to
some subset of a full crossbar connection.

● Direct Interconnect
Many FPGAs provide special connections between adjacent logic blocks. These
interconnects are fast because they do not go through the routing matrix. Many FPGAs
provide direct interconnections to the four nearest neighbors: top, bottom, left, and right.
  Global Lines
For purposes such as high fan-out and low-skew clock distribution, most FPGAs
provide routing lines that span the entire width/height of device. A limited
number (two or four) of such global lines are provided by many FPGAs in the
horizontal and vertical directions.

● Interconnects in Row based FPGAs

Many of the interconnect resources mentioned previously are very characteristic of
symmetric array devices with a two-dimensional array of logic blocks (e.g., Xilinx). In
devices that are row based, there are rows of logic blocks and there are channels of
switches to enable connections between the logic blocks.
Eg. 2. Given F = A`B` + BC` and G = AC + B`, write a complete Verilog module that realizes the functions F
and G using an 8-word x 2-bit ROM. Include the array type declaration and the constant declaration that
defines the contents of the ROM.