Axioms and Laws of Boolean Algebra

31 October 2020 20:18

AND Operation OR Operation NOT operation

Axiom 1: 0.0 = 0 Axiom 5: 0+0 =0 Axiom 9: 1' = 0

Axiom 2: 0.1 =0 Axiom 6: 0+1 =1 Axiom 10: 0' =1
Axiom 3: 1.0 = 0 Axiom 7: 1+0 =1
Axiom 4: 1.1 =1 Axiom 8: 1+1 = 1

Boolean Algebra Page 1

Shannon's Expansion Theorem
01 November 2020 17:44

Shannon's expansion theorem states that any switching expression can be

decomposed with respect to a variable A into two parts, one containing A and other
containing A'.
f(A,B,C,…) = A.f(1,B,C,…) + A'.f(0,B,C,…)
f(A,B,C,…) = [A+f(0,B,C,…) ]. [A'+f(1,B,C,…)]

Sanjiv Tokekar at 01-11-2020 18:05

Boolean Algebra Page 2

Demorganization
01 November 2020 18:18

CA+C'B+AB , X=C,Y=A,Z=B

XY+X'Z+YZ = XY+X'Z

Boolean Algebra Page 3

Reduction using Boolean Algebra
01 November 2020 18:18

C'=A'B'+AB Exclusive NOR

= BCD + AC'D' +ABCD+ABC'D

= BCD+ABCD + AC'D' + ABC'D
= BCD.(1+A) + AC'(D'+DB) (X+X'Y = X+Y)
= BCD + AC'(D'+B) (X=D', Y=B)
= BCD + AC'D' +ABC'

Boolean Algebra Page 4

Reduction using Boolean Algenbra
01 November 2020 18:32

Sanjiv Tokekar at 01-11-2020 19:29

f(A,B,C,D) = m(0,1,2,3,5,7,8,9,10,12,13)

A'B'

f( A,B,C,D) = A'B' + A'D+AC'+B'D'

= A'D+AC'+BD' SOP
f(A,B,C,D) = Л M(4,6,11,14,15)

f(A,B,C,D) = ( B'+C'+D).(A'+C'+D').(A+B'+D)

Boolean Algebra Page 5

 F1 =A'B' + A'BD
F2 = A'B'+ A'D

Boolean Algebra Page 6

Minimization of Switching Functions Karnaugh map
01 November 2020 18:32

F (a,b,c) =  m (1,2,5,6,7)

f(a,b,c) = B'C+BC'+AB

f(a,b,c) = Л M(0,3,4,)

f(a,b,c) = (B+C).(A+B'+C')

Boolean Algebra Page 7

K- Map
01 November 2020 18:31

f(a,b,c) =  m(0,2,3,4,5,6)
Implement using AOI as well as NAND-NAND logic

f(a,b,c) = a'b+ab'+c'

Boolean Algebra Page 8

K - Map
Monday, November 2, 2020 1:24 PM

f(a,b,c,d) = ЛM(2,8,9,10,11,12,14)
Derive NAND-NAND and NOR-NOR expressions
OR Derives SOP and POS expressions

f(a,b,c) = (A'+B).(A'+D).(B+C'+D) (POS form)

f(a,b,c) =  m(0,1,3,4,5,6,7,13,15)

f(a,b,c) = BD+A'D+A'C' + A'B (SOP form)

Boolean Algebra Page 9

K MAP
Monday, November 2, 2020 4:01 PM

f(a,b,c,d) =  m(0,2,4,6,7,8,10,12,13,15) SOP

as well as POS.

f(a,b,c) = c'd'+bd+abd+a'bc (SOP)

= c'd'+bd+a'd'+abd+bcd

f(a,b,c,d) = ЛM(1,3,5,9,11,14)

f(a,b,c,d) = (b+d').(a+c+d').(a'+b'+c'+d) POS

Boolean Algebra Page 10

K-Map
Monday, November 2, 2020 4:06 PM

f(a,b,c,d) = m(2,3,6,7,8,10,11,13,14)
Fmin = abc'd+ab'd'+a'c+b'c+cd'

Boolean Algebra Page 11

K-Map
17 November 2020 23:08

f(a,b,c,d) = m(0,1,2,3,5,7,8,9,10,12,13)
fmin = b'd'+ac'+a'd
f(a,b,c,d) =  M (4,6,11,14,15)
fmin = (a+b'+d)(a'+c'+d').(a'+b'+c')

Boolean Algebra Page 12

Implicants
17 November 2020 23:17

Prime Implicants, Essential Prime Implicants, Redundant Prime Implicants and

Selective Prime Implicants

Prime Implicant: Each square or rectangle made of adjacent minterms is called a

subcube. Each of these subcube is called a prime implicant (PI).
Essential Prime Implicant: The prime implicant which contains at least one 1 which
can not covered by any other prime implicant is called an essential prime implicant
(EPI).
Redundant Prime Implicant: The prime implicant whose each 1 is covered at least
by one EPI is called a redundant prime implicant (RPI).
Selective Prime Implicant: A prime implicant which is neither an essential prime
implicant nor a redundant prime implicant is called a selective prime implicant (SPI).
f(a,b,c,d) = m(3,4,5,7,9,13,14,15) (Identify EPI and RPI)

Boolean Algebra Page 13

EPI and SPI
17 November 2020 23:41

f(a,b,c,d) =  m(0,4,5,10,11,13,15)
EPI a'c'd',ab'c
SPI a'bc',bc'd,abd,acd
(4,5) and (13,15) a'bc'+abd
(5,13) and (13,15) bc'd+abd
(5,13) and (15,11) bc'd+acd

Boolean Algebra Page 14

Implicants
Wednesday, November 18, 2020 1:15 PM

f(a,b,c,d) = m(1,2,3,7,8,9,10,11,14,15)

Boolean Algebra Page 15

Do not care conditions
Wednesday, November 18, 2020 1:37 PM

f(a,b,c,d) = m(1,3,4,5,9,10,11) + dm(6,8)

Boolean Algebra Page 16

3-bit Binary to Gray converter
Wednesday, November 18, 2020 1:46 PM

B2 B1 B0 G2 G1 G0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0

Boolean Algebra Page 17

Thursday, November 19, 2020 7:56 PM

Boolean Algebra Page 18

False Prime Implicants
22 November 2020 22:13

The maxterms are called false minterms. The prime implicants obtained by using
the maxterms are called false prime implicants (FPIs). The FPI which contains
atleast one 0 which cannot be covered by any other FPI is called an essential
false prime implicant (EFPI).

f(a,b,c,d) = m(0,1,2,3,4,8,12)
=  M(5,6,7,9,10,11,13,14,15)
a
fmin = (b'+c').(a'+c')(a'+d')(b'+d')

Boolean Algebra Page 19

Redundant False Prime Implicant
22 November 2020 22:23

f(a,b,c,d) =  m(3,4,5,7,9,13,14,15)
=  M (0,1,2,6,8,10,11,12)
f(a,b,c,d) = (a+b+c)(a+c'+d)(a'+c+d)(a'+b+c')
All essential FPIs
(b+d) is Redundant False Prime Implicant (RFPI)

Boolean Algebra Page 20

Selective False Prime Implicant
22 November 2020 22:29

f(a,b,c,d) =  m(0,4,5,10,11,13,15)
=  M(1,2,3,6,7,8,9,12,14)
Essential FPI (a+c') (2,3,6,7) f1
Selective FPIs (a+b+d') (1,3) f2, (b'+c'+d) (6,14) f3, (a'+b+c) (8,9) f4 ,
(b+c+d') (1,9) f5, (a'+c+d) (8,12) f6 (a'+b'+d) (12,14) f7

1 2 3 6 7 8 9 12 14 f1 EFPI, (2,3,6,7)
f1 f4 ,f5,f6, f7 no term common
with f1
f2
f2 and f3 not good choice
f3 because add only one term.
f4 Terms not included
f5 (1,8,9,12,14) f4,f7,f5 one choice
f6 f5,f6,f7 another choice
F7

Boolean Algebra Page 21

Non Prime Implicant
22 November 2020 23:03

A non-prime implicant is a minterm which does not have any adjacent minterms.
Differentiate between a PI, Non PI, EPI, SPI

f(a,b,c,d) =  m(0,1,2,3,6,7,13,15)
= a'b'+a'c+abd (EPI)
bcd (RPI)
f(a,b,c,d) = m(2,3,6,7,10,11,12)
= b'c+a'c + abc'd'
b'c,a'c EPI
abc'd' Non Prime Implicant.

Boolean Algebra Page 22

Do not Care Conditions
22 November 2020 23:17

Minimize following expression using K-map

f(a,b,c,d) = m(1,4,7,10,13) +d(5,14,15)
fmin = a'bc'+a'c'd+bd+acd'

Boolean Algebra Page 23

Do not Care Conditions
22 November 2020 23:21

Minimize following expression using K-map

f(a,b,c,d) = m(4,5,7,12,14,15) +d(3,8,10)
fmin = ad'+bcd+a'bc'

Boolean Algebra Page 24

Do Not Care Conditions
22 November 2020 23:23

Minimize following expression using K-map

f(a,b,c,d) = m(1,3,7,11,15) +d(0,2,5)
fmin = a'b'+cd or a'd+cd

Boolean Algebra Page 25

22 November 2020 23:25

Obtain simplified expression in POS form using K-

map
f(a,b,c,d) = m(0,1,2,3,4,5) +d(10,11,12,13,14,15)
fmin = a'(b'+c')

Boolean Algebra Page 26

Two Level Form
22 November 2020 23:28

Implement the function f with following four two-level forms:

(a) NAND-AND (b) AND-NOR
c. OR-NAND (d) NOR-OR
f(a,b,c,d) = m(0,1,2,3,4,8,9,12)

AND-NOR ( using f')

f' = ac+bd+bc (AND-OR followed by inverter AND-NOR)
(NAND -AND)
f' = (a+b).(c+d).(b+c) (OR - AND -Invert so OR-NAND)
(NOR -OR)

Boolean Algebra Page 27

Wednesday, November 25, 2020 12:44 PM

Boolean Algebra Page 28

Tuesday, December 8, 2020 2:08 PM

Boolean Algebra Page 29

Wednesday, November 25, 2020 12:45 PM

Boolean Algebra Page 30

Wednesday, November 25, 2020 1:46 PM

AND-NOR
NAND-AND

Boolean Algebra Page 31

OR-NAND
Wednesday, November 25, 2020 1:53 PM

NOR-OR

OR-NAND

Boolean Algebra Page 32

Combinational Logic Design
30 November 2020 20:44

Half Adder
S = AB'+A'B
C = AB

Half Adder using AND-OR-INVERT

Boolean Algebra Page 33

Half Adder Using NAND Gates
30 November 2020 21:08

S = AB'+A'B
= AB'+AA'+A'B+BB'
= A(A'+B') + B (A'+B')
= A.(AB)' + B.(AB)'

Total Nand Gates 5.

Boolean Algebra Page 34

Half Adder Using NOR Gates
30 November 2020 21:18

S =AB'+A'B
= AB' +AA' + A'B + BB'
= A ( A'+B') + B(A'+B')
= (A+B)(A'+B')
S' = ((A+B)(A'+B'))'
S' = (A+B)' + (A'+B')'
S = ( (A+B)' + (A'+B')' )'
C = AB= ((AB)')'
= ( A'+B')'

Boolean Algebra Page 35

Full Adder
30 November 2020 21:32

S = A'B'Cin + A'BC'in + AB'C'in + ABCin

= (A'B+AB')C'in + (A'B' +AB)Cin

Boolean Algebra Page 36

Full Adder
30 November 2020 21:46

Boolean Algebra Page 37

Full Adder using AND-OR-INVERT Logic
30 November 2020 22:10

Boolean Algebra Page 38

Full Adder Using NAND Gates
30 November 2020 22:15

Boolean Algebra Page 39

Half Subtractor
30 November 2020 22:26

Boolean Algebra Page 40

Direct NAND Gates Half Adder
Tuesday, December 1, 2020 12:34 PM

Boolean Algebra Page 41

Subtractor
Tuesday, December 1, 2020 1:20 PM

Half Substractor

A B b d
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

d= A'B+AB'
b= A'B

Boolean Algebra Page 42

Full Substractor
Tuesday, December 1, 2020 1:28 PM

A-B-bin
A B bin bout d
0 0 0 0 0
bout = A'B'bin + A'Bb'in +A'Bbin + ABbin
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

d= A'B'bin + A'Bb'in + AB'b'in + Abbin

d=

A-B-bin 0 b=1 d=1

- -
1 B bin = 1
------------------------------ ------------------------
b=1 d=1 b=1 d=0

Boolean Algebra Page 43

Half subtractor using NOR Gates
30 November 2020 23:21

Boolean Algebra Page 44

Carry Look ahead Adder
30 November 2020 23:40

If An and Bn are 1 Carry is to be generated

irrespective of Cn =1 or 0. This is called
generated carry, expressed as
Gn = [Link] .
Available at the output through OR gate.
Express Pn =

If Pn = 0 then carry will not be propagated. Carry will be

propagated only If Pn =1. Pn is call propagate carry.

General Expression

Boolean Algebra Page 45

BCD Adder0
Monday, December 7, 2020 1:50 PM

S4 S3 S2 S1 S0 Decimal No.
0 1 0 1 0 1 0 (0001 0000)
0 1 0 1 1 11
0 1 1 0 0 12
0 1 1 0 1 1 3
0 1 1 1 0 1 4 (0001 0100)
0 1 1 1 1 1 5
1 0 0 0 0 16
1 0 0 0 1 17
1 0 0 1 0 18
1 0 0 1 1 1 9 (0001 1001)

Boolean Algebra Page 46

BCD Adder
07 December 2020 23:03

Boolean Algebra Page 47

Excess-3 Adder
07 December 2020 23:17

Boolean Algebra Page 48

Binary to BCD Converter
07 December 2020 23:34

Decimal B4 B3 B2 B1 A B C D E
0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 0 1
2 0 0 1 0 0 0 0 1 0
3 0 0 1 1 0 0 0 1 1
4 0 1 0 0 0 0 1 0 0
5 0 1 0 1 0 0 1 0 1
6 0 1 1 0 0 0 1 1 0
7 0 1 1 1 0 0 1 1 1
8 1 0 0 0 0 1 0 0 0
9 1 0 0 1 0 1 0 0 1
10 1 0 1 0 1 0 0 0 0
11 1 0 1 1 1 0 0 0 1
12 1 1 0 0 1 0 0 1 0
13 1 1 0 1 1 0 0 1 1
14 1 1 1 0 1 0 1 0 0
15 1 1 1 1 1 0 1 0 1

B3,B2, B1 and B0 are inputs and A,B,C,D and E are outputs.

Boolean Algebra Page 49

BCD to XS-3 converter
08 December 2020 00:00

decimal B4 B3 B2 B1 X4 X3 X2 X1
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0

B4, B3, B2 and B1 are BCD inputs and X4,X3,X2 and X1 Excess-3 Outputs

Boolean Algebra Page 50

Encoder
Tuesday, December 8, 2020 1:30 PM

An encoder is a device whose inputs are decimal digits and / or alphabetic characters and
whose outputs are coded representation of these inputs.
Binary to Octal Encoder
Octal Digits Binary
A2 A1 A0
D0 0 0 0 0
D1 1 0 0 1
D2 2 0 1 0
D3 3 0 1 1
D4 4 1 0 0
D5 5 1 0 1
D6 6 1 1 0
D7 7 1 1 1

Boolean Algebra Page 51

4 to 2 encoder
Tuesday, December 8, 2020 1:46 PM

Boolean Algebra Page 52

4 to 2 priority Encoder
Tuesday, December 8, 2020 1:53 PM

Inputs Outputs
D3 D2 D1 D0 A B V
0 0 0 0 x x 0
0 0 0 1 0 0 1
0 0 1 x 0 1 1
0 1 x x 1 0 1
1 x x x 1 1 1

Boolean Algebra Page 53

Combinational Circuits
31 October 2020 20:16

Design of BCD-to-Seven Segment Decoder

Conbinational Circuits Page 54

Seven Segment Decoder
13 December 2020 19:23

BCD Inputs Seven Segment Outputs

A B C D a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1

Conbinational Circuits Page 55

Seven Segment
Decoder
13 December 2020 20:01

Conbinational Circuits Page 56

Even Parity Bit Generator
13 December 2020 20:14

Even Parity Checker

Conbinational Circuits Page 57

Make 9 Bit odd parity Checker Using a 74180 and an
inverter.
13 December 2020 22:30

 Odd Odd

Even I=0 0
Odd I=0 1
Even I=1 1 x=m1+m2
Odd I=1 0 x=( m1'.m4')' = m1+m4

m1 = a'b'c'd'
m1' = a+b+c+d
m4' = a+b'+c+d

Conbinational Circuits Page 58

Comparators
13 December 2020 22:58

A comparator is a logic circuit used to compare the magnitudes of two

binary numbers.
Depending on design it may provide an output that is active (goes HIGH
for example ) when two numbers are equal, or provide outputs that
signify which of the numbers is greater when equality does not hold.
X-NOR gate is basic comparator.
Two binary numbers are equal, if and only if all their corresponding bits
coincide. Equation of 4 bit equality comparator.

Conbinational Circuits Page 59

2-Bit Magnitude Comparator
13 December 2020 23:27

Let two numbers A = A1A0 and B=B1B0

If A1 = 1 and B1 = 0, then A>B or If A1 = B1 and A0 = 1 and B0 = 0, then A>B
A>B:G =

Similarly 4-Bit Magnitude comparator can also be designed.

Conbinational Circuits Page 60

IC Comparator 7485
14 December 2020 00:01

Cascading of two 7485 to design 8 bit comparator.

Conbinational Circuits Page 61

Design 5 bit Comparator Using 7485
14 December 2020 00:19

Conbinational Circuits Page 62

ODD Parity Generator and Checker.
14 December 2020 13:02

Microsoft account at 12/16/2020 4:31 PM

Conbinational Circuits Page 63

Conbinational Circuits Page 64
4 to 16 Decoder using Two 3-8 decoders
Thursday, December 17, 2020 1:35 PM

Conbinational Circuits Page 65

Flip Flop
Monday, December 21, 2020 5:15 PM

Conbinational Circuits Page 66

Flip Flop NAND GATE
Monday, December 21, 2020 5:40 PM

Conbinational Circuits Page 67

Positive Edge Triggered Flip-Flop
Wednesday, December 23, 2020 1:23 PM

Conbinational Circuits Page 68

Falling edge
Wednesday, December 23, 2020 1:35 PM

Conbinational Circuits Page 69

Conbinational Circuits Page 70
Level and Pulse
Thursday, December 24, 2020 12:25 PM

Conbinational Circuits Page 71

S -R FF explained
Thursday, December 24, 2020 1:05 PM

Conbinational Circuits Page 72

Conversion of S-R Flip-Flop to JK Flip-Flop
27 December 2020 19:36

External Present Next Flip-flop

Inputs State State Inputs
J K Qn Qn+1 S R
0 0 0 0 0 x
0 0 1 1 x 0
0 1 0 0 0 x
0 1 1 0 0 1
1 0 0 1 1 0 K-Map for S
1 0 1 1 x 0
1 1 0 1 1 0
1 1 1 0 0 1
Conversion Table

K-Map for R

Logic Diagram for J-K Flip-flop

Conversion of Flip-Flips Page 73

Conversion S-R Flip-flop to D flip-flop
27 December 2020 19:52

External Present Next Flip-flop

Inputs State State Inputs
D Qn Qn+1 S R
0 0 0 0 x
0 1 0 0 1
1 0 1 1 0 K-Map for S
1 1 1 x 0
Conversion Table

K-Map for R

Conversion of Flip-Flips Page 74

Conversion J-K Flip-flop to S-R flip-flop
27 December 2020 20:20

External Present Next Flip-flop

Inputs State State Inputs
S R Qn Qn+1 J K
0 0 0 0 0 x
0 0 1 1 x 0
0 1 0 0 0 x
0 1 1 0 0 1
1 0 0 1 1 0
1 0 1 1 x 0
1 1 0 x x x
1 1 1 x x x
Conversion Table
K-Map for R

Logic Diagram

Conversion of Flip-Flips Page 75

D flip-flop to S-R flip-flop
27 December 2020 20:39

External Present Next Flip-flop

Inputs State State Inputs
S R Qn Qn+1 D
0 0 0 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 0 0
1 0 0 1 1
1 0 1 1 1 K-Map for D
1 1 0 x x
1 1 1 x x
Conversion Table

Logic Diagram

Conversion of Flip-Flips Page 76

J-K to T flip-flop
27 December 2020 21:24

External Present Next Flip-flop

Inputs State State Inputs
T Qn Qn+1 J K
0 0 0 0 x
0 1 1 x 0
1 0 1 1 x
1 1 0 x 1
Conversion Table
K-Maps for J and K

Conversion of Flip-Flips Page 77

J-K flip-flop to D-flip-flop
27 December 2020 21:34

External Present Next Flip-flop

Inputs State State Inputs
D Qn Qn+1 J K
0 0 0 0 x
0 1 0 x 1 K-Maps J and K
1 0 1 1 x
1 1 1 x 0
Conversion Table

Logic Diagram

Conversion of Flip-Flips Page 78

D-flip-flop to J-K flip-flop
27 December 2020 21:40

External Present Next Flip-flop

Inputs State State Inputs
J K Qn Qn+1 D
0 0 0 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 0 0
1 0 0 1 1
K-Map for D
1 0 1 1 1
1 1 0 1 1
1 1 1 0 0
Conversion Table

Logic Diagram

Conversion of Flip-Flips Page 79

JK F/F
Monday, December 28, 2020 12:22 PM

Conversion of Flip-Flips Page 80

D-Flip/Flop
Monday, December 28, 2020 12:40 PM

Conversion of Flip-Flips Page 81

RC Circuit
Monday, December 28, 2020 1:14 PM

Conversion of Flip-Flips Page 82

Monday, December 28, 2020 1:17 PM

Conversion of Flip-Flips Page 83

Toggling of Level Triggered JK Flip-flop
Monday, December 28, 2020 1:54 PM

Clock started at t=0 , Clk =1 at t=0 to

t=tp
J=K=1, tp >>  ,  time delay of one gate.

Complement of Q' in Xn+1 = ( [Link].Q'n)'

n Time X Y Q Q'
previous row. Xn+1 = ( Q'n)'
t<0 1 1 0 1
0 t=0 1 1 0 1 Complement of Q in Yn+1 = ([Link])'
1 t= 0 1 0 1 previous row. Yn+1 = ( Qn)'
2 t=2 0 1 1 1
3 t=3 0 0 1 0 Qn+1 = ([Link]')'
Q'n+1 = (YnQn )'
4 t=4 1 0 1 1
5 t=5 0 0 0 1
6 t=6 0 1 1 1
7 t=7 0 0 1 0
8 t=8 1 0 1 1
9 t=9 0 0 0 1

Level trigged JK Flip-flop

01,01,11,10,11,01,11,10,11,01
If , tp >>  , then value of Q and Q' is not predictable.
Hence this is not desirable. So solution is to have edge triggered flip-flop.
Master- Slave Flip-flop.

Conversion of Flip-Flips Page 84

S-R Flip-Flop
Tuesday, December 29, 2020 12:24 PM

Conversion of Flip-Flips Page 85

T-Flip-flop
Tuesday, December 29, 2020 12:36 PM

Conversion of Flip-Flips Page 86

Master -Slave JK Flip-Flop
Wednesday, December 30, 2020 1:03 PM

J=K=1, CLK =1, Q and QM=1, Q' and (QM)' =0. t=0 (PRE)' = (CLR)' = 1.

Assume that  is delay of one gate.

Inputs of G1 at t=0 , J=CLK=1 and Q' =0 so G1 output at t= is 1
Inputs of G2 at t=0 , J=CLK=1 and Q =1 so G2 output at t= is 0
Inputs G3 at t = are Output of G1 =1 and (QM)' = 0 so G3 output at t=2 is
1
Inputs G4 at t = are Output of G2 =0 and (QM) = 1 so G4 output at t=2 is
1
Inputs of G1 at t= , J=CLK=1 and Q' =0 so G1 output at t=2 is 1
Inputs of G2 at t= , J=CLK=1 and Q =1 so G2 output at t=2 is 0
Inputs G3 at t =2 are Output of G1 =1 and (QM)' = 1 so G3 output at t=3 is
0
Inputs G4 at t =2 are Output of G2 =0 and (QM) = 1 so G4 output at t=3 is
1
10,11,01,01,01
Inputs of G1 at t=2 , J=CLK=1 and Q' =0 so G1 output at t=2 is 1

Conversion of Flip-Flips Page 87

Inputs of G1 at t=2 , J=CLK=1 and Q' =0 so G1 output at t=2 is 1
Inputs of G2 at t=2 , J=CLK=1 and Q =1 so G2 output at t=2 is 0
Inputs G3 at t =3 are Output of G1 =1 and (QM)' = 1 so G3 output at t=4 is
0
Inputs G4 at t =3 are Output of G2 =0 and (QM) = 0 so G4 output at t=4
is 1

When Clock becomes negative (zero) Q=QM, and Q' = (QM)' after appropriate
delay.

Conversion of Flip-Flips Page 88

Wednesday, December 30, 2020 2:02 PM

Conversion of Flip-Flips Page 89

Counters
Thursday, December 31, 2020 1:50 PM

MOD-10 Counter

Count Q4 Q3 Q2 Q1 R

Conversion of Flip-Flips Page 90

Count Q4 Q3 Q2 Q1 R
0 0 0 0 0 0
1 0 0 0 1 0
2 0 0 1 0 0
3 0 0 1 1 0
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 0
8 1 0 0 0 0
9 1 0 0 1 0
10 1 0 1 0 1
11 1 0 1 1 x
12 1 1 0 0 x
13 1 1 0 1 x
14 1 1 1 0 x
15 1 1 1 1 x

0,1,2,3,4,5,6,7,8,9,0,1,
10,0,1,2,…
11,0,1,2,…
12,13,14,0…
13,14,0,1,…
14,0,1,2,..
15,0,1,2,3

Count Q4 Q3 Q2 Q1 R
0 0 0 0 0 0
1 0 0 0 1 0
2 0 0 1 0 0
3 0 0 1 1 0
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 0
8 1 0 0 0 0
9 1 0 0 1 0
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1

Conversion of Flip-Flips Page 91

13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1

Mod-9 Counter

Conversion of Flip-Flips Page 92

Synchronous Counters 3 Bit Up Counter
17 January 2021 13:19

PS NS Required Excitations
PS NS J K
Q3 Q2 Q1 Q3 Q2 Q1 J3 K3 J2 K2 J1 K1
0 0 0 x
0 0 0 0 0 1 0 x 0 x 1 x
0 1 1 x
0 0 1 0 1 0 0 x 1 x x 1
1 0 x 1
0 1 0 0 1 1 0 x x 0 1 x
1 1 x 0
0 1 1 1 0 0 1 x x 1 x 1
1 0 0 1 0 1 x 0 0 x 1 x
1 0 1 1 1 0 x 0 1 x x 1
1 1 0 1 1 1 x 0 x 0 1 x
1 1 1 0 0 0 x 1 x 1 x 1

J1=K1= 1

New Section 1 Page 93

New Section 1 Page 94
+Synchronous 3 Bit Down Counter
17 January 2021 14:06

PS NS Required Excitations
Q3 Q2 Q1 Q3 Q2 Q1 J3 K3 J2 K2 J1 K1
0 0 0 1 1 1 1 x 1 x 1 x
1 1 1 1 1 0 x 0 x 0 x 1
1 1 0 1 0 1 x 0 x 1 1 x
1 0 1 1 0 0 x 0 0 x x 1
1 0 0 0 1 1 x 1 1 x 1 x
0 1 1 0 1 0 0 x x 0 x 1
0 1 0 0 0 1 0 x x 1 1 x
0 0 1 0 0 0 0 x 0 x x 1

J1=K1=1

New Section 1 Page 95

 3-bit Synchronous Down Counter

New Section 1 Page 96

Synchronous Mod-6 Gray Code Counter Using T-Flip-
flops
17 January 2021 19:34

PS NS Required Excitations
Q3 Q2 Q1 Q3 Q2 Q1 T3 T2 T1
0 0 0 0 0 1 0 0 1
0 0 1 0 1 1 0 1 0
0 1 1 0 1 0 0 0 1
0 1 0 1 1 0 1 0 0
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1

Synchronous Mod-6 Gray Code Counter

101 T1=1, T2= 1, T1=1, NS 010 Valid state

100 T1=1 T2= 0 T1=0 NS 000 Valid State
Self-Starting counter

New Section 1 Page 97

 Self-Starting counter

New Section 1 Page 98

Mod 3 Counter Using JK Flip-flop
17 January 2021 20:09

PS NS
Q2 Q1 Q2 Q1 J2 K2 J1 K1
0 0 0 1 0 x 1 x
0 1 1 0 1 x x 1
1 0 0 0 x 1 0 x
1 1 x x x x x x

Mod-3 Synchronous Counter

Invalid state 11
J1=Q2' = 0, K1=1, So Next Q1 =0
J2 = Q1=1 , K2 =1 So Next Q2 =0
So Next State 00 a valid State.

New Section 1 Page 99

Mod-4 Synchronous Counter with States 0,3,5,6 Using T -
Flip-flops
17 January 2021 20:29

PS NS Required Excitations
Q3 Q2 Q1 Q3 Q2 Q1 T3 T2 T1
0 0 0 0 1 1 0 1 1
0 1 1 1 0 1 1 1 0
1 0 1 1 1 0 0 1 1
1 1 0 0 0 0 1 1 0

(1,2,4,7 are do not care)

Mod -4 Synchronous Counters having States 0,3,5,6,0

Suppose Counter enters an invalid state at power on
say 001,(1 Invalid State)
T3 = Q2=0, T2=1, T1= Q2'=1
So next state
0 1 0 (2 again invalid State)
T3=Q2=1, T2=1 T1=Q2'=0
So Next State
1 0 0 ( 4 Again Invalid State)
T3= Q2= 0 T2 =1 T1=Q2'=1
So Next State
1 1 1 ( 7 Again Invalid State)
T3=Q2 = 1 T2= 1 T1=Q2' =0
So next State
0 0 1 ( 1 Invalid State First one)
It means That if counter enters into an invalid state
counter will not come out of it. So counter is not self-
starting. Lock out state.
1. Reset the counter if counter enters to any of these
states.
2. Modify the table such instead of do not care the
counter should go to state 000.

New Section 1 Page 100

 counter should go to state 000.

Q3 Q2 Q1 R
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

New Section 1 Page 101

Self-Starting of Counters
Monday, January 18, 2021 12:53 PM

PS NS Required Excitations
Q3 Q2 Q1 Q3 Q2 Q1 T3 T2 T1
0 0 0 0 1 1 0 1 1
0 0 1 0 0 0 0 0 1
0 1 0 0 0 0 0 1 0
0 1 1 1 0 1 1 1 0
1 0 0 0 0 0 1 0 0
1 0 1 1 1 0 0 1 1
1 1 0 0 0 0 1 1 0
1 1 1 0 0 0 1 1 1

New Section 1 Page 102

D/A Converter
17 January 2021 23:16

New Section 2 Page 103

 If Dn is input 1 and all other inputs are 0 and total number of bits = N.
D0 is LSB and DN-1 is MSB. Vout = E/(2N-n)

Determine the value of Vout for 8 bit DAC E=10V, Input 10001000

Vout = 10/(28-7 )+ 10/(28-3 ) = 10/2 + 10/32 = 5.3125 V

Full Scale Voltage = 255*(10/256) = 9.9609 is less than the input voltage.
If gain 1.

The Weighted Resistor Type DAC

Determine full scale output Input =5V, Rf = R = 1K

Vout = -5*(1+1/2+1/4+1/8) = -9.375 (Full Scale)

If Rf = 500  and R=1 K

Vout = -(5/2)*(1+1/2+1/4+1/8) = -4.6875 (Full Scale)

New Section 2 Page 104

 Timer
18 January 2021 22:51

The typical pinout of the 555 is as follows:

• Pin 1. – Ground, The ground pin connects the 555
timer to the ground reference voltage (0 volts).
• Pin 2. – Trigger, The inverting input of the trigger
comparator. A negative pulse on this pin “sets” the
internal Flip-flop when the voltage drops below 1/3Vcc
causing the output to switch from a “LOW” to a “HIGH”
state.
• Pin 3. – Output, The output pin can drive any TTL
circuit and is capable of sourcing or sinking up to
200mA. The output uses a push-pull architecture and
can drive from 0V to approximately Vcc – 1.7V. (Note:
CMOS timer parts can drive output up to VCC rail.)
• Pin 4. – Reset, This pin is used to “reset” the internal
Flip-flop controlling the state of the output, pin 3. This
is an active-low input and is generally connected to a
logic “1” level when not used to prevent any unwanted
resetting of the output.
• Pin 5. Control Voltage. This pin controls the timing of
the 555 by overriding the 2/3Vcc level of the voltage
divider network. By applying a voltage to this pin the
width of the output signal can be varied independently
of the RC timing network. In most applications, this pin
is not used, thus it is recommended to connect a low-
noise 10 nF decoupling capacitor (film or ceramic)
between Control pin and Ground pin to filter noise.
The control pin input can be used to build an astable
multivibrator with a frequency-modulated output.
• Pin 6. Threshold. The non inverting input (positive
input) of the threshold comparator. This pin is used to
reset the Flip-flop when the voltage applied to it
exceeds 2/3Vcc causing the output to switch from
“High” to “Low”.
• Pin 7. Discharge. The discharge pin is connected
directly to the Collector of an internal NPN transistor
which may be used to “discharge” a capacitor between
intervals. The transistor acts as a switch which is in
phase with output.

New Section 3 Page 105

 phase with output.
• Pin 8. Positive supply (+Vcc). The guaranteed voltage
range of bipolar parts are typically 4.5 volt to 15 volts
(some parts rated up to 16 volts or 18 volts), though
most bipolar parts will operate at voltages as low as 3
volts. (Note: CMOS timer parts have a lower minimum
voltage rating.) It is recommended that a 100 nF
decoupling capacitor be connected as close as possible
to this pin, and optionally a 10 to 100uF reservoir
capacitor depending on the size of the load on the
output pin.
From <[Link]

An astable timer operation is achieved by configuring

as shown on Figure 2. In the astable operation, the
trigger terminal and the threshold terminal are
connected so that a self-trigger is formed, operating as
a multivibrator. When the timer output is high, its
internal discharging Transistor (T1) turns off and the C1
is charged from Vcc.
During charging, the voltage across the external
capacitor C1, VC1, increases exponentially with the
time constant (RA+RB)×C1. That is because C1 is
charged from the current flowing through RA and RB.

New Section 3 Page 106

charged from the current flowing through RA and RB.
When the VC1, or the threshold voltage, reaches
2Vcc/3, the threshold comparator’s output becomes
high, resetting the F/F and causing the timer output to
become low. This in turn turns on the discharging
Transistor and the C1 discharges through the
discharging channel formed by RB and the discharging
Transistor.
>

Monostable operation
>

The external timing capacitor C1 is held initially

discharged by the transistor T1 inside the timer. Upon
application of a negative pulse to pin 2, the flip-flop is
set which releases the short circuit across the external
capacitor and drives the output high. The voltage
across the capacitor, now, rises exponentially with the
time constant RT×C1. When the voltage across the
capacitor equals 2Vcc/3, the threshold comparator
resets the flip-flop which, in turn, discharges the
capacitor rapidly and drives the output to its low state.
The circuit rests in this state till the arrival of next
pulse.
The larger the time constant RT×C1, the longer it takes
for the capacitor voltage to reach 2Vcc/3. In other
words, the RC time constant controls the width of the
output pulse.
The circuit triggers on a negative going input signal
when the level reaches Vcc/3. Once triggered the
circuit will remain in this state until the set time is
elapsed, even if it is triggered again during this interval.

New Section 3 Page 107

>

Bistable operation

The 555 timer can also function as a bistable flip-flop. This

flip-flop offers the advantage that it operates from many
different supply voltages, uses low power and requires no
external components other than bypass capacitors in noisy
environments. It also provides a high current output which
can sink or source as much as 200mA.
A basic bitable circuit which uses the 555 is shown in figure
8:

>

As shown in figure 8, a negative pulse applied to the

trigger input terminal (pin 2) sets the flip-flop and the
output goes high. A positive going pulse to the
threshold terminal (pin 6) will reset the flip-flop and
will drive the output low.
Besides the basic bistable circuit of figure 8, there is
also another configuration where the two comparator
inputs (pin 2 and pin 6) are tied together and biased at
VE through a voltage divider R1 and R2. This
arrangement is shown in figure 9. It is also a bistable
circuit but it moreover, it is a Schmitt trigger.

New Section 3 Page 108

Since the threshold comparator will trip at 2Vcc/3 and
the trigger comparator will trip at Vcc/3, the bias
provided by the resistors R1 and R2 should be within
the comparator’s trip limits. For instance, we may use
identical R1 and R2 to make VE equal to Vcc/2. Any
signal of sufficient amplitude to exceed the reference
levels is applied on the input of the Schmitt trigger, will
cause the internal flip-flop to be set or reset. In this
way, any input signal will create a square wave at the
output and the circuit can be used as a signal
shaper/buffer with the advantage of the availability of
a high output current.

Monostable NOR gates and inverter

Monostable using NAND gates

New Section 3 Page 109

 Normally Q=1, T=1, A=0 , B=0 Hence Q=1 Stable
If T=0 for a short Pulse, Makes A=1 so B=1 and Hence Q=0
A remains 1 even if T becomes 1.
C start charging So after some ( Depends upon RC) B=0 and So Q=1
Astable Multivibrator Using Inverters

Timing diagram

New Section 3 Page 110

MonoSta

New Section 3 Page 111