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Computer Organization Assignment 2025-26

The document outlines the assignment structure for the Computer Organization and Architecture course for the B.E / CSE program for the academic year 2025-26. It details the written assignments, case studies, seminars, and multiple-choice questions across various units, specifying marks distribution and topics to be covered. Additionally, it includes learning outcomes related to transaction processing, data integration, and data flow transformations.
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0% found this document useful (0 votes)
12 views4 pages

Computer Organization Assignment 2025-26

The document outlines the assignment structure for the Computer Organization and Architecture course for the B.E / CSE program for the academic year 2025-26. It details the written assignments, case studies, seminars, and multiple-choice questions across various units, specifying marks distribution and topics to be covered. Additionally, it includes learning outcomes related to transaction processing, data integration, and data flow transformations.
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Department of Computer Science and Engineering

Assignment –I
Academic Year &
Degree / Program B.E / CSE 2025-26 & ODD
Semester

Course Code 24CST38&


Computer Organization And Year / Sem.
&Course Name
Architecture
Name of the
Faculty& Regulation 2020
Department
Email Contact No

Written assignment/case study/ MCQ ( 24 Marks )


Assignment -1 Seminar ( 16 marks ) (One marks each Question )
( 40 Marks ) Unit 1 Unit 2 Unit 1 Unit 2 Unit 3
8 8 8 8 8
Written assignment/case study/ MCQ ( 16 Marks )
Assignment -2 Seminar ( 24 marks ) (One marks each Question )
( 40 Marks ) Unit 3 Unit 4 Unit 5 Unit 4 Unit 5
8 8 8 8 8

UNIT - I (COMPUTER ORGANIZATION AND


[Link] Marks BL SL
ARCHITECTURE)
WRITTEN ASSIGNMENT QUESTIONS
1. Explain the following: i)Byte addressability, ii) Big-endian
assignment, iii) Little-endian assignment. 8 K3 A2,A3

2. What is the role of Processor clock, clock rate in the


performance of computer system? Explain. 8 K3 A4,A5

3. Explain The Basic Operational Concepts


8 K3 B3,B4,B5

4. What are addressing modes? Explain the various addressing


modes with examples. 8 K3 B6 ,B7,B8

5. What are the functional units of a computer system? Explain 8 K2 C1,C2,C3


the way of handling information by each of them.
Case study /Seminar / Real time Examples / mini Project (PPT)
6. Case Study for A category students
Case Study: The role of Processor clock, clock rate in the
performance of computer system and The most important 8 K4 A1
measure of the performance of a computer is how quickly it can
compute programs.

7. Seminar for B category students


Seminar on the functional units of a computer system the way 8 K3 B1,B2
of handling information by each of them.

UNIT - II (DATA INTEGRATION )


WRITTEN ASSIGNMENT QUESTIONS
1. 8 K3 A1,A3
2. 8 K3 A4,A5
3. 8 K3 B1,B2,B5
4. 8 K3 B6, B7,B8
5. 8 K2 C1,C2,C3
Case Studies/Seminar / Mini project
6. 8 K4 A2
7. 8 K3 B3,B4

MCQ QUESTIONS
[Link] Unit – I CO Marks BL
1. In a typical CPU, which functional unit handles instruction decoding
and control signal generation?
a) Arithmetic Logic Unit (ALU)
b) Control Unit CO1 1 K3
c) Register File
d) Memory Management Unit (MMU)

2. Which statement is true about the basic operational concept of a


pipeline?
a) It decreases instruction latency for a single instruction.
b) It increases throughput by overlapping stages of multiple 1 K3
CO1
instructions.
c) It reduces the need for control signals.
d) It avoids data hazards automatically.

3. Fixed point representation is best suited for CO1 1 K3


a)Scientific calculations requiring large dynamic range
b) Financial calculations with known decimal places
c) Graphics rendering with high precision
d) Floating point division
4. Which of the following is true about RISC processors
a) They have complex instructions.
b) They use variable length instructions. 1 K3
CO1
c) They emphasize simple instructions and pipelining.
d) They have larger instruction sets than CISC

5. In indexed addressing mode, the effective address is calculated as


a) Base address minus offset
b) Operand plus accumulator
CO1 1 K3
c) Base address plus index register content
d) Program counter plus operand

6. Which operation is NOT part of the instruction cycle?


a) Fetch
b) Decode 1 K3
CO1
c) Print
d) Execute

7. he Instruction Set Architecture (ISA) is crucial for CPU design.


It defines the instructions that a processor can execute.
a) True
b) False CO1 1 K3
c) Only for RISC
d) Only for CISC

8. Which addressing mode is best for accessing array elements in


loops?It uses a base address plus an index offset
a) Direct
b) Register CO1 1 K3
c) Immediate
d) Indexed

Unit – II
9. CO2 1 K3
10. 1 K3
CO2
11. CO2 1 K3
12. CO2 1 K3
13. CO2 1 K3
14. CO2 1 K3
15.
CO2 1 K3
16. CO2 1 K3

Unit – III
17.
CO3 1 K3
18.
CO3 1 K3
19. CO3 1 K3
20.
CO3 1 K3
21.
CO3 1 K3
22.
CO3 1 K3
23.
CO3 1 K3
24. CO3 1 K3

CO1 Recall about transaction processing and analytical applications and describe the need for
business intelligence.
CO2 Identify the technology and processes associated with data integration.
CO3 Infer about data flow and transformations i.e., ETL using SSIS.

Course Instructor Module Coordinator Program Coordinator

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