Module 4: CMOS Circuits and Logic Design.
1. Draw the schematic diagram of the Boolean function Y= ((A + B)C + DE)’
using pseudo NMOS logic and explain its operation. Also discuss the
advantages and disadvantages of this logic.
2. Describe the operation of C2MOS logic.
3. Draw the schematic diagram of a 4:1 multiplexer using NMOS and CMOS
implementation of pass transistor logic.
4. Draw the schematic structure and the graphical representation of the
function Y= ((A + B) + CD)’ using CMOS logic. Also, draw the layout for
the same using the Euler path method.
5. Draw C2MOS logic circuit for the Boolean function Z=(XY+W)’
6. Differentiate between two-phase dynamic logic and four-phase dynamic
logic.
7. Describe the operation of CVS Logic. Also implement CVS logic for
Z=(A.B + C.D)’
8. Draw the schematic diagram of the Boolean function W= (XY+P(Q+R))’
using Dynamic CMOS logic and explain its operation. Also discuss the
cascaded issue in Dynamic CMOS logic.
9. Illustrate the operation of Clocked NAND-based JK Latch circuit with a gate
level schematic and All NAND implementation.
[Link] the schematic diagram of a 2:1 multiplexer using NMOS and CMOS
implementation of pass transistor logic.
[Link] body effect in a multiple input gate.
[Link] a short note on Input /output structures, Input pads and Tri-state pads.
[Link] the schematic to symbolic layout conversion for Inverter
Module 5: Sequential MOS Logic Circuits
1. Describe the behavior of a two-inverter basic bi-stable element.
2. Explain the operation of a NOR-based SR latch circuit and define the related
lumped load capacitances at the output node.
3. Explain the operation of a NAND-based SR latch circuit with the truth table
and gate level schematics
4. Illustrate the operation of Clocked NAND-based JK Latch circuit with a gate
level schematic and All NAND implementation.
5. Illustrate the operation of Clocked NOR-based JK Latch circuit
6. Explain Depletion-load nMOS SR latch circuit based on NOR2 gates
7. Illustrate clocked SR latch.
8. Explain a typical design flow of a contemporary design system.
9. Describe an ideal approach to design.
10. Explain any four techniques used for reducing the complexity of IC
design in structured design strategies.
11. Briefly explain Gate array design flow.
12. Write a short note on a) Fault Model b) Ad hoc testing
13. Briefly illustrate Level Sensitive Scan Design with a neat circuit
diagram.
14. Write a short note on the following topics related to automated
synthesis:
i) Procedural module definition
ii) Silicon compiler
iii)Structured design for testability
iv) Self-test and built-in testing