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VLSI Circuit Resistance and Capacitance Analysis

The document discusses the estimation of resistance and capacitance in circuit characterization for VLSI design. It details the formulas for calculating resistance based on resistivity, thickness, length, and width, as well as the total load capacitance of a CMOS gate which includes gate, diffusion, and routing capacitances. Additionally, it provides specific equations for calculating gate and diffusion capacitance, along with routing capacitance components.

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Leelavathi Leelavathi
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11 views7 pages

VLSI Circuit Resistance and Capacitance Analysis

The document discusses the estimation of resistance and capacitance in circuit characterization for VLSI design. It details the formulas for calculating resistance based on resistivity, thickness, length, and width, as well as the total load capacitance of a CMOS gate which includes gate, diffusion, and routing capacitances. Additionally, it provides specific equations for calculating gate and diffusion capacitance, along with routing capacitance components.

Uploaded by

Leelavathi Leelavathi
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Circuit Characterization and

Performance Estimation
Resistance Estimation
• Resistance
R (ρ / t)(L /W ), where ( ρ ,t, L,W ) is (resistivity,
thickness, conductor length, conductor width)
 Sheet resistance Rs /
 R R s (L /W ) W W
1 rectangular block t
R R s (L /W )
W L
t

L L
4 rectangular block
R R s (2L / 2W ) R s (L /W )

National Central University EE613 VLSI Design 2


Capacitor
• Load Capacitance ( total amount of electric charge that the output of a CMOS gate needs to charge or discharge when it changes
from 0 to 1 or 1 to 0) on the output of a CMOS gate is the sum of
  Gate capacitance
Diffusion capacitance
 Routing capacitance

• Capacitance can be calculated by


• C= ε0ε x A
tox

 ε x : dielectric constant
 ε 0 : permitivity of free space
National Central University EE613 VLSI Design 3
Gate Capacitor
gate

Cgs Cgb Cgd


source drain

Csb depletion layer Cdb


substrate

Cg=Cgb+Cgs+Cgd

National Central University EE613 VLSI Design 4


Gate Capacitor

National Central University EE613 VLSI Design 5


Diffusion Capacitor
b
Source Drain
a Diffusion Diffusion
Area Area

Cd  C ja (ab) C jp (2a 2b)


Cja=junction capacitance per micron square
Cjp=periphery capacitance per micron

National Central University EE613 VLSI Design 6


Routing Capacitor

•C_total = C_area + C_fringe


•C_area = (ε * A) / d
•C_fringe = k * L: (or a more complex formula depending on the specific geometry)

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