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This document contains a series of interview questions and answers related to SystemVerilog and Object-Oriented Programming (OOP) concepts. Key topics include OOP principles like inheritance and polymorphism, SystemVerilog features such as mailboxes, randomization of variables, and the use of timeunit and timescale directives. The document provides code examples to illustrate various concepts, making it a useful resource for understanding SystemVerilog programming.

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19 views24 pages

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This document contains a series of interview questions and answers related to SystemVerilog and Object-Oriented Programming (OOP) concepts. Key topics include OOP principles like inheritance and polymorphism, SystemVerilog features such as mailboxes, randomization of variables, and the use of timeunit and timescale directives. The document provides code examples to illustrate various concepts, making it a useful resource for understanding SystemVerilog programming.

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gajularohith2005
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© All Rights Reserved
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bee =| = SYSTEM = =VERILOG_ = INTERVIEW = = QUESTIONS __ TTTTTTttT PART Nagaraju NIT Jaipur ECE' 2026 1. What is OOPS? 00P5 stands for Object-Oriented Programming System. It is a programming paradigm that focuses on organizing code into objects, which are instances of classes, OOPS emphasizes concepts such as encapsulation, inheritance, and polymorphism to structure and design software systems. For more detailed explanation refer this post - LINK 2. What is inheritance? SYSTEMVERILOG INHERITANCE ‘Inheritance is a concept in object-oriented programming (OOP) that allows us to extend a class to create another class and have access to all the properties and methods of the original parent class from the handle of the child class object. Aderived class may add new properties and methods or modify the inherited properties and methods. Inheritance promotes reusability, as the derived class includes the properties and methods of the parent class, ready to use. ‘Ifa class's derived from a derived class, its referred to as multilevel inheritance. PARENT CLASS: 1) Its an existing class. 2) Itis the class whose features are inherited. 3) The parent class is also known as a base class or superclass. CHILD CLASS: 2) It's an extended class. 2) Itis the class that inherits the other class. 3). The child class is also known as an extended class, derived class, or subclass, Example: // Parent class definition class parent_class; bit [21:0] addr; // Property to store address endelass // Child class extending the parent class class child_class extends parent_class; bit [2170] data; // Additional property to store data endclass // Module to demonstrate inheritance module inheritance; initial begin child class c= new(); // Creating an object of child clase [Link] = 10; // Accessing and assigning value to the inherited property © semved wth Ot Scanner [Link] = 20; // Assigning value to the property in the child class Sdisplay (" r F I", [Link], [Link]); // Displaying the values end ‘endnodule 3. Howto write a message to a string in SystemVerilog? module MessageBxample; initial begin string message; int value = 42; string name = * // Write a message to the string message = $sformatf(" + value, name) ; // Display the message Sdisplay ("" ) message): ond ‘endnodule 4, Signals inside the interface should be wires or logic? Signals inside the interface in SystemVerilog can be declared as either wire or logic data types. > InsystemVerilog, the most preferred data type for signals inside an interface is logic The logic data type Is modern and versatile, providing better support for modeling constructs like procedural assignments, arithmetic operations, and bit-level manipulations. It is recommended for new designs and when utilizing advanced SystemVerilog features such as assertions, coverage, and functional coverage. However, the wire data type is stil commonly used, particularly for backward compatibility with older Verilog designs and when interfacing with external modules or IP blocks. The choice between wire and logic depends on specific design requirements and project/organization guidelines. ‘Always refer to design specifications and guidelines to select the appropriate data type for interface signals. ef FF & © semved wth Ot Scanner 5. Give examples of a static cast and a dynamic cast. Static Casting: Static casting is a concept in SystemVerilog that allows the conversion of one data type to another compatible data type. Itis a compile-time operation, where the data type is fixed during compilation. static casting is used to explicitly change the type of a value, variable, or expression. Example of Static Casting: In the following example, we demonstrate static casting by converting a real type into an int type. We ‘multiply two real numbers, which results ina real value. Then, we convert the result into an int type using static casting and assign it to a variable of int type. module casting; real za; int ia; initial begin // Real to integer conversion using static casting jas int'(2.1 * 3.2); // or ia = int'(ra); Sdisplay ("Real is 88", rad; Sdisplay ("Int v 1 iade end ‘endnodule Dynamic casting Dynamic casting is a concept in SystemVerilog used to safely cast a handle of a parent class to a handle of a child class in a class hierarchy. It allows runtime checking of the compatibility of objects during casting and can result in a runtime error ifthe casting is not compatible. Dynamic casting is performed using the $cast method, which checks the compatibility of the casting during runtime rather than compile-time, Let's explore how dynamic casting works: > Itis always legal to assign a child class handle to a handle of a parent class higher in the inheritance tree. For example: parent_class = child class; // Allowed © semved wth Ot Scanner > Itisnever legal to directly assign a parent class handle to a handle of one of its child classes. For example: > child_class = parent_class; // Not allowed > However, it is legal to assign a parent class handle to a child class handle if the parent class handle refers to an object of the child class. For example: parent_class p_hr child Glass c hl, c_n2; ph=c hl; coh2 = ph // Allowed because parent_class is pointing to cl > Although assigning a parent class handle to a child class handle is allowed when the parent class handle refers tothe child class, a compilation error is encountered due to incompatible types for the assignment. This can be overcome by using the Scast method. For example: Scast(¢_h2, ph); // Allowed using $cast method Dynamic casting allows for safe casting between related classes in a class hierarchy, providing flexibility in handling class objects and enabling polymorphic behavior. 6 What is Mailbox? ‘A mailbox is 2 communication mechanism that facilitates the exchange of messages between processes in ‘SystemVerilog, It allows data to be sent from one process and retrieved by another process. Here is an example that demonstrates how to declare and create a mailbox: mailbox mbsRcv; mbxRev = new(); In SystemVerilog, there are two methods available for placing a message in a mailbox: put() (blocking): This method blocks the executing process until there is space available in the mailbox to hold the message. Once space becomes available, the message is placed in the mailbox. peek{) (nonblocking): This method attempts to place the message in the mailbox but does not block the executing process. If there is space available, the message is successfully placed; otherwise, it returns without modifying the contents of the mailbox. © semved wth Ot Scanner ‘Similarly, to retrieve a message from a mailbox, there are two methods available: {get() (blocking): This method blocks the executing process until a message is available in the mailbox. Once a message becomes available, itis retrieved from the mailbox, ‘try_geti) (nonblocking): This method attempts to retrieve a message from the mailbox but does not block the executing process. If a message is available, itis successfully retrieved; otherwise, it returns without ‘modifying the contents of the receiving variable. Additionally, the mailbox provides the num() method, which allows you to retrieve the number of ‘messages currently present in the mailbox. ‘The usage of mailboxes and their associated methods enables synchronized and efficient communication between processes in SystemVerilog. It allows for the exchange of data in a controlled manner, ensuring, seamless coordination between different parts of the design. The following example demonstrates the usage of a mailbox for communication between a generator and a driver in a SystemVerilog design. Uf Packet ol packet; rand bit [7:0] addr; rand bit [7:0] data; // Displaying randomized values function void post_randomize(); Sdisplay ("Pack Gener : Sdisplay ( Addr=80d, Data=80d", addr, data); endfunction endolass // Generator ~ Generates the transaction packet and sends it to the driver ou s generator; packet pkt; mailbox m_box; // Constructor, getting mailbox handle function new (mailbox m_box) ; this.m_box = m box; © semved wth Ot Scanner endfunction task run; repeat (2) begin pkt = new); [Link](); // Generating packet m_box.put(pkt); // Putting packet into the mailbox display ("Generator::Packet Put into Mailbox"); 57 // Driver ~ Retrieves the packet from the generator and displays its fields driver; packet pkt; mailbox mbox: // Constructor, getting mailbox handle function new (mailbox m_box) ; this.m_box = m_box; endfunction task run; repeat () begin m_pox.get (pkt); // Retrieving packet from the mailbox $display("oriver:: ea")? Sdisplay d\n", [Link], [Link]) // top-level module module mailbox_ex; generator gen; driver ari; mailbox mbox; // Declaring mailbox m_box initial begin // Creating the mailbox and passing the sane handle to the generator and deiver, // as the same mailbox should be shared for communication. mbox = new(); // Creating mailbox © semned ith nt Seamer gen = new(m_box); // Creating generator and passing mailbox handle dri = new(m_box); // Creating driver and passing mailbox handle Sdisplay( ve fork [Link](); // Process-1 [Link](); // Process-2 jean Sdisplay (" ": end ‘endnodule 7. What will be the values of rand and randc variables if randomization fails? If randomization fails for a rand variable, the value of the variable will depend on its initial value or any value assigned to it before randomization. For example: rand int myRandVar = 5; // Initial value assigned // Randomization process A ([Link]()) begin Sdisplay ("Ran // Value of myRandVar will still be 5 end In this example, if the randomization process for myRandVar fails, the value of myRandVar will remain as 5 since it was explicitly assigned that value before the randomization attempt. On the other hand, for a randc variable, if randomization fails, it wll be assigned an illegal value that cannot be legally represented by its data type. Here's an example: rande logic [3:0] myRandevar; // Randomization process Af ([Link]()) begin Sdisplay ("Randomizat // Value of myRandcVar will be an illegal value f for myRandeVar") : ) In this example, if the randomization process for myRandcVar fails, the variable will be assigned an illegal value that cannot be represented by the logic [3:0] data type. The specificillegal value assigned will depend ‘on the simulation tool and implementation. © semved wth Ot Scanner t's important to handle randomization failures appropriately in your code and check for success/failure Using constructs like the randomize method or the randomize with construct. This allows you to perform error handling, provide fallback mechanisms, or implement alternative strategies when randomization fails. 8. Explain about the timeunit, timeprecision, and timescale in SystemVerilog. The timeunit, timeprecision, and timescale directives in SystemVerilog are used to specify the time resolution and units for simulation. The timeunit directive sets the basic time unit for simulation, It determines the smallest time increment used in the simulation. The default timeunitis Ans. For example: timescale Ins/ins ‘The timeprecision directive determines the number of decimal places used for fractional time values. The default timeprecision is Ins. For example: “timescale Ins/100p= The timescale directive combit 1es both timeunit and timeprecision directives in a the time unit and time precision for the entire compilation unit. Jingle statement. It sets For example: “timescale Ins/ips By specifying the timescale directive at the beginning of a file, you can define the time unit and precision used throughout the design. © semved wth Ot Scanner 9, Howto randomize a real data type variable? In SystemVerilog, to randomize a real data type variable, you can make use of the built-in randomize method provided by the language. The randomize method is used to assign random values to variables based on their data type constraints. To randomize a real variable, you need to follow these steps: 1) Declare a real variable that you want to randomize. 2) Call the randomize method on the real variable to assign a random value. Here's an example code snippet demonstrating how to randomize a real variable in SystemVerilog: class MyClass; real myRealVar; // Declare a real variable function new(); myRealVar = $randem; // Assign a random value to myRealVar using $random system function endfunction function void displayvalue(): Sdisplay ("Rand e sealvar: 8£", myRealvar); // Display the randomized value endgunction endolass module Example: initial begin MyClass obj = new(); // Create an instance of MyClass obj-displayValue(); // Call the displayValue function to print the randomized value end ‘endnodule © semved wth Ot Scanner 10, What is the default value of an enumerated data type? ‘The default value of an enumerated data type is the first value defined in the enumeration list. If no explicit assignment is given, the first enumeration member is assigned a value of 0, and subsequent members are assigned values in the order they are defined, incrementing by 1. For example, consider the following enumeration: typedef enum logic [2:0] (RED, GREEN, BLUE) Color; In this case, the default value of the Color data type would be RED, which has an implicit value of 0. If you explicitly assign values to the enumeration members, the default value remains the same, unless ‘you specifically set it otherwise. 111. What is polymorphism? Polymorphism Polymorphism, which means "many forms," is a concept in SystemiVerilog that allows an object to take on multiple forms. In SystemVerilog, polymorphism enables a variable of the parent class type to hold objects of child classes and access the methods of those child classes directly from the parent class variable. It also allows a child class method to have a different definition than its parent class if the parent class method is declared as virtual. Here are the key points regarding polymorphism in SystemVerilog: 1) A parent class variable can be used to reference objects of child classes. 2). The parent class method should be declared as virtual 3) The method name should be the same in both the parent and child classes. 4) Child class objects can be assigned to a parent class variable using the assignment operator. 5) The child class methods can be accessed using the parent class handle. 12. Give an example of polymorphism. Let's see an example that demonstrates polymorphism in SystemVerilog: // Base class class base_class; virtual function void display); Sdisplay (" 7 ”: ‘endfunction endolass © semved wth Ot Scanner Child class 1 class child_class_1 extends base_clas: function void display()? Sdisplay ("Inside ass 1"); endfunction endclass // child class 2 class child_class_? extends base_class; function void display) Sdieplay ("Inside endfunction endolass module class_polymorphism; initial begin base_class b_h; // veclaxe base child_class_1 cl = new(); // create child child class 2 ¢2 = new(); bheclr // Assign child class handle bhec2 b_b.display (0; // access child using base class handle end ‘endnodule 13. What is meant by abstraction? class class class class handle objects to base methods ‘An abstract class in SystemVerilog is declared using the keyword "virtual" and is intended to serve as a prototype for its derived subclasses. Here are some key points about abstract classes: ‘An abstract class sets out the prototype for its sub-classes, defining common attributes and behaviors that the derived classes should implement. ‘An abstract class cannot be directly instantiated; it can only be derived to create objects of its derived ‘An abstract class may contain methods for which only the prototype is provided without any implementation. These methods are referred to as abstract methods or pure virtual methods, and they serve as placeholders for the derived classes to provide their own implementation. Let's look at examples illustrating the concepts of instantiating and deriving from an abstract class: Instantiating a Virtual Class: © semved wth Ot Scanner In this example, we attempt to create an object of a virtual class, which results in a compilation error because abstract classes cannot be instantiated. 1 Mpstract class virtual class packet; bit [51:0] addr; endelas ol packet_2 extends packet; // Derived class implementation endolas module virtual_class: Anitial begin packet_2 pr P = new(); // Compilation error: abstract class cannot be instantiated [Link] = end ‘endnodule Error: Instantiation of the object 'p' cannot be done because its type ‘packet’ is an abstract base class Perhaps there is a derived class that should be used. Deriving from a Virtual Class: In this example, we derive a class from an abstract class, providing an implementation for the abstract method defined in the abstract class. / Npstract class virtual class packet; bit [51:0] addr; endclass el extended packet extends packet; function void display: $display ("Vall endfunction endel: ") addr): module virtual_class; Anitial begin extended_packet p; P= new; [Link] = 10; P-display(); // Calling the derived class method end ‘endnodule © semned ith nt Seamer value of addr is 10 Abstraction is an important concept in SystemVerilog and helps in designing modular and extensible code by defining common behavior in abstract classes while allowing specific implementations in derived classes. 14, What are virtual methods? Virtual Methods Virtual methods in SystemVerilog are declared using the keyword "virtual" before the method declaration, There are two types of virtual methods: 2) Virtual functions 2). Virtual tasks. Here's an overview of each > Virtual Functions: ‘A function declared with the virtual keyword before the function keyword is referred to as a virtual function. Virtual functions allow polymorphic behavior, where the derived class can override the implementation of the function defined in the base class, Virtual function syntax: /viztual funetion return_type functien_nane; // Function definition ‘endfunction } Virtual Tasks: ‘Atask declared with the virtual keyword before the task keyword is referred to as a virtual task. Similar to virtual functions, virtual tasks also support polymorphism, allowing the derived class to provide its own implementation of the task defined in the base class. Virtual task syntax: virtual task task_name; // Task definition endtask About Virtual Methods: ‘When a virtual method is used, a base class handle can be assigned an object of a derived class. The behavior of calling the virtual method depends on whether the method is virtual in the base class or not. © semved wth Ot Scanner Consider the following scenario: base_class bcs extended class ec; // Assigning the derived class object to the base class handle besec // Calling the display) method b_c.display(); Y If the display() method in the base class is declared as virtual, then the display() method of the extended class will be called, Y Ifthe display() method in the base class is not declared as virtual, then the base class will be called. isplay() method of the Let's look at examples illustrating the usage of virtual methods: > Method without the Virtual Keyword: In this example, the method inside the base class is declared without the virtual keyword. When calling, the method of the base class using the base class handle pointing to the extended class, the base class ‘method will be invoked. // Parent class class base_class; function void display? $display("Inside base endfunction endolass child class class extended_class extends base_class; function void display? $display (" lass"); endfunction endolass module virtual_class: initial begin base_class be extended_class ec; ec = new; besec b_e.display(; end ‘endnodule © semved wth Ot Scanner Simalator Output: Inside base_class > Method with the Virtual Keyword: In this example, the method inside the base class is declared with the virtual keyword. When calling the method of the base class using the base class handle pointing to the extended class, the extended class method will be invoked. // Parent class class base_class; virtual function void display? Sdisplay("Inside base_ ) endfunction endolas: 7 child class class extended_class extends base_class; function void display? $display ( lass"); endfunction endolass module virtual_class: initial begin base_class be; extended_class ec; ec = new; besec b_e.display(; end ‘endnodule Simulator Output: Inside extended_class In this example, the display() method is declared as virtual in the base class, allowing the derived class method to be called when using the base class handle. © semved wth Ot Scanner 15. What is a virtual class? © Refer to Question - 13, 16. What is a scope resolution operator? The scope-resolution operator (::) in SystemiVerilog is used to access static members or members of an outer scope within a class or module. It allows you to explicitly specify the scope of the member you want to access. Regarding static class members, the scope-resolution operator is used to access static properties or methods of a class without creating an object of that class. Here's how the scope-resolution operator is. used: : : By using the scope-resolution operator, you can directly reference the static members of a class using the class name followed by the operator (::) and the member name, For example, in the given code snippet class A; static int i; endolass program main; A obj_1; initial begin obj_1.i = 1237 Sdisplay (A:ti); end ‘endprogran The line obj_1.i = 123; assigns the value 123 to the static property i of class A using an instance of A. However, to display the value of i, we can directly access it using the scope-resolution operator with the class name: $display(A::i);. This way, we can access the static member i without creating an object of class A ‘The scope-resolution operator is particularly useful when you want to access static members or members of an outer scope within a class or module, allowing you to explicitly specify the scope of the member you want to access. It helps in resolving naming conflicts and accessing members that are not specific to a Particular instance but are associated with the class itself. © semved wth Ot Scanner 17. What is shallow copy? Shallow Copy refers to the process of copying the properties of a main class object without copying the object of its subclass. Ina shallow copy, the copied object shares the same reference to the subclass object as the original object. Let's consider the following example: eu! sub; int addr; endelass int data; sub sub_h = new(); endelass module tb; main M1, M2; initial begin Mi = new; // Create a new instance of the main class M1 Midata = 4; // Set the value of data property in Mi te 4 M1.sub_h.addr = 5; // Set the value of addr property in Mi's sub_h object to 5 M2 = new M1; // Perform a shallow copy by assigning M1 to M2 end, ‘endnodule In the above code, we have a main class and a sub class. The main class contains an integer variable “data” and an instance of the sub class "sub_h". The sub class has an integer variable "addr". The tb module creates two instances of the main class, Mi and M2. During the initialization, M1's data is set to 4, and the addr variable of M1's sub_h object is set to 5. Then, M2 is assigned the value of Mi. Ina shallow copy, only the properties of the main class are copied, not the object of the subclass. So, after the assignment M2 = new M1;, M2 will have its own copy of the main class properties, including the "data" © semved wth Ot Scanner variable. However, M2 will still share the same reference to the sub_h object as M1. This means that any ‘changes made to the sub_h object in M2 will aso affect the sub_h object in M1. It's important to note that shallow copy is the default behavior when assigning objects in SystemVerilog. To perform a deep copy, where both the main class properties and the subclass objects are copied, additional code or techniques, such as a custom copy constructor or assignment operator, would need to be implemented, 18. What is deep copy? Deep copying in SystemVeriiog involves copying all the properties of the main class as well as its subclass. Unlike shallow copy, which only copies nested class handles, deep copy replicates the entire object hierarchy. To achieve deep copying, a custom method needs to be implemented. In a deep copy, a new object is created, and all the properties of the class are copied to the new handle. This ensures that both the main class and its nested class members are duplicated. By performing a full or deep copy, any modifications made to the copied object will not affect the original object. Here is an example of a custom deep copy method in SystemVerilog: ol sub: int addr; // Property to store the address // Custom copy method to perform deep copy function Sub copy; Sub copy_ob} // Create @ new instance of Sub class copy_obj-addr sade; // Copy the address value return copy obj; // Return the copied object endfunction endel: ol Main; int data; // Property to store the data Sub sub_h = new; // Instance of the Sub class // Custom copy method to perform deep copy function Nain copy; Main copy_obj = new; // Create a new instance of Main class copy_obj.data = [Link]; // Copy the data value copy_obj.sub_h = sub_h.copy: // Perform deep copy of sub_h using custom copy method return copy_obj; // Return the copied object © semved wth Ot Scanner endfunction endolass module tb; Main M1, M2; // Objects of the Main class initial begin Mi = new; // Instantiate M1 object [Link] = 4; // Set the data value of M1 M1.sub_h.addr = 5; // Set the addr value of MI's sub_h ol M2 = [Link]: // Perform deep copy by assigning M1 to M2 MZ.sub_h.addr = 10; // Modify the addr value of M2's sub_h object end ‘endnodule In this code, we define two classes: Sub and Main. The Sub class has an integer property addr to store the address. It also includes a custom copy method to perform a deep copy. Inside the copy method, a new instance of Sub called copy_obj is created, and the addr value is copied from the current object using [Link]. Finally, the copied object copy_obj is returned. ‘The Main class contains an integer property data and an instance of the Sub class called sub_h, which represents a nested object. It also includes a custom copy method to perform a deep copy. Inside the copy method, a new instance of Main called copy_obj is created, and the data value is copied from the current object using [Link]. The sub_h object is deep copied by invoking its custom copy method and assigning. ‘the copied object to copy_obj.sub_h. Finally, the copied object copy_obj is returned. In the tb module, we instantiate two objects: M1 and M2 of the Main class. Initially, we create Mi using the new keyword, set the data value to 4, and modify the addr value of the sub_h object. Then, we perform a deep copy by assigning M1 to M2. After the copy, we modify the addr value of the sub_h object in M2. By implementing the deep copy mechanism, each object maintains its independent copies of class properties, including nested objects. This ensures that modifications made to one object do not affect the other abject, providing isolation and preventing unintended side effects. © semved wth Ot Scanner 19. What is method overriding? + Overriding class members allows child classes to redefine or replace properties and methods inherited from the parent class. ‘ Child classes can provide their own implementation of class members while still inheriting the structure and functionality from the parent class. ‘© Class members with the same name as those in the parent class are declared in the child class to override them, ‘ When an object of the child class is created, accessing the overridden member wi implementation defined in the child class. “© Overriding class members provides flexibility and customization in the behavior of child classes, allowing them to modify or enhance the inherited functionality to suit their specific requirements. © Itenables the creation of specialized classes based on a common parent class, invoke the /f Overriding class members // Base class or parent class properties and methods can be overridden in the child class or extended class. // defining the class properties and methods with the same name as the parent class in the child class will override the class members. // overriding class menber example // Parent class class parent_class; bit [51:0] addr; // Parent class display() method function display (); $display(": ") addr) 5 endfunction endolass // Child class extending the parent class class child_class extends parent_clas: bit [51:0] data; // child class display() method overriding the parent class method function display (); Sdisplay ("Data + dated endfunction ‘endel: module inheritance; Anitial begin child_class c = new(); [Link] = 10; © semved wth Ot Scanner e-data = 20; [Link] 0; ond ‘endnodule In the provided example, we have a parent class called parent_class anda child class called child_class that extends the parent class. The parent class has a property addr of type bit [31:0] and a display() method that displays the value of addr. In the child class, we define a property data of type bit [31:0]. We also redefine the display() method in the child class to display the value of data, This is an example of method overriding, where the child class provides its own implementation of the display() method, which overrides the implementation in the Parent class. In the inheritance module, we create an instance of the child class c using the new/) keyword. We assign a value of 10 to the addr property of c and a value of 20 to the data property Finally, we call the display() method on c, which invokes the overridden method in the child class. The simulator output will display: Data = 20 20. What is method overloading? Method overloading in SystemVerilog refers to the ability to have multiple methods with the same name ina class, but with different parameter lists. Each overloaded method performs a different operation based con the specific parameters provided. Let's extend the previous code example to demonstrate method overloading: class ParentClass; bit [51:0] addr; function void displayAddr (); Sdisplay( ", addr) ; endfunction function void displayValue(int value); Sdisplay( » value); endfunetion endolass class Childclass extends ParentClass; © semved wth Ot Scanner bit [21:0] data; function void displaybata (); Sdisplay ("pata , data) endfunction function void displayDatavalue (int value) Sdisplay ("bata i ", data, value); endfunction endolas: module Inheritance; ‘initial begin childclass ¢ [Link] = 10; [Link] = 20; [Link](); // Calls the displayData() method in childclass [Link] (20); // Calls the displayDataValue(int value) method in Childciass [Link] ; // Calls the displayAddr() method in ParentClass fend ‘endnodule new () ‘The ParentClass defines two functions: displayAddr() and displayValue(). displayAddr() simply value of the addr property, while displayValue() takes an integer argument and displays its value, The ChildClass extends ParentClass and adds two additional functions: displayData() and displayDataValue(). These functions operate on the data property of the ChildClass and provide their own display messages. In the Inheritance module, an object of ChildClass named c is created, ‘The addr and data properties of c are assigned values (10 and 20 respectively). [Link]() is called, which invokes the displayData() method defined in ChildClass. It displays the message "Data = 20". [Link](30) is called, which invokes the displayDataValue(int value) method defined in ChildClass. It displays the message "Data = 20, Value = 30", [Link]() is called, which invokes the displayAddr() method defined in ParentClass. It displays the message "Addr = 10” © semved wth Ot Scanner Override versus Overload Method override refers to the ability of an extended class to replace a base class method with, ‘anew implementation. In SystemVerilog, an extended class can override a base class method by defining a method with the same name in the extended class. ‘When an object of the extended class invokes the overridden method, the implementation in the extended class is executed instead of the base class method. ‘The override completely replaces the base class ‘method in the extended class. Method overload allows for the existence of multiple methods with the same name but different parameter lists. Overloading a method means providing multiple versions of the method that can accept different argument types or different numbers of arguments. The appropriate version of the method selected based on the arguments passed to the method. However, in SystemVerilog, method and function overloading is not supported. Due to the complexity of working with loose data types in Verilog and SystemVerilog, overloading methods is not implemented in the language. In summary, while method override is possible in SystemVerilog, method overload is not supported. Overriding a method replaces the base class method in the extended class, whereas overloading would allow for multiple versions of a method with different parameter lists, selected based on the arguments passed to the method. However, due to implementation challenges, method and function overloading is, ‘ot available in SystemVerilog. © semned ith nt Seamer

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