A Detailed Analysis

of Hot-Electron Programming Efficiency

in 40-nm Split-Gate Flash Memory Cells

Yuri Tkachev and Alexander Kotov

Silicon Storage Technology, Inc. (a subsidiary of Microchip Technology, Inc.)
450 Holger Way, San Jose, CA 95134, USA
ytkachev@[Link]

Abstract—Using the precisely measured floating gate compatible integration with the baseline CMOS logic process
capacitance, we were able to extract the absolute values of offered by foundries.
programming efficiency in the 40-nm SuperFlash® memory cells In the current paper we analyzed in detail the programming
at different voltage and temperature conditions. Due to the split- performance of the most advanced 3rd generation of SuperFlash
gate design, the cell shows very fast and efficient programming. It
was shown that the peak injection efficiency may reach 10%.
cell (ESF3). Using the actual floating gate capacitance values,
we were able to evaluate the absolute magnitude of
Index Terms—Flash memory, SuperFlash technology, floating programming efficiency at different voltage and temperature
gate, hot-electron injection, programming, split-gate memory conditions.
cell, single electron.
II. EXPERIMENTAL
I. INTRODUCTION The structure and the typical operating conditions of ESF3
cell are shown in Fig. 1. The cell uses interpoly Fowler–
Between two major types of floating gate-based memories
Nordheim tunneling for erase, and hot electron source-side
– stacked- and split-gate – the split-gate technology gained a
injection for programming. For the current study we used ESF3
big popularity for standalone, and especially for embedded
cell fabricated using 40 nm CMOS technology [7].
NOR flash memory applications [1]. One of the main
advantages of the split-gate flash technology making it During programming, a certain drain current (IPROG) is
particularly attractive for embedded NOR flash solutions, is the flowing through the cell channel, and a fraction of this current
presence of an integrated select transistor, which makes NOR is injected to the FG (IFG). We define programming efficiency
array free from overerase issue and allows one to use simpler EPROG as IFG/IPROG ratio. An example of cell programming
design and program-erase algorithms. Split-gate cell kinetics in terms of cell read current Id and threshold voltage Vt,
architecture also efficiently resolves one of the biggest stacked- is shown in Fig. 2. Here Time-to-Program (T2P) is the
gate cell issues – low programming efficiency, and the programming time required to bring the cell read current below
associated high programming power consumption. a certain reference value, 5 µA in this particular case.
The split-gate concept for improving hot-electron The T2P at nominal operating conditions at IPROG~1 µA is
programming efficiency was proposed in 1980-s [2], [3], and very short (sub-µs). In order to be able to monitor the whole
since then was successfully implemented in a variety of NVM programming kinetics, we intentionally slowed the
technologies [4], [5]. SST split-gate SuperFlash® technology
[6] quickly became the technology of choice for embedded
NOR flash memory due to its superior reliability and
performance characteristics, scalability, as well as due to its

Fig. 1. The structure and typical operation conditions of ESF3 memory cell.
Two mirrored cells sharing common source are shown. Electron transfer
directions during programming (Cell 1) and erase (Cell 2) are schematically
shown by arrows. WL is the word line (select gate), CG is the coupling gate,
EG is the erase gate, BL is the bit line, SL is the source line, and FG is the Fig. 2. An example of programming kinetics at IPROG=1 nA. VCG=10.5V,
floating gate VSL=4.5V, 25C.

978-1-5090-3274-7/17/$31.00 ©2017 IEEE

Fig. 3. The programming current IPROG and substrate current ISUB vs. drain
voltage Vdp at programming conditions. VCG=10.5V, VSL=4.5V, 25C. Fig. 5. Kinetics of cell programming at different CG voltage (shown in
legend). The X-axis is normalized to IPROG =1 µA. SL voltage during
programming – 4.5V.

Fig. 4. Dependence of Time-to-Program vs. programming current IPROG.

VCG=10.5V, VSL=4.5V, 25C.
programming down using much lower IPROG. The programming Fig. 6. Kinetics of cell programming at different SL voltage (shown in legend).
The X-axis is normalized to IPROG =1 µA. CG voltage during programming –
current IPROG can be controlled by drain voltage Vdp, see Fig. 3.
10.5V.
By measuring programming kinetics at different IPROG, we
demonstrated that T2P is inversely proportional to IPROG in a
wide range (see Fig. 4). The programming kinetics shown in
this paper were originally measured at IPROG about 1 nA, and
then the time axis was normalized to the typical user-mode
IPROG =1 µA.
The families of cell programming kinetics measured at
different coupling gate voltage (VCG) and source line voltage
(VSL) are shown in Fig. 5 and 6 correspondingly. Fig. 7 shows
cell Vt vs. VCG with the programming duration as a parameter,
the data extracted from Fig. 5.
To convert the time derivative of Vt into the FG current IFG,
and eventually to the programming efficiency, one needs to
establish a relationship between ΔVt and the FG charge
increment. This can be done by detecting the cell read current
variation caused by a countable number of individual electrons
Fig. 7. Cell Vt vs. CG voltage during programming. The data extracted from
[8]. By comparing the effect of a single electron on cell Vt, with the programming kinetics (Fig. 6). Programming time shown as a parameter.
the effect of CG voltage (see Fig. 8), we found that 1V change VSL=4.5V, 25C.
of cell Vt is caused by 250 electrons. This amount directly
voltages, and experimentally found values of WL, EG, and CG
relates to the CG-FG capacitance (250·q/1V=4.0·10-17 F).
coupling coefficients [9].
To find the dependence of programming efficiency vs. FG
The resulting EPROG-VFG dependencies, extracted from the
potential VFG during programming, we calculated VFG at every
programming kinetics (Fig. 5 and 6), are shown in Fig. 9 and
point of the programming kinetics, using the cell Vt, the gate
Fig. 10 correspondingly. It can be seen that all the points
 apparent simplicity, this method has several drawbacks, such as
a noticeable charge trapping in the FG oxide during current
measurement, which affects injection efficiency, and the need
of a contact to FG, which may lead to the unnecessary
complication of the manufacturing process flow. Knowing the
FG capacitance (and the FG charge corresponding to the Vt
change) we were able to use a regular FG cell for precise and
non-destructive analysis of programming performance.
At the beginning of the programming, the FG potential is
high (8V–10V), due to the charge on the FG, and to the
voltages coupled from the other cell’s nodes. Due to the
inversion layer formed in the FG channel, SL programming
voltage is delivered to the gap. The resulting lateral voltage
drop in the narrow split area, combined with the high vertical
field underneath the FG, makes hot-electron injection in FG-
based split-gate cells extremely efficient. At VSL≈5V, the peak
Fig. 8. (a) The kinetics of cell read current under erase gate stress (4.2V). Each
step on the characteristics corresponds to the removal of a single electron from
efficiency at the beginning of programming can reach a
the FG, equivalent change of Vt is 4 mV. (b) Cell Id-VCG characteristics. whopping 10%.
As the FG potential decreases during programming, EPROG
gradually goes down, and becomes vanishingly small around
extracted from variable VCG kinetics (Fig. 8), fall on the same the FG inversion threshold, where programming virtually
unique EPROG-VFG curve, i.e. the programming efficiency saturates. The effective (integrated) programming efficiency
depends on the FG potential only, which is expected in case of during 1 µs programming is still pretty high and is about
purely coupling effect of VCG. Unlike VCG, the effect of SL 0.04%, which guarantees the effective cell programming in the
voltage is not limited to coupling, and at the same VFG, the sub-µs range. Note that this high efficiency is accompanied by
programming efficiency depends on the distribution of the relatively low carrier multiplication – substrate hole current
lateral electric field in the channel, which in turn is controlled during programming is only about 10% of the IPROG at nominal
by VSL. conditions (Fig. 3), which results in the further relaxed
The programming characteristics, and corresponding EPROG- requirements for the SL charge pump size and output.
VFG dependence at different temperatures in –40C – 150C The programming efficiency sharply drops when SL
range, are shown in Fig. 11 and Fig. 12 correspondingly. voltage approaches the height of the energy barrier at the
Substrate-FG oxide interface (~3V). Some slow programming
III. DISCUSSION however takes place even at lower SL voltages, which is likely
Traditionally programming efficiency in the FG memory caused by high-energy tail of channel electron kinetic energy
cell has been studied by direct measurement of FG injection distribution.
current using a contacted-FG structure [10], [11]. Despite the The non-linear shape of the programming kinetics results in

Fig. 9. Programming efficiency vs. FG potential. Extracted from the Fig. 10. Programming efficiency vs. FG potential. Extracted from the
programming kinetics (Fig. 6). CG voltage during programming shown as a programming kinetics (Fig. 7). SL voltage during programming shown as a
parameter. VSL=4.5V, 25C. parameter. VCG=10.5V, 25C.
 IV. CONCLUSIONS
During programming the split-gate SuperFlash cell, both
lateral and vertical electric fields in the channel have a
configuration favorable for hot-electron injection toward the
floating gate. As a result, very fast, efficient and low-power
programming is achieved.
Using the precisely measured floating gate capacitance, we
extracted the absolute values of programming efficiency in the
40-nm SuperFlash memory cells at wide range of voltage and
temperature conditions.
It was shown that the peak injection efficiency in the
beginning of the programming may reach 10%. The
dependence of programming efficiency vs. FG potential and
temperature was also reported.

Fig. 11. .Programming kinetics at different temperature. VCG=10.5V, REFERENCES

VSL=4.5V. [1] S. N. Keeney, M. Gill, and D. Sweetman, “NOR Flash stacked
and split-gate technology,” in Nonvolatile Memory Technologies
With Emphasis on Flash. A Comprehensive Guide to
Understand and Using NVM Devices, J. E. Brewer and M. Gill,
Eds. Hoboken, NJ: Wiley, 2008, pp. 179–222.
[2] M. Kamiya, Y. Kojima, Y. Kato, K. Tanaka, and Y. Hayashi,
“EPROM cell with high gate injection efficiency,” in Proc.
IEDM, 1982, pp.741-744.
[3] J. Van Houdt, P. Heremans, L. Deferm, and G. Groeseneken,
“Analysis of the enhanced hot-electron injection in split-gate
transistors useful for EEPROM applications,” IEEE Trans.
Electron Dev., 1992, Vol.39, pp.1150-1156.
[4] D. Wellekens, J. Van Houdt, L. Haspeslagh, J. Tsouhlarakis, P.
Hendrickx, L. Deferm, and H. Maes, “Embedded HIMOS Flash
memory in 0.35 µm and 0.25 µm CMOS technologies,” IEEE
Trans. Electron Dev., 2000, Vol.47, pp.2153-2160.
[5] S. Tsuda, Y. Kawashima, K. Sonoda, A. Yoshitomi, T. Mihara,
S. Narumi, et al., “First demonstration of FinFET split-gate
MONOS for high-speed and highly-reliable embedded Flash in
16/14 nm-node and beyond,” in Proc. IEDM, 2016, pp.280-283.
[6] Y. Tkachev, X. Liu, and A. Kotov, “Floating gate corner-
enhanced poly-to-poly tunneling in split-gate flash memory
Fig. 12. Programming efficiency at different temperature vs. FG potential, cells,” IEEE Trans. Electron Dev., 2012, Vol.59, pp.5-11.
Extracted from the programming kinetics (Fig.10). VCG=10.5V, VSL=4.5V. [7] L.Q. Luo, Z.Q. Teo, Y.J. Kong, F.X. Deng, J.Q. Liu, F. Zhang et
al., ”Functionality Demonstration of a High-Density 2.5V Self-
a direct proportionality between cell Vt and VCG, which is Aligned Split-Gate NVM Cell Embedded Into 40nm CMOS
observed at tPROG exceeding 0.1 µs (see Fig. 7). Logic Process for Automotive Microcontrollers,” in Proc. IMW,
2016, pp. 149-151.
The parallel shift of Vt-tPROG characteristics (Fig. 10) is
[8] Y. Tkachev and A. Kotov,”Detection of single-electron transfer
caused by the temperature dependence of programming events and capacitance measurements in submicron floating-gate
efficiency. The change of the shape of Id-tPROG curves is memory cells,” in Proc. ESSDERC, 2006, pp. 411-414.
associated with the effect of temperature on FG channel [9] Y. Tkachev, “Extraction of floating-gate capacitive parameters
transconductance. It can be seen (Fig. 11) that at high VFG, in split-gate flash memory cells,” in Proc. ICMTS, 2016, pp.110-
EPROG at 150C is ~2.5 times lower compared to –40C, which 115.
approximately corresponds to EPROG doubling every 150C. [10] C.-M. Liu, M.-B. Chang, P. Guo, A.V. Kordesh, B. Lee, and K.-
Y. Su, “Macro gate current model and modeling parameter
Although the sign of the effect is consistent with the extraction of the SSI Flash cell,” in Proc. ICSSDM, 2001,
temperature dependence of hot-electron scattering mean free pp.542-543.
path, the observed EPROG temperature dependence in ESF3 cell [11] C.Y.-S. Cho, M.-J. Chen, C.-F. Chen, P. Tuntasood, D.T. Fan,
is weaker than reported previously for a 1st generation and T.Y. Liu, “A novel self-aligned highly reliable sidewall
SuperFlash cell (EPROG doubles every 48C) [10], and for drain- split-gate flash memory,” IEEE Trans. Electron Devices, 2006,
Vol.53, pp.465-473.
side hot-electron injection (EPROG doubles every 28C) [12]. The
[12] S. Tam, P.-K. Ko, and C. Hu, “Lucky electron model of channel
weaker temperature dependence of ESF3 EPROG may be due to hot –electron injection in MOSFET’s,” IEEE Trans. Electron
thinner gap width in scaled ESF3 cells, and because of reduced Devices, 1984, Vol.31, pp.1116-1125.
electron scattering in the gap during programming operation.