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RISC vs. CISC: 20 Key Comparisons

RISC and CISC are processor architectures using different data processing instruction
sets to perform basic logical and input/output operations.

Vijay Kanade AI Researcher February 14, 2023

RISC and CISC represent key processor architectures developed to boost CPU
performance.

RISC and CISC are popular processor architectures that utilize different data
processing instruction sets to perform basic logical and input/output
operations.

This article explains the RISC and CISC processor architectures in detail, along
with the key comparisons between them.

Table of Contents

What Is CISC?

What Is RISC?

CISC vs. RISC: 20 Key Comparisons

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Before we jump into the processor architectures, let’s first understand the
workflow of a typical processor.
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Processors or microcontrollers use ‘instruction sets’ to carry out various tasks.
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Let’s consider an analogy. Say you train your pet to understand certain commands
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such as ‘sleep’ and ‘run,’ which are associated with specific tasks of sleeping and windows 2019 domain enviorment. All
running. Later, when you throw a toy and give the instruction ‘run’ to your pet, it users including the offending user are

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A typical central processing unit (CPU), the brain of a computer, works in a similar
manner, wherein the CPU equates to processors and microcontrollers. Similar to Welcome to today’s edition of the
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the above example, we give instructions to the CPU, which triggers transistors to security and tech news, in brief, along with a
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We input instructions in operation codes or opcodes, which are expressed in the
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instructions are represented via an assembly language, which is further converted
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The collection of all such instructions forms an ‘instruction set.’ This is an

important component of any computing system as the design of several high-level
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A CPU’s performance is deduced based on the number of programs it can run in a Practices

given time span. Mathematically, this is represented as: What Is PowerShell?

CPU performance =Time/Program = Instructions/Program X Cycles/Instructions X

Time/Cycle ….. [Equation 1]

As per this equation, CPU performance depends on the number of instructions in a

computer program. This implies that the more instructions, the more time is
needed to execute them. It can further be simplified into the number of clock
cycles per instruction and time per cycle.

Thus, the CPU performance can be optimized in either of two ways:

Reduce the number of instructions per program, or Table of Contents

Minimize cycles per instruction. What Is CISC?

What Is RISC?

Since these two options are complementary, achieving both at once is impossible. CISC vs. RISC: 20 Key Comparisons
This means that improving one parameter may easily sacrifice the other. However,
all this is just at the surface level; the real optimizations that we intend to
introduce are deeply ingrained in the hardware and instruction set of the CPU.

The primary objective of RISC and CISC architectures is to improve CPU

performance. The fundamental difference between the two is that RISC has less
number of instructions, with each one capable of performing a single operation,
while CISC has a large number of complex instructions capable of carrying out
multiple internal operations.

The CPU industry includes companies supporting and backing either of the two
architectures. For example, Intel’s machines use CPUs that run on the CISC
architecture, while Apple’s CPUs and ARM’s machines come with RISC-based
processors and microcontrollers.

What Is CISC?
CISC stands for ‘Complex Instruction Set Computer.’ This architecture was
introduced in the 1970s by Intel Corporation when the earliest computers focused
on enhancing CPU speed by minimizing the number of instructions per program
(as per equation 1). This objective was achieved by combining multiple simple
commands into one complex instruction.

In the pet analogy, the command ‘run’ can be referred to as a CISC instruction.
When you instruct your pet to run, it performs a set of instructions such as ‘track
the toy,’ then ‘pick the toy up,’ followed by ‘get back to the owner,’ and finally,
‘hand over the toy to the owner.’ As the example reveals, it is a lot more convenient
and faster to give a single ‘run’ instruction to your pet rather than giving it four
independent commands. This is exactly why tech companies such as Intel
preferred designing CISC processors in the initial computing years.

Let’s understand this with a simple CISC ADD instruction, which requires two
inputs:

Memory locations of two numbers essential for an addition

Perform addition and store the result in the first memory location

| ADD 1800, 1801

The ADD instruction picks up numbers from memory locations 1800 and 1801 or
registers. Later, the picked-up numbers are added and eventually stored in location
1800.

Here, a single ADD instruction performs multiple low-level operations, such as

loading numbers from memory, performing the arithmetic ADD operation, and
then storing the result in another memory. The compiler’s workload is reduced
significantly here as high-level instructions are easily computed and stored.
Moreover, these instructions consume minimum RAM as the hardware takes care
of most tasks while decoding the instructions in the beginning stages.

Hence, in CISC architectures, the CPU is entitled to put in more work to perform a
single instruction. As the execution of the instruction takes more time, clock
speeds are compromised. Moreover, CISC operations require more transistors to
decode complex instructions.

Commonly known examples of CISC processors are AMD, Intel x86, VAX, and
System/360.

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What Is RISC?
RISC stands for ‘Reduced Instruction Set Computer.’ These were introduced in the
1980s by David Patterson and John Hennessy to overcome the complexities of CISC
processors. RISC processors work with more instructions; however, the number of
cycles an instruction may take to execute is minimized. In general terms, a RISC
machine takes one CPU cycle to complete one instruction. This may equate to the
‘sleep’ instruction you gave your trained pet.

Let’s consider the same ADD instruction and look at how RISC devices accomplish
it. To begin with, RISC machines do not execute the ADD instruction in one step.
Instead, it is broken down into multiple steps. For example, you need to load the
numbers from memory through a LOAD instruction, followed by an ADD
instruction that adds them, and finally, a STORE instruction that stores the result
in memory.

| Load X, 1600

| Load Y, 1601

| ADD X, Y

| Store 1600, X

In this example, the ‘Load’ instruction loads data at memory location 1600 into
register X. Similarly, the second ‘Load’ instruction picks up data from 1601 and
loads it into register Y. Later, the values in registers X and Y are added. Lastly, the
result X of addition is stored at memory location 1600 or any other location. It is
worth noting that operations in RISC-type processors are performed on ‘registers’
rather than directly on memory.

Although the process seems intricate, as each of these instructions consumes only
one clock cycle, the entire addition operation is accomplished in much fewer clock
cycles. However, such time benefits also present some disadvantages. For instance,
since RISC processors useTech News
simpler & Insights
instruction Newsletter
sets, complex and high-level
instructions need to be divided into multiple, simple instructions.
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The task of breaking down
twicecomplex commands
a week on Monday into simpler ones is trivial and is
and Thursdays.
accomplished by compilers. As a result, software components have more work to
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do in RISC than the processor’s hardware, as seen in CISC. This puts an additional
responsibility on software designers as they are held accountable in case of
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Unlike CISC processors, the logic of RISC machines isSubmit

simple to decode.
Consequently, fewer transistors are required to complete tasks. RISC architecture
uses a simplified set of instructions that tend to work less but execute at a
significant pace. The key feature of such machines is that they enable developers to
fit in more general registers in CPUs and thereby focus on employing parallel
threads to complete complex yet optimized instructions. It boosts internal
parallelism and speeds up the CPU’s instruction execution time.

ARM (Advanced RISC Machine) is a well-known example of the RISC framework. It

is an architecture developed by Arm Ltd. that is based on the design principles of
RISC. Its processors are observed in desktops, laptops, smartphones, gaming
consoles, and several other smart IoT devices that are battery-operated where
energy efficiency is essential.

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CISC vs. RISC: 20 Key Comparisons

The CISC architecture tries to elevate CPU performance by finishing a task in
minimal lines of assembly code, while RISC relies on the strategy of lowering the
execution time of each instruction. For example, on an Intel 8086 processor (CISC
device), multiple operations on two 8-bit numbers may require around 70 to 77
clock cycles. In contrast, a PIC microcontroller (RISC device) may take up to 38
clock cycles. As the example reveals, the RISC device is 2x faster than its CISC
counterpart.

Since CISC devices take more time to execute a single operation, the architecture
does not support the parallel processing and pipelining of instructions. On the
contrary, in the RISC architecture, every instruction is completed in one clock
cycle, thereby promoting the pipelining of instructions.

Here are some of the key differences between CISC and RISC processor
architectures:

Sr. CISC RISC

No.

1. CISC is the short form for Complex RISC refers to Reduced

Instruction Set Computer. Instruction Set Computer.

2. The CSIC architecture processes The RISC architecture executes

complex instructions that require simple yet optimized
several clock cycles for execution. On instructions in a single clock
average, it takes two to five clock cycle. It processes instructions
cycles per instruction (CPI). at an average speed of 1.5 clock
cycles per instruction (CPI).

3. CISC focuses on hardware, such as RISC focuses more on software

RISC vs. CISC: Which is the better

architecture?
Each processor architecture is powerful in its own way. As a result, both types are
exploited for different applications, as revealed in the comparison table above.

If you look at the history of these processor types, you will realize that the CISC
architecture was quite popular when microprocessors and microcontrollers were
first introduced. This was due to the limited access to software capabilities at the
time. However, as time went by, the software field matured, and with its growing
sophistication, companies such as Apple invested in developing the RISC
architecture.

However, today, the CISC architecture is almost obsolete as its development is

becoming increasingly difficult. Since the technology was developed by Intel, the
company continued to invest in it to keep its current hardware and software
backward compatible with x86 processors.

Today’s advanced ARM devices, PICs microcontrollers, and intelligent devices such
as smartphones use the RISC architecture since they are power-efficient, require
fewer resources, and are faster. The only CISC devices existent today are Intel’s
series of x86 processors.

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Applications in 2022

Takeaway
The debate on which architecture is better has been around since the early 1980s.
However, by studying both processors, one realizes there’s no definitive answer to
the question. CISC is more hardware-centric, which implies that transistors on
microchips may only multiply in years to come, thereby increasing the complexity
on the hardware side. On the contrary, RISC presents a software-centric
architecture that is easier to implement and modify. As a result, it can enter the
market in much less time and continue to do so in the near future.

With each approach having its own share of benefits and drawbacks, it is difficult
to weigh in on the better-architecture debate between CISC and RISC.

Did this article help you understand the differences between RISC and CISC
processor architectures? Comment below or let us know on Facebook  , Twitter  ,
or LinkedIn  . We’d love to hear from you!

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Vijay Kanade 
AI Researcher

Vijay A. Kanade is a computer science graduate with 7+ years of corporate experience

in Intellectual Property Research. He is an academician with research interest in
multiple research domains. His research work spans from Computer Science, AI, Bio-
inspired Algorithms to Neuroscience, Biophysics, Biology, Biochemistry, Theoretical
Physics, Electronics, Telecommunication, Bioacoustics, Wireless Technology,
Biomedicine, etc. He has published about 30+ research papers in Springer, ACM, IEEE
& many other Scopus indexed International Journals & Conferences. Through his
research work, he has represented India at top Universities like Massachusetts
Institute of Technology (Cambridge, USA), University of California (Santa Barbara,
California), National University of Singapore (Singapore), Cambridge University
(Cambridge, UK). In addition to this, he is currently serving as an 'IEEE Reviewer' for
the IEEE Internet of Things (IoT) Journal.

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