SYNTHESIS FLOW OF ALU USING GENUS

PROJECT: ALU

NAME: SANTHOSH MUTHABATHULA

[Link]: SHYD2407PDO27
BATCH :JULY PD2 2024
 TABLE OF CONTENTS
CHAPTER 1: INTRODUCTION

1.1 TYPES OF SYNTHESIS

1.2 GOALS OF SYNTHESIS
1.3 INPUTS FOR SYNTHESIS
1.4 OUTPUTS OF SYNTHESIS

CHAPTER 2: FLOW OF SYNTHESIS

2.1 BASIC SYNTHESIS FLOW

CHAPTER 3: COMMANDS
3.1 GENUS COMMANDS
3.2 SDC CONSTRAINTS
3.3 COMPILE (SYN GENERIC, SYN MAP ,SYN OPT)

CHAPTER 4: CHECKS & REPORTS

4.1 CHECKS
4.2 REPORTS

CHAPTER 5: RESULTS
5.1 OUTPUTS
 CHAPTER 1: INTRODUCTION
SYNTHESIS
What is Synthesis

Synthesis is a process of converting high level hardware description language HDL such as RTL code
into gate level netlist that can be implementable lower level of abstraction. Here lower level of
abstraction is Gate level i.e., the circuit is described by logical links and their timing properties
➢ Synthesis process can be optimized for Speed (timing), Area, Testability, Power, Runtime.
1.1 TYPES OF SYNTHESIS:
• Logic synthesis: Logic synthesis involves transforming an RTL or gate-level description of a
digital circuit into an optimized gate-level representation. The goal of logic synthesis is to
minimize the number of gates, reduce power consumption, optimize timing characteristics, and
meet design constraints while preserving the functionality of the circuit.
• Physical synthesis: Physical synthesis, also known as place-and-route synthesis, involves
optimizing the physical implementation of a circuit after logic synthesis. The goal of physical
synthesis is to minimize wire delays, optimize routing resources, and meet timing, area, and
power constraints while ensuring manufacturability and yield.

1.2 GOALS OF SYNTHESIS:

• To get a gate-level netlist

• Inserting Clock gates
• Logic optimization
• Inserting DFT logic
• Logic Equivalence between RTL and Netlist should be maintained.

1.3 INPUTS:
• RTL codes: HDL files: high level description that specifies functional behavior of
the circuit.
• Libraries: cells used in the design that describes their delay, power and area
characteristics.
• Constraints: a set of specifications defined for the design requirements such as timing
constraints, power, area constraints.
• UPF

1.4 OUTPUTS:
• Netlist
• Reports (QOR, Area, Timing etc.)
• UPF (Unified Power Format)
• SDC (Synopsys Design Compiler)
 CHAPTER 2: FLOW OF SYNTHESIS
2.1 Synthesis Flow:

Figure: Basic Synthesis Flow

• RTL: RTL (Register Transfer Level) in a synthesis flow refers to the stage in digital design
where the high-level behavioral description of a digital circuit, typically written in a
hardware description language (HDL) such as Verilog or VHDL, is translated into a lower-
level representation that can be implemented on a target hardware platform. RTL synthesis
is a crucial step in the design process of digital integrated circuits (ICs) or programmable
logic devices (PLDs).

• ANALYZE & ELABORATE: The synthesis tool verifies that the RTL description accurately
captures the desired functionality of the digital circuit. It checks for proper signal
assignments, correct operation of combinatorial logic, and appropriate state transitions in
sequential elements. Any discrepancies or ambiguities in the functional specification are
identified for resolution. After analyze step it generates an intermediate file which is given
as an input for further synthesis flow.

The elaborate command translates the design into technology-independent design (GTECH)
from the intermediate files produced during analysis. It allows changing of parameter values
defined in the source code. Replaces the HDL arithmetic operators in the code with Design
Ware components.

• IMPORT SDC & UPF: In the synthesis flow, the SDC file is imported into the synthesis tool
as input. The tool parses the SDC file to extract timing constraints and other design
constraints specified by the designer. These constraints guide the synthesis process,
ensuring that the synthesized design meets the required timing specifications & goals
The UPF file is imported into the synthesis tool as input. The tool parses the UPF file to extract power-
related constraints and specifications. These constraints guide the synthesis process in optimizing power
consumption, managing power domains, and implementing power-saving techniques such as power gating
and voltage scaling.

• CLOCK GATING: Clock gating logic is inserted into the design to control the clock signal to
specific registers or logic elements dynamically. Once clock gating opportunities are
identified, the synthesis tool inserts additional logic into the design to selectively enable or
disable the clock signal to certain registers or logic elements based on predefined
conditions. This additional logic typically consists of AND gates or multiplexers that control
the clock enable signal based on control signals derived from the design's state or activity.

• COMPILE: The compile step in the synthesis flow plays a crucial role in transforming the
high-level RTL description into an optimized, efficient, and functionally correct gate-level
implementation. It involves various transformations, optimizations, and analyses to achieve
the desired synthesis goals and constraints.

• INSERT DFT: Integrating DFT structures into the synthesis flow, designers can enhance the
testability, and reliability of their digital designs, thereby improving manufacturing yield and
reducing the time-to-market for semiconductor products. DFT insertion is an integral part
of the overall design-for-test (DFT) strategy, which aims to ensure that ICs can be efficiently
and thoroughly tested for defects and faults before deployment in electronic systems.

• COMPILE INCREMENTALLY: In the synthesis flow, "compile incrementally" refers to a

technique where synthesis tools are used to update only the portions of the design that
have been modified, rather than re-synthesizing the entire design from scratch. This
approach helps to save time and resources, particularly in larger designs where only a small
portion of the RTL code has been modified or optimized.
 CHAPTER 3: COMMANDS

3.1 Design Compiler:

For synthesis process we will use “Design Compiler” for converting RTL/ hardware
description level to hardware design. So, for this program we use design compiler from tools
like cadence. You can use command-line interface directly “GENUS”
Steps in Synthesis:
• set library
• raddle
• elaborate
• syngeneic, syn_map, syn_opt
• start_gui and stop_gui after compile
• create_clock
• virtual clock
• set_input_delay
• set_output_delay
• set_driving_cell
• set_load
• set_clock_uncertainy
• group_paths
• report_timing, report_qor, report_area, report_power
• write_file, write_sdc
For Synthesis process, take an example like ALU (Arithmetic Logical Unit)

ALU

Genus :
Genus is a powerful synthesis tool developed by Synopsys. It's widely used in electronic design
automation (EDA) for converting high-level design descriptions into a netlist suitable for physical
implementation. Genus optimizes the design for area, performance, and power consumption, ensuring efficient
hardware realization.

INNVOKING OF GENUS TOOL

2.set_db library

the set_db library command is a scripting command that allows you to set database properties for
various objects in the design database. It is commonly used in the context of configuring or customizing
attributes of the design, libraries, or other tool parameters during synthesis.

library refers to a collection of files and data that define the standard cells, macros, and constraints used
during the synthesis process. These libraries provide the fundamental building blocks that allow the tool to map
the RTL (Register Transfer Level) design into a gate-level netlist optimized for the target technology.

Read_hdl:

the read_hdl command in Cadence Genus is used to import HDL (Hardware Description Language) files
into the synthesis environment. This command reads the RTL (Register Transfer Level) design files
written in HDL languages such as Verilog, VHDL, or SystemVerilog, and adds them to the tool's design
database for processing.
Elaborate:
Builds a design from the intermediate format of a verilog module, a VHDL entity and
architecture, or a VHDL configuration. That is, this command is used to convert RTL to logic.
Elaborate command is typically used after running the analyze command to create database
of cells and other design elements. Once the design is elaborated, design compiler perform
various optimizations on the design, such as mapping the design onto a target technology
library, optimizing for power, area and performing timing analysis.
Syntax: elaborate <top_module_name>
Gui_show:
This command starts the application GUI from the shell promt. It is ignored if the application
GUI has already been started. This is an alias of the gui_start command. It shows the shematic
view of the design.
Syntax: gui_show

3.2 SDC CONSTRAINTS:

Create_clock:
Create_clock command is used to creates a clock object and defines its waveform in the
current design. Create_clock command found in synthesis and timing constraint setup tools,
such as Synopsys Design Constraints (SDC) that specifies the properties of a clock signal in a
digital design.

This command allows the user to specify the characteristics of the clock signal including the
timing constraints that are applied to it throughout the design flow and downstream
analysis.

The create_clock command includes several parameters that define the properties of the
 clock signal, including its frequency, waveform, jitter, duty cycle and more.
by using these commands we findout the all clock domains in the current design.
Get_clock_ports
ALU clock_ports:
After knowing the clock domains, creates the clocks with some period. Example:

create_clock -name <clk_name> -period <period_value> [get_ports <clock_domain>]

Here, <clk_name> is the name for those clock domain by “-name” option and its optional if
its not used then the tool taken as same as name of the clock domain. The <period_value>
specifies the period of the clock (based on technology), for this ALU project, its belongs 28nm
technology so this period should be taken as in nanoseconds, <clock_domain> is specifies
the source signals that are part of the clock tree(clock_domain).
If creates a clock without source_object(clock_domain), its leads to be a virtual clock. We
discussed about it later for more understanding after group_path.

Report_clock:
The report_clock command in dc_shell is used to generate reports about all clock-related
information for a design (clock-tree information). The clock related information like clock
period, clock skew, clock tree structure. The report can aslo help indentify potential clock
tree issuses, such as excessive skew or unexpected clock fanoue.

ample:
report_clock [-name <clock_name>] [-internal] [-setup | -hold | -recover | -remap] [-skew]
[-fanout] [-width] [-depth]
Where,
➢ -name specifies the name of the clock.
➢ -internal restricts the report to only the clock network that is internal to the cell.
➢ -setup reports timing information related to setup time.
➢ -hold reports timing information related to hold time.
➢ -recover reports timing information related to clock domain crossing recovery.
➢ -remap reports timing information related to clock domain crossing remapping.
➢ -skew reports the clock skew information, -fanout reports of clock tree fanout.
 ➢ -width reports the width of each clock buffer and -depth reports the depth of the
clock tree.
The report_clock command is often included in Synopsys Design Constraints (SDC) files to
help identify timing issues in the clock tree and ensure correct operation of the design.

Input delay:
Input delay should be sets input path delay values for the current design. The input delay
applied to input ports of the design by using “set_input_delay” command. The
set_input_delay command is used to specify how much time is used by external logic.
Design compiler then calculates how much time is left for the internal logic. If this command
does not used then the tool will assume an input clock and taken as full clock period then it
will leads to increase the time period for doing functionality of the logic, it should leads to
timing violations.

Assume delay for internal logic is 60% of clock period.

syntax:
set_input_delay <60% of clock period> -clock <clk_name> [get_ports <input_data_ports>]
here, in this project there are two clock domains are there. Those are I1 and clk named as ck1
and ck2 in my design respectively.
So, apply input delay for data ports of related these two clocks.
 I observed that only one data port is appear for related I1 clock domain that is ‘ci’ from start_gui
schematic view representatioin. So for avoiding overwrite input delay interference, input delay
set these port seperately.

From, the above command ‘[remove_from_collection [all_inputs] {I1 clk}]’ for getting data ports for setting
input delay for data ports.

Output delay:
The set_output_delay command sets output path delays on output ports for the current
design. The input and output delays characterize the operating environment of the current
design. The set_output_delay command sets output path delay on the output ports related
to a clock edge. Based on the type of logic we have apply output delay for the output ports.
For example, to describe a path delay to a level-sensitive latch, use the -level_sensitive option
for positive or negative-enabled latchs.
Syntax:
set_output_delay <60% of clock_period> -clock <clock_name> [get_ports <output_ports>]

Check timing:
Gives the warnings when we have any issues with SDC. Syntax:
check_timing

Here, non-unate path is detected. This type of paths are does not identify the corresponding
 output for the logic example Exclusive-OR gate. The non-unate represents a function where
change in output value cannot be determined from the direction of the change in the input.
Output pin value is not dependent on single input pin.
So, we can take one of the pins of the non-unate path logic as a constant value of one of the inputs by
setting ‘set_case_analysis’.

Create generated clock:

The create generated clock command creates a generated clock object in the current design. This
command defines a list of objects as gener- ated clock sources in the current design. You can specify
a pin or a port as a generated clock object. The command also specifies the clock source from which
it is generated. The advantage of using this command is that whenever the master clock changes,
the generated clock changes automatically.

The generated clock can be created as a frequency-divided clock with the-divide by option, a
frequency-multiplied clock with multiply_by, or an edge-derived clock with-edges. In addition, the
frequency- divided or frequency-multiplied clock can be inverted with the invert option. The shifting
of edges of the edge-derived clock is specified with the edge_shift option. The edge shift option is
used for inten- tional edge shifts and not for clock latency. If a generated clock is specified with a
divide factor that is a power of 2 (1, 2, 4,...), the rising edges of the master clock are used to
determine the edges of the generated clock. If the divide factor is not a power of 2, the edges are
scaled from the master clock edges.

Using create_generated_clock on an existing generated_clock object overwrites the attributes of

the generated_clock object.
The generated clock objects are expanded to real clocks at the time of analysis.

Set_clock_uncertainty:
By default Design compiler assumes the clock network are ideal (no delays). To change this behaviour,
we need to use set_clock_uncertainty and set_clock_latency commands.
Uncertainty accounts for varying delays between the clock network branches.
There are two types of uncertainties: simple and interlock. Simple uncertainty means that
setup uncertainty and hold uncertainty applies to all paths to the endpoint. Interlock
uncertainty allows to specify different skew expected to the endpoint or between the clock
domains.
The recommendation is to set the uncertainty to the worst skew expected to the endpoint
or between the clock domains. We can always increase the value to account for additional
margin for setup and hold.
Syntax:
 Set_clock_uncertainty -setup <20% of clockperiod> | -hold <18% of clockperiod>
[get_clocks <clock_name>]

Set_driving_cell:
This constraint specifies the external drive strength of input port.
By default, tool assumes zero drive resistence on input ports, meaning infinite drive strength.
Alternately we can use set_drive and set_input_transition, but not gives accurate as above.
Syntax:
set_driving_cell [-lib_cell <lib_cell_name>] [-rise] [-fall] [-library <lib_name>] [-pin
<pin_name>] [-from <from_pin_name>] [-multiply_by factor] [-don’t_scale] [-
no_design_rule] [-input_transition_rise] etc.,
set_driving_cell -lib_cell <lib_cell_name> [get_ports <input_ports>]

Set_load:
During the synthesis process, its important to accurately model the load capacitance on the
output signals of the synthesized design. The load capacitance represents the combined
capacitance that the output driver of a circuit must drive, including the capacitance of the
interconnects and the input capacitance of the next stage in the design.
To specify the load capacitance in synthesis, ttypically use design constraints or script that
provide information to the synthesis tool about the load the output driver needs to handle.
This information helps the synthesis tool optimize the design for factors such as timing,
power and signal integrity. The specific method for specifying the load capacitance can vary

depending on the synthesis tool and the design flow being used. However, a general example
using the Synopsis Design Constraints (SDC) language.
Syntax:
set_load <cap_value> [get_ports <output_ports>]

Filter collection:
Filters an existing collection, resulting in a new collection. The base collection remains
unchanged. In many cases, application commands that create collections support a filter
option that filters as part of the collection process, rather than after the collection has been
made.
This type of filtering is almost always more efficient than using the filter collection command
after a collection has been formed. The fil- ter collection command is most useful if you plan
to filter the same large collection many times using different criteria.
The filter collection command results in either a new collection or an empty string. A
resulting new collection contains the subset of the objects in the input collectionl. A resulting
empty string (the empty collection) indicates that the expression filtered out all elements of
the input collectionl.
The basic form of the conditional expression is a series of relations joined together with AND
and OR operators. Parentheses () are also supported. The basic relation compares an
attribute name with a value through a relational operator.

Virtual clock:
Virtual clock is used to met i2o(input to output) timing path groups, there is no clock between
the i2o, for general we apply the clock input delay for all input ports. For i2o path groups
does not have the clock, but by appling input delay and output delay of 60% of both, it leads
to extended the clock period then the data arraival time should not be in the required time.
Then the timing violations should be occurred. For avoid this type of violations we have to
decrease the input and output delays for the i2o paths. For this purpus we have to create
virtual clock and 30% delay of this clock period of input and output delays are applied for the
inputs and outputs related to the i2o paths.
Virtual clock does not have any clock source that is the clock is create virtually for done
functionality of i2o paths for timing met.
Syntax:
Create_clock -name <virtual_clock_name> -period <time_period>
 Timing paths:
Timing analysis involves breaking a design down into sets of timing paths then calculating the
delay for each path. There are four types of timing paths are available in the circuit design.
Example for timing paths shown in the below figure,

Figure: timing paths

Path groups are:
➢ Input to register path : data from input port/pin to register data pin path
➢ Register to register path : data from register clock pin/port to register data pin path
➢ Register to output path : data from register clock pin/port to output port path
➢ Input to output path : data from input port to output port path
Path groups are automatically created when the create_clock or group_path command is
used. The default path group contains all paths not captured by a clock. We can use the
report_path_group command to see which groups of paths have.
The group_path command is used to create path groups for timing analysis and
optimization. Path groups allow to specify specific paths or groups of paths within the design
that should be treated as a single unit during optimization or timing analysis.
Syntax:
Group_path -name <grp_name> -from <source> -to <destination>
Where,
-name : specifies the name for the path group
-from : specifies the source of the path group, such as input ports, registers, or other elements.
-to: specifies the destination of the path group, such as output ports, registers, or other
elements.
By using the group_path command, define path groups to constrain optimization or analysis
operations within specific paths of the design. This allows for more targeted optimization and
analysis, ensuring the desired timing requirements are met.

3.3 COMPILE
SYN GENERIC:

the term "syn_generic" refers to the generic synthesis mode or feature where the tool
synthesizes the RTL design into a technology-independent netlist. This means the synthesized design is
not yet mapped to any specific standard cell library and instead uses generic cells to represent the
functionality.

Generic synthesis is an intermediate step in the synthesis process where the tool creates a high-level,
technology-independent representation of the design. The synthesized netlist contains generic cells
(e.g., AND gates, OR gates, flip-flops) that are not tied to any specific library or technology.

Syntax: syn_generic
SYN_MAP :
1. Technology Mapping:
The syn map command maps the synthesized design's logic gates (from RTL) to the
standard cells provided in the technology library. This ensures that the design uses
actual physical components like NANDs, NORs, or flip-flops available in the target
technology.
2. Optimization for Timing and Area:
During synthesis, the mapping process tries to meet the timing, area, and power
constraints. The syn map step evaluates delays, slack, and power characteristics to
choose the best-matching cells.
3. Gate-level Netlist Generation:
After mapping, the tool generates a gate-level netlist that can be used for Static Timing
Analysis (STA), placement, routing, and further downstream processes.
Syntax: syn_map
 SYN_OPT :
The syn_opt command in Cadence Genus is used during the synthesis process to optimize a design with
respect to specific constraints, such as timing, area, and power. It is a critical step in Static Timing Analysis
(STA) and is executed to ensure the synthesized netlist meets the design specifications.

Key Features of the syn_opt Command:

1. Timing Optimization: Adjusts the design to resolve any timing violations, such as setup or hold time
issues, ensuring it meets the specified timing constraints.

2. Area Optimization: Reduces the area by minimizing the number of gates or other logic elements while
still meeting timing and other design goals.

3. Power Optimization: Aims to reduce dynamic and leakage power by resizing gates, using lower-power
cells, or adjusting logic where feasible.

4. Iterative Refinement: Runs multiple iterations of optimization to balance timing, area, and power trade-
offs.
5. By using syn_opt effectively, designers can achieve a balanced trade-off between timing, power, and
area, ensuring that the design is both functional and efficient.
 CHAPTER-4: CHECKS & REPORTS
4.1 REPORTS:
Report timing:
The report_timing command is used for the tool to checking timing violations and for particular
paths. This command will analyze the timing paths in the design and generate a detailed report
displaying timing information for each path. The report will include information such as:

• Slack: the tming slack represents the amount of time a path has before violating the
specified timing constraints. Positive slack values indicate that the path is meeting
timing requirements, while negative slack values indicate violatiions.

• Paths: the report will list the critical timing paths in the design, including the path
delay and delay components for each path.
• Violations: if there are any setup or hold violations, the report will highlight those
paths and provide details about the violation.
Syntax:
• Report_timing : for display all path group types timing information.
• Report_timing -group <group_name> : displays particular path group
timing information.
• Report_timing -slack [greater_than <value> | lesser_than <value>] : display
the paths based on their slack information value.
From, the above report_timing r2r and i2r timing path groups are violated. r2r (register to register)
paths are violated because of arrival time for data is 4.66ns then these time should not be available
for ck2 time period (2.5ns), required time for data arrival is 1.87ns.
So, for this problem we have to taken multicycle path by setting 2 cycles for data arriving. Its
enough time for data arriving, then r2r paths are met.
Syntax:
set_multicycle_path <required_cycles> -from <start_reg_clk> -to <end_reg_clk>
i2r (input to register) paths are violated because the input delay is not enough for the logic. So
we have to decrease the input delay for met the i2r paths.
update_timing and compile and observe the report_timing for i2r and r2r timing paths. By doing
several stages like this timing paths should be met.
These reports are after setting multicycle path and decreasing input delay. The r2r and i2r timing paths
are met.

REPORT QOR:
To generate Quality of Results (QoR) report containing various optimization results and
statistics for the design. For saving this report by using redirectional operator ‘>>’.
Example, report_qor >> alu_rqor.txt
If the file does not exist, it will created. If the file already exist, the new will be appended to
the existing one.
The QoR report typically includes information such as area utilization, power consumption,
timing constraints, critical paths and other relevent optimization metrics.
Syntax:
report_qor :

Report area:
This command used to generate area report and also saved by using redirectional operator.
Syntax:
 report_area :

REPORT GATE:

the "report gate" command is used to generate detailed information about the gates present in the
synthesized design. This report helps in analyzing the gate-level characteristics of the design after synthesis,
such as the type and number of gates, their instances, and their distribution.

1. -cell: Reports the cell types used in the design (e.g., AND, OR, XOR, etc.).
2. -hierarchy: Reports gate information hierarchically for sub-modules in the design.
3. -summary: Provides a summarized view of the gate count and type.
4. -output <filename>: Saves the report to a specified file instead of displaying it in the terminal.
5. -library <lib_name>: Limits the report to cells from a specific library.
 4.2 CHECKS:

CHECK TIMING: This shows the potential timing problems in the design.
This checks timing attributes placed on the current design and issue warnings.
It performs checks on:
o Gated clocks
o Generated clocks
o Combinational loops
o no clock is defined
o Input delay
o Unconstrained end points
o Clock crossing
o Data check

• CHECK DESIGN: Runs pre-defined and user defined checks on the current design.
It checks the internal representation of the current design for consistency, and
issues error and warning messages.

The check_design command in Cadence Genus is used to perform a comprehensive validation of

the design during the synthesis process. This command identifies and reports potential issues in
the design, ensuring that it is free of structural, functional, and connectivity errors. It is an
essential step in verifying the correctness of the design before proceeding to more advanced
stages of synthesis and implementation
5.1 OUTPUTS:
Net list:
The netlist is a file contains information about hierarchical, in the GTECH format. After
compile and synthesized design netlist should be created.
Syntax:
Write_file -format verilog -hierarchy -output alu_netlist.v
This command generates a verilog netlist file in the GTECH format, which hierarchy
information included, for a design that has been synthesized using Design Compiler. The
resulting netlist file is named ‘alu_netlist.v’.
SDC:
To write Synopsys Design Constraints (SDC) file in DC shell, by using “write_sdc”
command
after load, compile and synthesized design in the
dc_shell. Syntax:
write_sdc <file_name>
example, write_sdc alu_sdc
This command will create an SDC file name “alu_sdc” in the current working directory. This
SDC file containts the constraints and timing information extracted from the synthesized
design.
GOALS OF SYNTHESIS:
The main goal of synthesis is to optimize the maximum possible in design or circuit .to ensure
the slack is >= 0, and then generate the required inputs for placement and routing (PNR)

• To get a gate-level netlist

• Inserting Clock gates
• Logic optimization
• Inserting DFT logic
• Logic Equivalence between RTL and Netlist should be maintained.

OUTPUTS:
• Netlist
• Reports (QOR, Area, Timing etc.)
• UPF (Unified Power Format)
• SDC (Synopsys Design Compiler) constraints

INPUTS FOR PNR:

1. Netlist
• A synthesized gate-level netlist in a format like Verilog or VHDL, which represents the
logical representation of the design.
2. Timing Constraints
• SDC File (Synopsys Design Constraints): Defines the timing constraints, such as clock
definitions, input/output delays, and multi-cycle paths.
3. Technology Library
• Standard Cell Library (.lib): Includes the timing, power, and functional characteristics
of the cells.
• LEF File (Library Exchange Format): Contains the physical information like cell
dimensions and pin locations.
4. Design Constraints
• Physical constraints such as floorplan, pin placements, and blockages.
5. Power Intent (Optional)
• UPF/CPF (Unified Power Format/Common Power Format): Defines the power
domains and related information for low-power designs.
6. Clock Constraints
• Clock tree synthesis (CTS) requirements such as clock definitions, clock buffers, and
tree structure information.