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VLSI Testing and Verification Exam 2017

The document outlines the examination paper for the Second Semester M.Tech in VLSI Design & Embedded Systems at Siddaganga Institute of Technology. It includes various questions related to VLSI testing and verification, covering topics such as fault simulation, D-algorithm, DFT techniques, boundary scan registers, and functional verification. The exam consists of six questions, from which students must answer any five in a 3-hour timeframe for a maximum of 100 marks.

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Bhavya Gowda
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12 views2 pages

VLSI Testing and Verification Exam 2017

The document outlines the examination paper for the Second Semester M.Tech in VLSI Design & Embedded Systems at Siddaganga Institute of Technology. It includes various questions related to VLSI testing and verification, covering topics such as fault simulation, D-algorithm, DFT techniques, boundary scan registers, and functional verification. The exam consists of six questions, from which students must answer any five in a 3-hour timeframe for a maximum of 100 marks.

Uploaded by

Bhavya Gowda
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

US 2LVS03

Siddaganga Institute of Technology, Tumakuru – 572 103


(An Autonomous Institution affiliated to Visvesvaraya Technological University, Belgaum, Approved by AICTE, New Delhi, Accredited by NBA, New Delhi,
An ISO9001:2008 Certified)

Second Semester [Link], VLSI Design & Embedded system Examinations 2017
Electronics and Instrumentation Engineering Department
VLSI Testing and Verification
Time: 3 Hours Max. Marks: 100
Not : 1. Answer any Five full questions
e

1. a. What is fault simulation? Explain different types of fault simulations with examples. 8M
b. What is stuck at fault in digital circuits? With example explain different type of
stuck at faults. 6M
c. Find the test set to determine the S-A-1 fault at node h in the Fig.1(c )using Boolean
difference method. 6M

Fig.1(c)

2. a. Find test vector to test S-A-0 fault at node Z in Fig.1(a) using Boolean
Difference method. 6M

Fig. 2(a)
b. Mention basic steps involved in implementing D-algorithm. Find suitable test vector
for SA-1 at α in Fig.2(b) using D-algorithm. 10M

c. Write the difference between FAN and PODEM methods. 4M

3. a. How are DFT techniques categorized? Explain Ad hoc techniques. 10M


b. Define terms controllability and observability. Explain scan path technique for testable
sequential circuits with one example. 10M
4. a. With neat block diagram, explain how a boundary scan register can be used
for Testing Chips. 8M
b. Explain BILBO based BIST architecture. 4M
c. Explain following RAM Testing algorithms 8M
 March test zero-one algorithm
 Checker board algorithm
 Butterfly algorithm
 NPSF algorithm

5. a. Discuss the methods to reduce the human intervention in verification. 6M


b. Explain model checking with its model checking path diagram. 6M
c. What is functional verification? Discuss three complementary approaches used
for functional verification. . 8M

6. a. What is unateness of a signal? Explain with waveforms. 8M


b. Discuss various timing parameters used in static timing analysis. 6M
. c. What is the need for parasitic extraction and how it is used in back annotation? 6M

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