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8-Bit Counter Frequency Division Report

The laboratory report details an experiment on frequency division using an 8-bit counter, demonstrating how a clock pulse can be divided into lower frequency signals. It includes theoretical background, requirements, Verilog code for the counter and test bench, observations, and results of the experiment. The conclusion emphasizes the understanding of frequency division and its applications in various fields such as communication and digital signal processing.

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8 views7 pages

8-Bit Counter Frequency Division Report

The laboratory report details an experiment on frequency division using an 8-bit counter, demonstrating how a clock pulse can be divided into lower frequency signals. It includes theoretical background, requirements, Verilog code for the counter and test bench, observations, and results of the experiment. The conclusion emphasizes the understanding of frequency division and its applications in various fields such as communication and digital signal processing.

Uploaded by

VVK VINAYAKA
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Laboratory Report

On

Frequency Division using 8-Bit Counter

(Name of the Lab in brackets and in italics)

Submitted by

Name of Student 1 (Roll number)


Name of Student 2(Roll number)
Name of Student 3(Roll number)
Name of Student 4(Roll number)
Name of Student 5(Roll number)

[Link] Programme in Electronics and Telecommunication


Engineering

School of Electronics Engineering


Kalinga Institute of Industrial Technology, Deemed to be University
Bhubaneswar, India

October 2018
OBJECTIVE

A clock pulse can be divided into n parts using a n-bit counter, in this
experiment, we would be simulating the division of a clock frequency by a
8-bit counter.

THEORY

A clock divider circuit creates lower frequency clock signals from an input
clock source.

The divider circuit counts input clock cycles and drives the output clock
low and then high for some number of input clock cycles.

An n-bit counter can produce n divided clock signals, with each successive
bit oscillating at one-half the frequency of is less significant neighbor. Each
bit divides the input clock by a “power of 2”, where the exponent is the bit
+1 on the counter.

In an 8-bit counter, the output frequency fout can be derived from the input
frequency fin using the formula:

fout = fin/2n ,where n is the bit of the counter output.

Thus, for an 8-bit counter, n ranges from 1 to 8 and we observe:


i. Observing the 1st bit output gives: fout = fin/2
ii. Observing the 2nd bit output gives fout = fin/22 = fin/4
iii. Finally, the 8th bit output gives fout = fin/28= fin/256
REQUIREMENTS
Requirements for the experiment as follows:

Software(s) Used: Vivado 2016.1

SCHEMATIC DIAGRAM

CODE DEVELOPMENT

The Verilog Code is attached below:


1. Design:
Fig. 1. Put appropriate figure caption (font size 10)

module eightbitctr1(
input clk, rst,
output reg [7:0] counterout
);

always @ (posedge(clk), posedge(rst))


begin
if (rst) counterout <= 0;
else counterout <= counterout + 1;
end
endmodule
2. Test Bench:

`timescale 1ns / 1ps

module eightbitctr1_test;
reg clk;
reg rst;
wire [7:0] counterout;

counter1 uut (
.clk(clk),
.rst(rst),
.counterout(counterout)
);

// Clock generation
initial begin
clk = 0;
forever #10 clk = ~clk; // Toggle clock every 10 ns
end

initial begin
rst = 1;
#20; //reset for 20 ns

rst = 0;
#100; //100 ns

rst = 1;
#20; //reset for 20 ns

rst = 0;
#80; // 80 ns

$finish;
end
end
endmodule

OBSERVATIONS/RESULTS

Clock Cycle for 8 Bit Counter:

Counter Output
Clock Cycle Counter Output (Binary) (Decimal)
0 0 0
1 1 1
2 10 2
3 11 3
4 100 4
5 101 5
6 110 6
7 111 7
8 1000 8
9 1001 9
10 1010 10
... ... ...
255 11111111 255
256 0 0 (overflow)

Verilog Schematic for the experiment :


Simulation for the experiment:

DISCUSSION OF RESULTS

The following experiment shows how the clock pulse division works.

This division of frequency can be used in a plethora of areas including:

1. Communication.
2. Digital Signal Processing
3. Wireless Communication Systems
4. Microcontrollers.

CONCLUSION:
Thus, we understood the working, design and related theory of Frequency
Division via a n-bit (and in this case a 8-bit) counter, as well as its
applications.

REFERENCES:

1. Digital Design (M. Morris Mano, Michael [Link]) – Pearson


2. Electronics Tutorials: [Link]
STUDENT SIGNATURES

All students of the group should provide full signatures with submission
date.

SIGNATURE OF THE CONCERNED LAB FACULTY MEMBER

Signature of the concerned lab faculty member with date and comments (if
required)

Common questions

Powered by AI

Clock cycle overflow in an 8-bit counter occurs when the counter reaches its maximum value (255 for an 8-bit binary counter) and then resets back to 0 on the next clock pulse. This is inherent in the counter's design, where the increment operation causes the binary number to wrap around to zero after reaching the maximum binary value of '11111111' .

A clock divider circuit functions by counting the input clock cycles and then driving the output clock low and high for a specific number of input clock cycles. Each bit of an n-bit counter divides the input clock by a power of 2, based on its position in the counter, thereby producing a lower frequency signal. For instance, in an 8-bit counter, the 8th bit output gives an output frequency that is fin divided by 256 .

Reset conditions are implemented using a reset signal ('rst') in the Verilog test bench. This signal, when high, resets the counter to zero, ensuring a known and predictable starting state. It is crucial for verifying the design's repeatability and stability, as reliable reset conditions prevent erratic behaviors due to undefined states upon powering the system .

The Verilog code defines a module 'eightbitctr1' that uses a register 'counterout' to store the current count value. On each positive edge of the clock or reset signal, it checks if a reset is active to reset the counter, otherwise, it increments the counter. This incrementation corresponds to counting the input clock cycles, crucial for frequency division as described, with each bit of 'counterout' representing a different frequency division factor .

Vivado is shown to be effective for the frequency division lab as it allows for both design and testing in a seamless environment. Its capabilities in simulation and synthesis help verify the Verilog code and expected outcomes, providing clarity on counter behavior and facilitating learning about frequency division circuits' functionality .

The Verilog schematic illustrates the sequential logic of the 8-bit counter, while the simulation executes this logic to exhibit real-time outputs over several clock cycles. By comparing these outputs to predicted binary and decimal values, one can confirm the counter's correct operation. Discrepancies between outcomes and theoretical predictions would prompt a review of either the logic design or understanding of the theoretical model .

The formula fout= fin/2^n is based on the idea that each bit in an n-bit counter toggles at half the frequency of the next less significant bit. As each bit increases, the toggle interval (number of input clock cycles required for a state change) doubles, effectively dividing the input clock frequency by increasing powers of 2. This results in the formula, where 'n' specifies the bit in question .

The report highlights several applications of frequency division, including communication, digital signal processing, wireless communication systems, and microcontrollers. These applications are significant as they rely on precise timing and frequency control, which frequency division provides by creating stable clock signals at desired frequencies .

To verify the functionality of the 8-bit counter, one would implement a test bench in Verilog as given, initializing the clock signal and toggling it at a regular interval. After setting up the reset conditions as specified, the counter output should be monitored for expected behavior over time, essentially checking if it increments correctly with each cycle and correctly resets on input reset .

Using an 8-bit counter limits the division factor to powers of 2 up to 2^8, or 256. This may be insufficient for applications needing finer control or larger reduction scales, where a higher bit counter (such as 16-bit) would provide more division options (up to 2^16). Thus, the choice between 8-bit and a higher bit counter depends on the specific frequency requirements of the application .

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