Computer Architecture

MA 305

Dr. Daya Sagar Gupta

Department of Mathematics, IIT Patna

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 Lecture No. - 35 & 36

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I/O interfacing

⇒ Input-output interface provides a method for transferring information between

internal storage and external I/0 devices.

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Need for I/O interface

1 Peripherals are electromechanical and electromagnetic devices and their man-

ner of operation is different from the operation of the CPU and memory, which
are electronic devices. Therefore, a conversion of signal values may be required.
2 The data transfer rate of peripherals is usually slower than the transfer rate of
the CPU.
3 Data codes and formats in peripherals differ from the word format in the CPU
and memory.
4 The operating modes of peripherals are different from each other and each
must be controlled so as not to disturb the operation of other peripherals
connected to the CPU.

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I/O command

1 A control command is issued to activate the peripheral and to inform it what

to do.
2 A status command is used to test various status conditions in the interface
and the peripheral.
3 A data output command causes the interface to respond by transferring data
from the bus into one of its registers.
4 The data input command is the opposite of the data output. In this case
the interface receives an item of data from the peripheral and places it in its
buffer register.

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I/O versus Memory Bus

⇒ There are three ways that computer buses can be used to communicate with
memory and I/O:
1 Use two separate buses, one for memory and the other for I/O.
2 Use one common bus for both memory and I/O but have separate control lines
for each.
3 Use one common bus for memory and I/O with common control lines.

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Isolated versus Memory-Mapped I/O

⇒ The I/O read and I/O write control lines are enabled during an I/O transfer.
The memory read and memory write control lines are enabled during a memory
transfer. This configuration isolates all I/O interface addresses from the addresses
assigned to memory and is referred to as the isolated I/O method for assigning
addresses in a common bus.
⇒ In the isolated I/O configuration, the CPU has distinct input and output
instructions, and each of these instructions is associated with the address of an
interface register.
⇒ In computers that employ only one set of read and write signals and do not
distinguish between memory and I/O addresses. This configuration is referred to
as memory-mapped I/O.
⇒ In a memory-mapped l/0 organization there are no specific input or output
instructions. The CPU can manipulate I/O data residing in interface registers with
the same instructions that are used to manipulate memory words.

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Serial versus Parallel transmission

Serial Parallel
Shift registers are required No need
Burst error Bit error
Cheap Costly
Less reliable More reliable
More distance Less distance
Table:

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Synchronous versus Asynchronous transmission

⇒ The internal operations in a digital system are synchronized by means of clock

pulses supplied by a common pulse generator.
⇒ Clock pulses are applied to all registers within a unit and all data transfers
among internal registers occur simultaneously during the occurrence of a clock
pulse.
⇒ Two units, such as a CPU and an I/O interface, are designed independently of
each other.
⇒ If the registers in the interface share a common clock with the CPU registers,
the transfer between the two units is said to be synchronous.
⇒ In most cases, the internal timing in each unit is independent from the other in
that each uses its own private clock for internal registers. In that case, the two
units are said to be asynchronous to each other.

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Asynchronous transmission

⇒ Asynchronous data transfer between two independent units requires that

control signals be transmitted between the communicating units to indicate the
time at which data is being transmitted.
⇒ It can be done in two manners.
⇒ Strobe signal
⇒ Handshaking signal
⇒ Asynchronous Serial Transfer

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Strobe Control I
⇒ The strobe control method of asynchronous data transfer employs a single
control line to time each transfer. The strobe may be activated by either the
source or the destination unit.
⇒ Source-initiated strobe for data transfer.

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Strobe Control II

⇒ Destination-initiated strobe for data transfer.

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Handshaking Control I

⇒ The disadvantage of the strobe method is that the source unit that initiates
the transfer has no way of knowing whether the destination unit has actually
received the data item that was placed in the bus and vice-versa
⇒ One control line is in the same direction as the data flow in the bus from the
source to the destination. It is used by the source unit to inform the destination
unit whether there are valid data in the bus. The other control line is in the other
direction from the destination to the source. It is used by the destination unit to
inform the source whether it can accept data.
⇒ Source-initiated transfer using handshaking.

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Handshaking Control II

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Handshaking Control I
⇒ Destination-initiated transfer using handshaking

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Asynchronous Serial Transfer I

⇒ A serial asynchronous data transmission technique used in many interactive

terminals employs special bits that are inserted at both ends of the character code.
⇒ With this technique, each character consists of three parts: a start bit, the
character bits, and stop bits.
⇒ A transmitted character can be detected by the receiver from knowledge of the
transmission rules:
1 When a character is not being sent, the line is kept in the 1-state.
2 The initiation of a character transmission is detected from the start bit, which
is always 0.
3 The character bits always follow the start bit.
4 After the last bit of the character is transmitted, a stop bit is detected when
the line returns to the 1-state for at least one bit time.

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Asynchronous Serial Transfer II

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Modes of Transfer

⇒ Data transfer between the central computer and I/O devices may be handled in
a variety of modes.
1 Programmed I/O
2 Interrupt-initiated I/O
3 Direct memory access (DMA)

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Programmed I/O

⇒ Programmed I/O operations are the result of I/O instructions written in the
computer program.
1 Read the status register.
2 Check the status of the flag bit and branch to step 1 if not set or to step 3 if
set.
3 Read the data register.

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Interrupt-initiated I/O

⇒ While the CPU is running a program, it does not check the flag. However,
when the flag is set, the computer is momentarily interrupted from proceeding
with the current program and is informed of the fact that the flag has been set.
⇒ The CPU deviates from what it is doing to take care of the input or output
transfer. After the transfer is completed, the computer returns to the previous
program to continue what it was doing before the interrupt.
⇒ The way that the processor chooses the branch address of the service routine
varies from one unit to another.
⇒ vectored interrupt: In a vectored interrupt, the source that interrupts supplies
the branch information to the computer. This information is called the interrupt
vector.
⇒ nonvectored interrupt: In a non vectored interrupt, the branch address is
assigned to a fixed location in memory.

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Priority Interrupt

⇒ A priority interrupt is a system that establishes a priority over the various

sources to determine which condition is to be serviced first when two or more
requests arrive simultaneously.
⇒ The system may also determine which conditions are permitted to interrupt the
computer while another interrupt is being serviced.
⇒ Devices with highspeed transfers such as magnetic disks are given high priority,
and slow devices such as keyboards receive low priority.
1 Software based implementation (Polling)
2 Hardware based implementation (Serial connection and Parallel connection)

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Daisy-Chaining Priority

⇒ The daisy-chaining method of establishing priority consists of a serial

connection of all devices that request an interrupt.

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Parallel Priority Interrupt

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Direct Memory Access-DMA

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