UNIT II & IV – 8085 Theory & Instruction Set

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Notes By: Raju Poudel (Mechi Multiple Campus)
Introduction to 8085 Microprocessor
• 8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit
microprocessor designed by Intel in 1977.

• It has the following configuration –

- 8-bit data bus
- 16-bit address bus, which can address up to 64KB
- A 16-bit program counter
- A 16-bit stack pointer
- Six 8-bit registers arranged in pairs: BC, DE, HL
- Requires +5V supply to operate at 3.2 MHZ single phase clock

• It is used in washing machines, microwave ovens, mobile phones, etc.

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Notes By: Raju Poudel (Mechi Multiple Campus)
8085 Microprocessor Architecture & Functional Units

Fig: Block Diagram of 8085 Microprocessor

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Notes By: Raju Poudel (Mechi Multiple Campus)
8085 Microprocessor Architecture & Functional Units
8085 consists of the following functional units −
1) Accumulator
It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE operations. It is
connected to internal data bus & ALU.
2) Arithmetic and logic unit
As the name suggests, it performs arithmetic and logical operations like Addition, Subtraction, AND,
OR, etc. on 8-bit data.
3) General purpose register
There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each register can hold 8-
bit data. These registers can work in pair to hold 16-bit data and their pairing combination is like B-C,
D-E & H-L.
4) Program counter
It is a 16-bit register used to store the memory address location of the next instruction to be
executed. Microprocessor increments the program whenever an instruction is being executed, so that
the program counter points to the memory address of the next instruction that is going to be
executed.

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Notes By: Raju Poudel (Mechi Multiple Campus)
8085 Microprocessor Architecture & Functional Units
5) Stack pointer
It is also a 16-bit register works like stack, which is always incremented/decremented push & pop
operations.

6) Temporary register
It is an 8-bit register, which holds the temporary data of arithmetic and logical operations.

7) Flag register
It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending upon the result
stored in the accumulator.
These are the set of 5 flip-flops –
- Sign (S)
- Zero (Z)
- Auxiliary Carry (AC)
- Parity (P)
- Carry (C)

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Notes By: Raju Poudel (Mechi Multiple Campus)
Flag register
a) Sign Flag (S) – After any operation if result is negative sign flag becomes set, i.e. If result is positive
sign flag becomes reset i.e. 0.
Example:
– MVI A 30 (load 30H in register A)
MVI B 40 (load 40H in register B)
SUB B (A = A – B)
These set of instructions will set the sign flag to 1 as 30 – 40 is a negative number.

– MVI A 40 (load 40H in register A)

MVI B 30 (load 30H in register B)
SUB B (A = A – B)
These set of instructions will reset the sign flag to 0 as 40 – 30 is a positive number.

b) Zero Flag (Z) – After any arithmetical or logical operation if the result is 0 (00)H, the zero flag
becomes set i.e. 1, otherwise it becomes reset i.e. 0.
Example:
MVI A 10 (load 10H in register A)
SUB A (A = A – A)
These set of instructions will set the zero flag to 1 as 10H – 10H is 00H

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Notes By: Raju Poudel (Mechi Multiple Campus)
Flag register
c) Auxiliary Carry Flag (AC) – If intermediate carry is generated this flag is set to 1, otherwise it is reset
to 0.
Example:
MOV A 2B (load 2BH in register A)
MOV B 39 (load 39H in register B)
ADD B (A = A + B)
These set of instructions will set the auxiliary carry flag to 1, as on adding 2B and 39, addition of lower order nibbles B and
9 will generate a carry.

d) Parity Flag (P) – If after any arithmetic or logical operation the result has even parity, an even
number of 1 bits, the parity register becomes set i.e. 1, otherwise it becomes reset.
1-accumulator has even number of 1 bits
0-accumulator has odd parity

e) Carry Flag (CY) – Carry is generated when performing n bit operations and the result is more than n
bits, then this flag becomes set i.e. 1, otherwise it becomes reset i.e. 0.
During subtraction (A-B), if A>B it becomes reset and if (A<B) it becomes set.
Carry flag is also called borrow flag.

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Notes By: Raju Poudel (Mechi Multiple Campus)
8085 Microprocessor Architecture & Functional Units
8) Instruction register and decoder
It is an 8-bit register. When an instruction is fetched from memory then it is stored in the Instruction
register. Instruction decoder decodes the information present in the Instruction register.
9) Timing and control unit
It provides timing and control signal to the microprocessor to perform operations. Following are the
timing and control signals-
Control Signals: READY, RD’, WR’, ALE
Status Signals: S0, S1, IO/M’
DMA Signals: HOLD, HLDA
RESET Signals: RESET IN, RESET OUT
10) Interrupt control
As the name suggests it controls the interrupts during a process. When a microprocessor is executing
a main program and whenever an interrupt occurs, the microprocessor shifts the control from the
main program to process the incoming request. After the request is completed, the control goes back
to the main program.
There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5, TRAP. When
microprocessor receives interrupt signals, it sends an acknowledgement (INTA) to the peripheral
which is requesting for its service.
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Notes By: Raju Poudel (Mechi Multiple Campus)
Maskable and Non-Maskable Interrupts
• Maskable Interrupts are those which can be disabled or ignored by the
microprocessor. INTR, RST 7.5, RST 6.5, RST 5.5 are maskable
interrupts in 8085 microprocessor.
• Non-Maskable Interrupts are those which cannot be disabled or ignored
by microprocessor. TRAP is a non-maskable interrupt.

Priority of Interrupts
When microprocessor receives multiple interrupt requests simultaneously, it
will execute the interrupt service request (ISR) according to the priority of
the interrupts.

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Notes By: Raju Poudel (Mechi Multiple Campus)
8085 Microprocessor Architecture & Functional Units
11) Serial Input/output control
It controls the serial data communication by using these two instructions: SID (Serial
input data) and SOD (Serial output data).

12) Address buffer and address-data buffer

The content stored in the stack pointer and program counter is loaded into the
address buffer and address-data buffer to communicate with the CPU. The memory
and I/O chips are connected to these buses; the CPU can exchange the desired data
with the memory and I/O chips.

13) Address bus and data bus

Data bus carries the data to be stored. It is bidirectional, whereas address bus carries
the location to where it should be stored and it is unidirectional. It is used to transfer
the data & Address I/O devices.
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Notes By: Raju Poudel (Mechi Multiple Campus)
8085 Pin Configuration

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Notes By: Raju Poudel (Mechi Multiple Campus)
8085 Pin Configuration
The pins of a 8085 microprocessor can be classified into seven groups −
1) Address bus
A15-A8, it carries the most significant 8-bits of memory/IO address.
2) Data bus
AD7-AD0, it carries the least significant 8-bit address and data bus.
3) Control and status signals
These signals are used to identify the nature of operation. There are 3 control signal and 3
status signals. Three control signals are RD, WR & ALE.
a) RD − This signal indicates that the selected IO or memory device is to be read and is ready
for accepting data available on the data bus.
b) WR − This signal indicates that the data on the data bus is to be written into a selected
memory or IO location.
c) ALE − It is a positive going pulse generated when a new operation is started by the
microprocessor. When the pulse goes high, it indicates address. When the pulse goes down it
indicates data.
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Notes By: Raju Poudel (Mechi Multiple Campus)
8085 Pin Configuration
Three status signals are IO/M, S0 & S1.
IO/M
This signal is used to differentiate between IO and Memory operations, i.e. when it is high indicates IO
operation and when it is low then it indicates memory operation.
S1 & S0
These signals are used to identify the type of current operation.
4) Power supply
There are 2 power supply signals − VCC & VSS. VCC indicates +5v power supply and VSS indicates
ground signal.
5) Clock signals
There are 3 clock signals, i.e. X1, X2, CLK OUT.
6) Interrupts & externally initiated signals
Interrupts are the signals generated by external devices to request the microprocessor to perform a task.
There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
7) Serial I/O signals
There are 2 serial signals, i.e. SID (Serial input data line) and SOD (Serial output data line) and these
signals are used for serial communication.
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Notes By: Raju Poudel (Mechi Multiple Campus)
Addressing Modes in 8085
• To perform any operation, we have to give the corresponding instructions to the
microprocessor. In each instruction, programmer has to specify 3 things:
1. Operation to be performed.
2. Address of source of data.
3. Address of destination of result.
• The method by which the address of source of data or the address of destination of result is
given in the instruction is called Addressing Modes.
• The term addressing mode refers to the way in which the operand of the instruction is
specified.
• Intel 8085 uses the following addressing modes:
1) Direct Addressing Mode
2) Register Addressing Mode
3) Register Indirect Addressing Mode
4) Immediate Addressing Mode
5) Implicit Addressing Mode
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Notes By: Raju Poudel (Mechi Multiple Campus)
Addressing Modes in 8085
1) Direct Addressing Mode
• In direct addressing mode, the data to be operated is available inside a memory location
and that memory location is directly specified as an operand. The operand is directly
available in the instruction itself.
Example:
LDA 2050 (load the contents of memory location into accumulator A)

2) Register Addressing Mode

• In register addressing mode, the data to be operated is available inside the register(s) and
register(s) is(are) operands. Therefore, the operation is performed within various registers of
the microprocessor.
Examples:
MOV A, B (move the contents of register B to register A)
ADD B (add contents of registers A and B and store the result in register A)
INR A (increment the contents of register A by one)
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Notes By: Raju Poudel (Mechi Multiple Campus)
Addressing Modes in 8085
3) Register Indirect Addressing Mode
In register indirect addressing mode, the data to be operated is available inside a memory location and
that memory location is indirectly specified by a register pair.
Example:
MOV A, M (move the contents of the memory location pointed by the H-L pair to the
accumulator)
4) Immediate Addressing Mode
In immediate addressing mode the source operand is always data. If the data is 8-bit, then the instruction
will be of 2 bytes, if the data is of 16-bit then the instruction will be of 3 bytes.
Example:
MVI B 45 (move the data 45H immediately to register B)
5) Implied/Implicit Addressing Mode
In implied/implicit addressing mode the operand is hidden and the data to be operated is available in the
instruction itself.
Examples:
RRC (rotate accumulator A right by one bit)
RLC (rotate accumulator A left by one bit)
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Notes By: Raju Poudel (Mechi Multiple Campus)
Instruction Set
• An instruction is a binary pattern designed inside a microprocessor to perform a specific
function. The entire group of instructions that a microprocessor supports is called
Instruction Set.
• 8085 has 246 instructions. Each instruction is represented by an 8-bit binary value. These
8-bits of binary value is called Op-Code or Instruction Byte.
• Following are the classification of instructions:
a) Data Transfer Instruction
b) Arithmetic Instructions
c) Logical Instructions
d) Branching Instructions
e) Control Instructions
a) Data Transfer Instruction
• These instructions move data between registers, or between memory and registers. These
instructions copy data from source to destination. While copying, the contents of source are
not modified. Example: MOV, MVI
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Notes By: Raju Poudel (Mechi Multiple Campus)
Instruction Set
b) Arithmetic Instructions
• These instructions perform the operations like addition, subtraction, increment and
decrement.
Example: ADD, SUB, INR, DCR
c) Logical Instructions
• These instructions perform logical operations on data stored in registers and memory. The
logical operations are: AND, OR, XOR, Rotate, Compare and Complement.
Example: ANA, ORA, RAR, RAL, CMP, CMA
d) Branching Instructions
• Branching instructions refer to the act of switching execution to a different instruction
sequence as a result of executing a branch instruction. The three types of branching
instructions are: Jump, Call and Return.
e) Control Instructions
The control instructions control the operation of microprocessor. Examples: HLT, NOP,
EI(Enable Interrupt), DI(Disable Interrupt).
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Notes By: Raju Poudel (Mechi Multiple Campus)
Data Transfer Instructions
Instruction Opcode Addressing Mode Bytes Description

LDA address 3A Direct 3 Transfers contents stored in memory location

to accumulator.
STA address 32 Direct 3 Transfers contents stored in accumulator to
memory address.
MOV A, A 7F Register 1 Transfers the contents from one register to
another
MOV A, B 78 Register 1
MOV A, C 79 Register 1
MOV A, D 7A Register 1
MOV A, E 7B Register 1
MOV A, H 7C Register 1
MOV A, L 7D Register 1
MOV B, A 47 Register 1
MOV B, B 40 Register 1
MOV B, C 41 Register 1
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Notes By: Raju Poudel (Mechi Multiple Campus)
Data Transfer Instructions
Instruction Opcode Addressing Mode Bytes Description

MOV B, D 42 Register 1
MOV B, E 43 Register 1
MOV B, H 44 Register 1
MOV B, L 45 Register 1
MOV C, A 4F Register 1
MOV C, B 48 Register 1
MOV C, C 49 Register 1
MOV C, D 4A Register 1
MOV C, E 4B Register 1
MOV C, H 4C Register 1
MOV C, L 4D Register 1
MOV D, A 57 Register 1
MOV D, B 50 Register 1
MOV D, C 51 Register 1
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Notes By: Raju Poudel (Mechi Multiple Campus)
Data Transfer Instructions
Instruction Opcode Addressing Mode Bytes Description

MOV D, D 52 Register 1
MOV D, E 53 Register 1
MOV D, H 54 Register 1
MOV D, L 55 Register 1
MOV E, A 5F Register 1
MOV E, B 58 Register 1
MOV E, C 59 Register 1
MOV E, D 5A Register 1
MOV E, E 5B Register 1
MOV E, H 5C Register 1
MOV E, L 5D Register 1
MOV H, A 67 Register 1
MOV H, B 60 Register 1
MOV H, C 61 Register 1
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Notes By: Raju Poudel (Mechi Multiple Campus)
Data Transfer Instructions
Instruction Opcode Addressing Mode Bytes Description
MOV H, D 62 Register 1
MOV H, E 63 Register 1
MOV H, H 64 Register 1
MOV H, L 65 Register 1
MOV L, A 6F Register 1
MOV L, B 68 Register 1
MOV L, C 69 Register 1
MOV L, D 6A Register 1
MOV L, E 6B Register 1
MOV L, H 6C Register 1
MOV L, L 6D Register 1
MOV A, M 7E Register Indirect 1 It moves / copies the data stored in memory
location whose address is given in H-L register
pair, to the given register.
MOV B, M 46 Register Indirect 1
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Notes By: Raju Poudel (Mechi Multiple Campus)
Data Transfer Instructions
Instruction Opcode Addressing Mode Bytes Description
MOV C, M 4E Register Indirect 1
MOV D, M 56 Register Indirect 1
MOV E, M 5E Register Indirect 1
MOV H, M 66 Register Indirect 1
MOV L, M 6E Register Indirect 1
MOV M, A 77 Register Indirect 1 This instruction moves / copies the data in the
given register to the memory location
addressed by H-L register pair.
MOV M, B 70 Register Indirect 1
MOV M, C 71 Register Indirect 1
MOV M, D 72 Register Indirect 1
MOV M, E 73 Register Indirect 1
MOV M, H 74 Register Indirect 1
MOV M, L 75 Register Indirect 1

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Notes By: Raju Poudel (Mechi Multiple Campus)
Data Transfer Instructions
Instruction Opcode Addressing Mode Bytes Description
MVI A, data 3E Immediate 2 This instruction transfers the given data
immediately to the register.
MVI B, data 06 Immediate 2
MVI C, data 0E Immediate 2
MVI D, data 16 Immediate 2
MVI E, data 1E Immediate 2
MVI H, data 26 Immediate 2
MVI L, data 2E Immediate 2
IN port-address DB Immediate 2 Load data from input port to accumulator.
(8-bit)
OUT port-address D3 Immediate 2 Transfer data to output port from accumulator.
(8-bit)
LXI H, 16-bit data 21 Immediate 3 Transfer 16-bit data to H-L pair.
LXI D, 16-bit data 11 Immediate Transfer 16-bit data to D-E pair.
LXI B, 16-bit data 01 Immediate 3 Transfer 16-bit data to B-C pair.

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Notes By: Raju Poudel (Mechi Multiple Campus)
Data Transfer Instructions
Instruction Opcode Addressing Mode Bytes Description
XCHG EB Implied/Implicit 1 Exchange contents of H-L pair and D-E pair.
LHLD address 2A Direct 3 Load 16-bit contents of memory address to H-L
pair.
SHLD address 22 Direct 3 Load 16-bit contents of H-L pair to memory
address.
LDAX B 0A Register Indirect 1 This instruction copies the contents of that
memory location into the accumulator. The
contents of either the register pair or the
memory location are not altered.
LDAX D 1A Register Indirect 1
STAX B 02 Register Indirect 1 The contents of the accumulator are copied
into the memory location specified by the
contents of the operand (register pair). The
contents of the accumulator are not altered.
STAX D 12 Register Indirect 1
Total = 84

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Notes By: Raju Poudel (Mechi Multiple Campus)
Arithmetic Instructions
Instruction Opcode Addressing Mode Bytes Description
ADD A 87 Register 1 It adds the content stored in given register with
the accumulator. The result of this addition is
stored in accumulator.
ADD B 80 Register 1
ADD C 81 Register 1
ADD D 82 Register 1
ADD E 83 Register 1
ADD H 84 Register 1
ADD L 85 Register 1
ADD M 86 Register Indirect 1 adds the content of memory location whose
address is given in H-L register pair with the
accumulator and the answer is stored in
accumulator.
ADI data C6 Immediate 2 It immediately adds the given data with the
accumulator and the answer will be stored in
Accumulator.
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Notes By: Raju Poudel (Mechi Multiple Campus)
Arithmetic Instructions
Instruction Opcode Addressing Mode Bytes Description
ADC A C6 Register 1 A=A+A+CY (Add with carry)
ADC B 8F Register 1 A=A+B+CY
ADC C 88 Register 1
ADC D 89 Register 1
ADC E 8B Register 1
ADC H 8C Register 1
ADC L 8D Register 1
ADC M 8E Register Indirect 1
ACI data CE Immediate 2
DAD B 09 Register 1 HL=HL+BC
DAD D 19 Register 1 HL=HL+DE
DAD H 29 Register 1 HL=HL+HL

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Notes By: Raju Poudel (Mechi Multiple Campus)
Arithmetic Instructions
Instruction Opcode Addressing Mode Bytes Description
SUB A 97 Register 1 A=A-A
SUB B 90 Register 1 A=A-B
SUB C 91 Register 1
SUB D 92 Register 1
SUB E 93 Register 1
SUB H 94 Register 1
SUB L 95 Register 1
SUB M 96 Register Indirect 1
SUI data D6 Immediate 2
SBB A 9F Register 1 A=A-A-CY
SBB B 98 Register 1 A=A-B-CY
SBB C 99 Register 1
SBB D 9A Register 1
SBB E 9B Register 1
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Notes By: Raju Poudel (Mechi Multiple Campus)
Arithmetic Instructions
Instruction Opcode Addressing Mode Bytes Description
SBB H 9C Register 1
SBB L 9D Register 1
SBB M 9E Register Indirect 1
SBI data DE Immediate 2
INR A 3C Register 1 A=A+1
INR B 04 Register 1 B=B+1
INR C 0C Register 1
INR D 14 Register 1
INR E 1C Register 1
INR H 24 Register 1
INR L 2C Register 1
INR M 34 Register Indirect 1 M=M+1 (pointed by HL)
INX B 03 Register 1 BC=BC+1
INX D 13 Register 1 DE=DE+1
INX H 23 Register 1 HL=HL+1
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Notes By: Raju Poudel (Mechi Multiple Campus)
Arithmetic Instructions
Instruction Opcode Addressing Mode Bytes Description
DCR A 3D Register 1 A=A-1 Total=65
DCR B 05 Register 1
DCR C 0D Register 1
DCR D 15 Register 1
DCR E 1D Register 1
DCR H 25 Register 1
DCR L 2D Register 1
DCR M 35 Register Indirect 1 M=M-1
DCX B 0B Register 1 BC=BC-1
DCX D 1B Register 1 DE=DE-1
DCX H 2B Register 1 HL=HL-1
RAL 17 Implied/Implicit 1 Rotate accumulator left
RAR 1F Implied/Implicit 1 Rotate accumulator right
RLC 07 Implied/Implicit 1 Rotate accumulator left through carry
RRC 0F Implied/Implicit 1 Rotate accumulator right through carry
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Notes By: Raju Poudel (Mechi Multiple Campus)
Logical Instructions
Instruction Opcode Addressing Mode Bytes Description
ANA A A7 Register 1 A=A AND A
ANA B A0 Register 1 A=A AND B
ANA C A1 Register 1
ANA D A2 Register 1
ANA E A3 Register 1
ANA H A4 Register 1
ANA L A5 Register 1
ANA M A6 Register Indirect 1
ANI data E6 Immediate 2 A=A AND data
ORA A B7 Register 1 A=A OR A
ORA B B0 Register 1 A=A OR B
ORA C B1 Register 1
ORA D B2 Register 1
ORA E B3 Register 1
ORA H B4 Register 1
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Notes By: Raju Poudel (Mechi Multiple Campus)
Logical Instructions
Instruction Opcode Addressing Mode Bytes Description
ORA L B5 Register 1
ORA M B6 Register Indirect 1
ORI data F6 Immediate 2
XRA A AF Register 1 A=A XOR A
XRA B A8 Register 1 A=A XOR B
XRA C A9 Register 1
XRA D AA Register 1
XRA E AB Register 1
XRA H AC Register 1
XRA L AD Register 1
XRA M AE Register Indirect 1
XRI data EE Immediate 2
CMP A BF Register 1 A=A-A (Accumulator remain unchanged)
CMP B B8 Register 1 A=A-B
CMP C B9 Register 1
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Notes By: Raju Poudel (Mechi Multiple Campus)
Logical Instructions
Instruction Opcode Addressing Mode Bytes Description
CMP D BA Register 1
CMP E BB Register 1
CMP H BC Register 1
CMP L BD Register 1
CMP M BE Register Indirect 1
CPI data FE Immediate 2 A=A-data (Acc. Remain unchanged)
CMA 2F Implied/implicit 1 Complement Accumulator contents
CMC 3F Implied/implicit 1 Complement Carry flag
STC 37 Implied/implicit 1 CY=1 (It sets carry flag)

Total=39

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Notes By: Raju Poudel (Mechi Multiple Campus)
Branching Instructions
Instruction Opcode Addressing Mode Bytes Description
JMP address C3 Immediate 3 Unconditional Jump
JC address DA Immediate 3 Jump if CY=1
JNC address D2 Immediate 3 Jump if CY=0
JZ address CA Immediate 3 Jump if Z=1
JNZ address C2 Immediate 3 Jump if Z=0
JM address FA Immediate 3 Jump if S=1
JP address F2 Immediate 3 Jump if S=0
JPE address EA Immediate 3 Jump if P=1
JPO address E2 Immediate 3 Jump if P=0
CALL address CD Immediate 3 Unconditional Call
CC address DC Immediate 3 Call Subroutine if CY=1
CNC address D4 Immediate 3 Call Subroutine if CY=0
CZ address CC Immediate 3 Call Subroutine if Z=1
CNZ address C4 Immediate 3 Call Subroutine if Z=0
CM address FC Immediate 3 Call Subroutine if S=1
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Notes By: Raju Poudel (Mechi Multiple Campus)
Branching Instructions
Instruction Opcode Addressing Mode Bytes Description
CP address F4 Immediate 3 Call Subroutine if S=0
CPE address EC Immediate 3 Call Subroutine if P=1
CPO address FE Immediate 3 Call Subroutine if P=1
RNZ C0 Register Indirect 1 Return to main program if Z=0
RZ C8 Register Indirect 1 Return to main program if Z=1
RNC D0 Register Indirect 1 Return to main program if C=0
RC D8 Register Indirect 1 Return to main program if C=1
RM F8 Register Indirect 1 Return to main program if S=1
RP F0 Register Indirect 1 Return to main program if S=0
RPO E0 Register Indirect 1 Return to main program if P=0
RPE E8 Register Indirect 1 Return to main program if P=1

Total=26

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Notes By: Raju Poudel (Mechi Multiple Campus)
Program Control & Stack Instructions
Instruction Opcode Addressing Mode Bytes Description
PUSH B C5 Register Indirect 1 PUSH data from data from stack on the basis
of address pointed by BC pair.
PUSH D D5 Register Indirect 1
PUSH H E5 Register Indirect 1
POP B C1 Register Indirect 1 POP data from data from stack on the basis of
address pointed by BC pair.
POP D D1 Register Indirect 1
POP H E1 Register Indirect 1

NOP 00 Implied/Implicit 1 No operation is performed

HLT 76 Implied/Implicit 1 Terminate program
DI F3 Implied/Implicit 1
EI 7B Implied/Implicit 1
RIM 20 Implied/Implicit 1 Read interrupt mask (read status of interrupt)
SIM 30 Implied/Implicit 1 Set interrupt mask (used to implement
interrupt)
Total=12 Grand Total=226
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Notes By: Raju Poudel (Mechi Multiple Campus)