JUNE-JULY 2011 VTU

MICROCONTROLLERS
4th SEM B.E. Degree Examination
Question 1

a. Compare the following:

i) Microprocessors and Microcontrollers
Microprocessor Microcontroller
Microprocessor is complete functional Microcontroller is complete functional
CPU i.e. it contains ALU, registers, microcomputer i.e. it contains the circuitry of
stack pointer, program counter, microprocessor and in addition it has built in
instruction decode and control unit and memory (ROM, RAM), I/O circuits and
interrupt processing circuits. peripherals necessary for an application.
Microprocessor instruction sets are data Microcontrollers have instruction sets that are
processing intensive, means powerful related to the control of inputs and outputs,
addressing modes and many instructions means they have many bit handling
to move data between memory and CPU instructions along with byte processing
to handle large volumes of data. instructions.
Microprocessor based products are Microcontroller based products are primarily
primarily designed to interact with designed to interact with machines; once a
humans and are more flexible to design system is designed they are less flexible.
Access times for external memory and Access times for on-chip memory and
I/O devices are more, resulting in a I/O devices are less, resulting in a faster
slower system. system.
Microprocessor based systems require Microcontroller based systems require less
support devices and are usually bulkier, external hardware, reducing PCB size and
costly, less reliable and consume more hence are compact, cheaper, more reliable and
power. consume less power.
Software protection is not possible Software protection is possible because of on-
because of the requirement of external chip code memory.
code memory.

ii) RISC and CISC architecture.

CISC: Complex Instruction Set Computer

In the early days of the computer development, most of the program development work was done
in assembly language because high level languages were not developed. Therefore CPU
designers tried to make instructions that will perform as much work as possible, which in turn
has led to development of instructions with many addressing modes for arithmetic, logical and
data transfer operations. These powerful instructions provide greater flexibility in performing
operations. The CISC architecture require less the number of instructions per program at the cost
of number of cycles per instruction. The 8051 microcontroller is based on CISC architecture, for
example multiply and divide instructions are complex instructions for which operation is
performed in hardware.
The common characteristics of CISC architecture are:

 Complex hardware: complex as well as more addressing modes, variable instruction size.
 Many clock cycles to execute an instruction.
 High code density- small program size.
 Complex data types.

RISC: Reduced Instruction Set Computer

The simple instructions which perform a few operations at a time will provide high performance
because of less hardware requirements for instruction decoder. Thus, instructions require very
less time to execute. The RISC instructions have few addressing modes for supported by all
instructions. It reduces the cycles per instruction at the cost of the number of instructions per
program. The Microchip PIC microcontrollers are based on RISC architecture.

The common characteristics of RISC architecture are:

 Simple hardware: simple and less addressing modes, fix instruction size.
 Single clock cycle execution, uniform instruction format.
 Low code density- Larger program size.
 Few data types in hardware.
 Emphasis is on software: Compiler design is more complex.

iii) Harvard and Von-Neumann architecture

Von Neumann Architecture: It has single memory storage to hold both program instructions
and data i.e. common program and data space. The CPU can either read an instruction or data
from the memory one at a time (or write data to memory) because instructions and data are
accessed using same bus system. The Von Neumann Architecture is named after the
mathematician and computer scientist John Von Neumann. The basic organization of memory in
this architecture is shown in figure 1.7.

Figure 1.7Von Neumann architecture

The advantage of Von Neumann architecture is simple design of microcontroller chip because
only one memory is to be implemented which in turn reduces required hardware. The
disadvantage is slower execution of a program. It is also referred as Princeton architecture as it
was developed at Princeton University. Motorola 68HC11 microcontroller is based on Von
Neumann architecture.

Harvard Architecture: It has physically separate memory storage to hold program instructions
and data i.e. separate program and data space. Since it has separate buses to access program and
data memory, it is possible to access program memory and data memory simultaneously. The
organization of memory and buses in this architecture is shown in figure 1.8.

Figure 1.8 Harvard architecture

The advantage of a Harvard architecture microcontroller is that it is faster for a given circuit
complexity because it offers greater amount of parallelism. The disadvantage is that it requires
more hardware, because two sets of buses and memory blocks are required. MCS 51 (8051
family) and PIC microcontrollers are based on Harvard architecture.

b. Explain the following pins and its function of 8051 microcontrollers:

i) ALE: When connecting the 8051 to external memory, port P0 provides both address and data
i.e. address and data are time multiplexed using P0 to save pins of the microcontroller. The
ALE (Address latch enable, Pin 30) is used for demultiplexing the address and data. ALE
pulse (ALE=1) indicates that the address is present on P0 and is used to enable external latch
(normally 74LS373) which will store (and demultiplex) the address present on P0.

Address/Data demultiplexing using ALE

Port 0 and 2 are collectively used to provide 16 bit address to external memory. P2 provides
upper 8 bits of addresses - A15 to A8 and P0 provides lower 8 bits of addresses - A7 to A0 as
well as 8 bit data D0 to D7. The P0 is time multiplexed to provide address and data bus. These
multiplexed address and data lines must be separated to access memory. Separation of
address and data from P0 is called address/data demultiplexing. Figure 11.3 shows a
simplified memory access timing.
As shown in figure 11.3, the 8051 first provides upper 8 bits of addresses - A15 to A8 on
P2 and lower address bits A7-A0 on P0 and along with this, ALE is made high (ALE=1)
to indicate P0 contains lower address bits. To extract address, P0 should be connected to
a latch chip (typically 74LS373) and ALE should be connected to enable, G (equivalent
to chip select) of the latch as shown in figure 11.4.

Refer topic 11.2 for more details.

ii) : PSEN (Pin 29) is the active low output control signal used to activate
(enable) external ROM/EPROM/EEPROM. Thus, this signal acts as the read
strobe (or output enable) to external program memory.
iii) : EA (Pin 31) is used for selection of on-chip or off-chip ROM, EA=1 will tell
the 8051 to read a program code from on-chip (internal) ROM and EA is
grounded (EA=0) when a program code is totally contained in an external ROM
only.
iv) : Read signal is activated by the microcontroller to read data from external
RAM. It is connected with OE of the RAM chip. It is activated by instructions
like MOVX A,@DPTR or MOVX A, @Riwhich read external RAM. However,
RD may be connected to OE of ROM chip, when ROM is used as data memory.
Question 2

a. Explain the addressing modes of 8051 with examples.

Data addressing modes
1. Immediate addressing
2. Register addressing
3. Direct addressing
4. Indirect addressing
 Register indirect addressing
 Indexed addressing

1. Immediate addressing mode

The data (constant) is specified as a part of instruction in a program memory. The data is
available immediately as a part of instruction itself, therefore immediate addressing is very fast.
However, since the data is fixed, at run time it is not flexible. The instructions using an
immediate operand have an 8 bit or 16 bit number following the op-code. For example,

MOV A, #data // load 8 bit immediate data in to Accumulator

MOV A, #55H // A= 55H

MOV Rn,#data // load 8 bit immediate data into Rn

MOV R3, #0FFH // R3= FFH

MOV DPTR, #data16 // load 16-bit number into DPTR

MOV DPTR, #2000H // DPTR=2000H

2. Register addressing mode

In register addressing mode, the operands are specified by register names. Register A and R0 to
R7 may be named as a part of the instruction mnemonic. The advantage of register addressing
mode is that it occupies only one byte memory, and is fast because only on-chip registers are
accessed i.e. instruction takes only one machine cycle for execution. For example,

MOV A, Rn // copy contents of register Rn to Accumulator

MOV A, R2 // If R2=10H →A=10H

MOV Rn, A // copy contents of Accumulator to register Rn

MOV R1, A // If A=20H →R1=20H

3. Direct addressing mode

The data is accessed directly from the memory address specified as one of the operand i.e. one of
the operand is an 8-bit address for internal RAM location. Internal RAM includes 128 byte of
RAM from (00H-7FH) and any special function register. It is more flexible compared to
immediate and register addressing because the value to be accessed from address may be
variable. These are 2 byte instructions (3 bytes when source and destination are both direct
addresses). The address refers to either byte location or a specific bit in a bit addressable byte.
For example,

MOV A, direct // copy data from (contents of) address direct in to A

MOV A, 10H // If address 10H contains data 50H i.e (10H)=50H→ A=50H

MOV direct, A // copy data from A to address direct

MOV 10H, A // If A=44H→ (10H)= 44H

MOV Rn, direct // copy data from address direct in to register Rn

MOV R5, 80H // If (80H)= FFH→R5= FFH

MOV direct, Rn // copy data from Rn to address direct

MOV 50H, R3 // R3=10H →(50H)= 10H

MOV direct, #data // load 8 bit immediate data in to address direct

MOV 0A0H, #20H // (A0H) = 20H

MOV direct1, direct2 // copy data from address direct2 to address direct1
MOV 50H, 83H // If (83H)=10H→ (50H)=10H

4. Indirect addressing mode

The data is specified indirectly in an instruction i.e. address of the data (rather than data itself) is
specified as one of the operand. Here, the register holds the address that contains the data i.e. the
number in the register is treated as an pointer to address. Indirect addressing mode is the most
flexible and useful in array operations. There are two types of indirect addressing in the 8051

Register indirect addressing mode: The register indirect addressing uses only register R0 or R1
to hold address of the data in internal RAM, these two registers are also referred to as pointer
registers or simply pointers. The symbol @ is used along with R0 or R1 to indicate indirect
addressing. For example,
MOV @Ri, #data // load constant value in to address contained in Ri
MOV @R0, #30H // If R0=40H, → (40H)=30H

MOV @Ri, direct // copy data form address direct to address Ri

MOV @R1, 10H // If (10H)=50H, R1=15H→ (15H)=50H

MOV direct, @Ri // copy data from address in Ri to address direct

MOV 10H, @R1 // If R1=50H, (50H)=15H→ (10H)=15H
MOV @Ri, A // copy data from A to address in Ri
MOV @R0, A // If A=50H, R0=15H→ (15H)=50H

MOV A, @Ri // copy data from address in Ri to A

MOV A, @R1 // If R1=50H, (50H)=15H→ A=15H

Indexed addressing mode: Two registers are used to form the address of the data. The contents
of either DPTR or PC are used as a base address and the A is used as index (or offset) address.
The final address is formed by adding these two registers. It results in a forward reference of 0 to
255 bytes from the base address. They are used to access only program memory (internal as well
as external)
Indexed addressing is used to access data tables (lookup tables) from the program memory and
implementing jump tables. They are also suitable for multidimensional array operations.
The instructions are:
MOVC A, @A+PC // copy data (or code) byte from program memory address formed by
//addition of contents of A and PC into A

MOVC A, @A+DPTR// copy data (or code) byte from program memory address formed by
// addition of contents of A and DPTR into A

b. Explain the following instructions of 8051 with examples for each

instruction:
i) SUBB A, direct:
SUBB A, direct // subtract contents of address direct and carry from A, store result in A
// i.e. A= A– (direct) – C
SUBB A, 40H // A= A – (40H) –C, If A=10H, (40H) =15H, C=0 →
// A=10H–15H–0=FBH, C=1

ii) PUSH direct

Push onto the stack. The Stack Pointer is first incremented by one. The contents specified direct
address then copied onto the stack (internal RAM address pointed by the SP).
Example: Assume B=20H, A=15H and SP=45H before execution of following instructions,
PUSH F0 // SP=46H, (46H)=(F0H)=20H
PUSH E0 // SP=47H, (47H)=(E0H)=15H

iii) MOVC A,@A+DPTR

Transfer the content of address formed by Content of Accumulator plus DPTR of program
memory into the Accumulator.

MOV DPTR,#0100H
MOVC A,@A+DPTR

The operation of instruction MOVC A, @A+DPTR is shown in figure.

The following program will find square of number present in A. The result will be available in A
after execution of MOVC A, @A+DPTR instruction. The square is found by accessing
corresponding entry from look up table defined in program memory

ORG 0000H
MOV DPTR, #1000H // load address of lookup table in DPTR
MOV A, #02H // value for which square is to be found
MOVC A, @A+DPTR // access look up table, place result in A
…
ORG 1000H // define lookup table at ROM address 0100H
DB 0H, 1H, 4H, 9H, 10H,19H,24H,31H,40H,51H,64H

c. Examine the following code and analyze the result with flag register
content:
MOV A,#+96
MOV R1,#+70
ADD A,R1

The operation performed by above statements is as shown below.

(+96d) = 0110 0000B = 60H

+ (+70d) = 0100 0110B = 46H
+166d (expected) 1010 0110B A6H
= –90d (actual result)
Here the expected result is +166, which exceeds maximum positive number (+127) that an 8 bit
number can represent (or an 8 bit register can hold). So we get an incorrect result. This is
indicated by OV=1, because there is carry out from bit 6 but not from bit 7.

The reason for getting erroneous result may also be understood this way: Since both the original
numbers were positive and therefore the result should have been positive, but we got it as
negative because of the excessive magnitude of the result (overflow) has modified (inverted) the
sign bit.
These sets of instruction will add two numbers stored in A and R1.

Parity-0 Overflow-1 Register Bank-0 Auxiliary Carry-0 Carry-0

Question 3

a. Classify the CALL instruction in 8051. Explain each one.

LCALL (long call)
- 3-byte instruction
-First byte is the opcode
-Second and third bytes are used for address of target subroutine
–Subroutine can be located anywhere within 64K byte address space
-The format is,

LJMP add16 // jump to direct destination address add16

ACALL (absolute call)

- 2-byte instruction
- AJMP instruction logically divides entire program memory in to 32 pages of 2K Bytes each.
-11 bits are used for address within 2K-byte rangeThe format is,

AJMP add11 // jump to absolute destination address add11

A call (ACALL or LCALL) causes a jump to address where called subroutine is located. After
completing a subroutine the main program (calling program) execution should resume at
instruction next to the call instruction. The stack automatically keeps track of where
microcontroller is supposed to return after executing the subroutine. When we call a subroutine,
address of the instruction next to the call instruction is automatically saved on to the stack, this
address is called return address. At the end of a subroutine the return (RET) instruction will load
return address from the stack to PC to resume the execution of the calling program. The stack
pointer (SP) register is used to access the stack. Stack pointer always points to top of the stack
i.e. last memory address accessed.

The process of calling a subroutine and returning form it to resume the operation of calling
program using ACALL instruction is described in following steps.
  ACALL instruction will save the return address (PC) on the stack using two push
operations, lower byte at address SP+1, and higher byte at SP+2. (Stack pointer is
automatically incremented before pushing each byte). Address of subroutine is placed in
the PC.
 Subroutine is completed
 A RET instruction at the end of the subroutine will retrieve the return address to the PC
from the stack using two pop operations. (Stack pointer is automatically decremented
after each pop operation).
 Calling (main) program resumes it operation from the next instruction after ACALL.

The operation of ACALL instruction is illustrated in figure 7.4.

after SP+2 before

12H(PCH) RET
ACALL
main program SP+1 47H(PCL)
address instructions
before SP after
ACALL RET
Stack

current
instruction 1245 H ACALL XYZ
1. save PC
PC 1247 H (return address) subroutine XYZ
on the stack
2. jump to
subroutine
XYZ

resume execution at retrieve return

RET address
next instruction
PC= 1247H

Figure 7.4 Operation of ACALL instruction

The operation of LCALL is exactly same as ACALL instruction. The only difference it has is
that it can call subroutine anywhere in the entire program space of 64Kbytes, while ACALL can
call subroutine within a page of 2Kbytes in which instruction following ACALL is located.
ACALL is a 2 byte instruction, while LCALL is a 3 byte instruction. The way 11 bit address is
specified for ACALL instruction is exactly similar to the AJMP instruction.

b. What are the step executed by the 8051 microcontroller when the following
instructions is executed:
i) RET: It is used to return to main program from subroutine which was called by ACALL or
LCALL instruction. It pops (retrieves) two bytes from top of stack (return address) in to PC
and SP is decremented by two. The program execution continues at the return address,
usually the instruction immediately following an ACALL or LCALL.
PCH=(SP);
SP=SP-1;
PCL=(SP);
SP=SP-1

ii) AJMP addr-11: The instruction for absolute jump is AJMP and its format is,

AJMP add11 // jump to absolute destination address add11

AJMP instruction logically divides entire program memory in to 32 pages of 2K Bytes each.

It transfers the program execution to specified address within 2Kbyte page with respect to PC.
The new value of PC (destination address) is obtained by combining the five bits of the PC (PC15
through PC11), opcode bits 7 through 5, and the second byte of the instruction. Since three bits of
opcode are decided by A10 toA8 of the destination address, this instruction has 8 opcodes.

PC10-0= addr11

Refer topic 7.1 (Absolute jump subtopic) for more details.

c. Write an ALP to add ‘N’ 8-bit numbers available from memory location START.
Display the result at Port 0 and Port 1.

ORG 0000H
CLR C
CLR A
MOV R4, #00H // clear R4H to store upper byte of result
MOV R0, # START // load address of label START in the R0
MOV R2, # N // N numbers
NEXT: ADD A, @R0 // add array elements with A
JC AHEAD
SJMP SKIP
AHEAD: INC R4 // if C=1, increase upper byte of result
SKIP: INC R0 // next array element
DJNZ R2, NEXT // check all numbers are added
 MOV P0, A // display lower byte of result at P0
MOV P1, R4 // display lower upper of result at P1
HERE: SJMP HERE
END

Question 4

a. Explain different data types in the 8051 C.

Different data types in the 8051 C are shown in the following table followed
by brief description.
Data type Bits Bytes Range of values
Standard C data types
signed char 8 1 -128 to +127
unsigned 8 1 0 to 255
Enum 8 1 -128 to +127
16 2 -32768 to 32767
signed short 16 2 -32768 to 32767
unsigned 16 2 0 to 65535
signed int 16 2 -32768 to 32767
unsigned 16 2 0 to 65535
signed long 32 4 -2147483648 to 2147483647
unsigned 32 4 0 to 4294967295
Float 32 4 +1.175494E-38 to + 3.402823E+38
Additional data types for the 8051
Bit 1 - 0 or 1 (bit addressable RAM only)
Sbit 1 - 0 or 1 (Bit addressable SFR only)
Sfr 8 1 0 to 255 (SFRs)
sfr16 16 2 0 to 65535

bit

The ‘bit’ data type is used to define a one bit variable. It is defined and declared as follows:
bit variable_name ; or
bit variable_name = value;
Where variable_name is a name of the bit variable and value is value assigned to the bit. For
example,
bit output; // declare one bit variable output
bit switch_flag = 0; // assign value 0 to a variable switch_flag
bit LED = input; // assign value of bit variable input to variable LED
All bit variables are stored in a bit addressable area of the 8051 i.e. from 20H- 2FH byte
addresses in internal RAM. Since this area has only 16 bytes, a maximum of 128 bit variables
may be declared within any one scope.

The limitations apply to the bit variables are that they cannot be declared as a pointers and array
of type bits. For example,
bit *addr;
bit array [10]; are invalid declarations

sfr
The ‘sfr’ data type defines a special function register (SFR) and assigns the name to it. It is
declared as follows:

sfr variable_name = address;

Wherevariable_name is the name of the SFR and address is the address of the SFR. For
example,

sfr P0 = 0x80; // Port 0 (address 80H) is defined as P0 and will be accessed using
// name P0
sfr P1 = 0x90; // Port 1 (address 90H) is defined as P1 and will be accessed using
// name P1
sfr TMOD = 0x89; // Timer Mode register (address 89H) is defined as TMOD and
// will be accessed using name TMOD
sfr IE = 0xA8; // Interrupt enable register (address A8H) is defined as IE and will
// be accessed using name IE

Note that any symbolic name may be used in sfr declaration. The variables declared as sfr are
assigned values similar to any other C variable, for example,
P0 = 0x00; // 0x00 is written in to P0
TMOD= 0x02; // 0x02 is written in to TMOD register

sbit

The ‘sbit’ data type defines a bit within a special function register (SFR).It should be noted that
bit can be only within bit addressable SFRs. It is defined and declared as follows:
1. sbit variable_name = sfr_name ^ bit_position; or
2. sbit variable_name = sfr_address ^ bit_position; or
3. sbit variable_name = sbit_address;
Where sfr_name is a name of SFR already defined, sfr_address is address of a SFR, bit_position
is position of the bit within the register and sbit_address is the bit address. For example,
1. sfr PSW = 0xD0; //define PSW
sbit P = PSW^0; //parity flag (bit 0 of PSW) is now accessed using name P
sbit AC = PSW^6; //auxiliary flag (bit 6 of PSW) is accessed using name AC
 2. sbit P = 0xD0^0; //parity flag is bit 0 of PSW, accessed using name P
sbit AC = 0xD0^6; //auxiliary flag is bit 6, accessed using name AC

3. sbit P = 0xD0; //parity flag P has bit address D0H

sbit AC = 0xD6; //auxiliary flag AC bit address D6H

b. Write an 8051 C program to get a byte of data from P1, wait ½ second and
then send it to p2.

#include<reg51.h>
void DELAY(void);

void main ()
{
unsigned char i;
P1=0xFF; // configure P1 as input

while (1) // repeat the operation continuously

{
i= P1; // read a byte from P1
DELAY (); // wait for ½ second
P2=i; // send the contents of P1 to P2
}

void DELAY(void) // function to generate delay

{
unsigned int i;
for(i=0; i<=65535; i++);

Note: The delay generated by function DELAY depends upon the crystal
frequency as well as compiler used. To get exact delay of 0.5 seconds, we can
use timers as shown below.
Delay of 50 ms is generated using Timer 0 and it is repeated 10 times using a loop.
Timer works with frequency 12MHz/12 =1MHz and time period is 1/1MHz = 1 µs.
To generate delay of 50 ms, timer clock cycles required is 50 ms/1 µs=50000 cycles.
Therefore, count to be loaded is 65536-50000= 15536 = 3CB0 H
TH0= 3CH and TL0=0B0H.
 void DELAY ()
{
unsigned char i;
for (i=0; i<10; i++) // repeat loop 10 times
// 50 ms delay is repeated 10 times to
// generate delay of 0.5s
{
TMOD = 0x01; // configure timer 0 as a timer in mode 1
TL0 = 0xB0; // load count in timer registers TH0-TL0
TH0 = 0x3C;
TR0 = 1; // start timer
while (TF0!=1); // wait for TF0 to roll over
TR0 = 0; // stop timer 0
TF0 = 0; // clear TF0 flag

}
}

c. Write an 8051 C program to convert ASCII digits of any two values to

packed BCD and display it on Port 1.
Assume that two ASCII digits are ‘3’ and ‘5’.

We need to mask the upper nibbles of both ASCII numbers to remove 3 from upper
nibbles and then both unpacked digits are packed.
ORG 0000H
MOV A, # ‘3’ // ASCII number corresponding to higher nibble
// equivalent to ‘MOV A, # 33H
ANL A, #0FH // mask upper nibble
SWAP A
MOV R1, A
MOV A, # ‘5’ // ASCII number corresponding to lower nibble
ANL A, #0FH // mask upper nibble
ORL A, R1 // pack both nibbles.
MOV P1, A // display packed BCD on port 1
HERE: SJMP HERE
END
The result is, P1=A=35H
PART-B

Question 5

a. Explain TMOD and TCON SFR registers of 8051 timers.

TMOD:
TMOD is 8 bit special function register dedicated to both timers. The lower 4 bits configure the
timer 0 and upper 4 bits configure the timer 1. The bit assignment of the TMOD is shown in
following Table.
Table: TMOD register

Timer 1 Timer 0
GATE C/T M1 M0 GATE C/T M1 M0
MSB LSB

Bit Symbol Description

7/3 Gate Start/stop control using hardware or software. When Gate=0, start/stop of
timer is controlled only by TR1/0 bits; While Gate=1, it is controlled by
TR 1/0 as well as signal on INT1/0 pin
6/2 C/T C/T =0 configures timer as a interval timer (or time delay generator),
C/T=1 will configure timer as event counter
5/1 M1 Mode select bit 1
4/0 M0 Mode select bit 0
M1 M0
0 0 Mode 0;13 bit timer
0 1 Mode 1; 16 bit timer/counter
1 0 Mode 2; 8 bit auto reload
1 1 Mode 3; split timer mode, TL0 as 8 bit timer/counter and
TH0 as 8 bit timer controlled by control bits of timer 0 and
timer 1 respectively. Timer 1 operation timer/counter
stopped.
TCON:
Bit assignment of TCON register is shown and explained in following table.

Table: TCON register

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

MSB LSB

Bit Symbol Description

7 ( TCON.7) TF1 Timer 1 overflow flag; Set to 1(by hardware) when timer 1
overflows; Cleared to 0 automatically when controller vectors to
interrupt service routine at address 001BH.
6 ( TCON.6) TR1 Timer 1 run control bit; set to 1 by a program to start
timer/counter 1; Cleared to 0 to stop timer/counter 1.
5 ( TCON.5) TF0 Timer 0 overflow flag; Set to1 (by hardware) when timer 0
overflows; Cleared to 0 automatically when controller vectors to
interrupt service routine at address 000BH
4 ( TCON.4) TR0 Timer 0 run control bit; Set to 1 by a program to start
timer/counter 0; Cleared to 0 to stop timer/counter 0.
3 ( TCON.3) IE1 External interrupt 1 edge flag; Set by hardware when external
interrupt is detected on INT1 pin; Cleared by hardware when
controller vectors to interrupt service routine at address 0013H
only when interrupt is configured as an edge triggered interrupt
(see IT1 bit below)
2 ( TCON.2) IT1 External Interrupt 1 signal type control bit; set to 1 by a program
to configure interrupt 1 as a edge triggered (falling edge); cleared
to 0 to configure it as level triggered (low level)
1 ( TCON.1) IE0 External interrupt 0 edge flag; Set by hardware when external
interrupt is detected on INT0 pin; Cleared by hardware when
controller vectors to interrupt service routine at address 0003H
only when interrupt is configured as an edge triggered interrupt
(see IT0 bit below)
0 ( TCON.0) IT0 External Interrupt 0 signal type control bit; set to 1 by a program
to configure interrupt 0 as a edge triggered (falling edge); cleared
to 0 to configure it as level triggered (low level)

b. Write an ALP or C program to generate a frequency of 100 Hz square

wave, using timer 0 in mode 1. Assume crystal frequency 11.0592 MHz.

The period of square wave is 1/100Hz = 10ms.

Square wave have duty cycle of 50%, so, ON period = OFF period = Total Period/2
= 10000µs/2 = 5000µs
We should generate the time delay of 5000µs and toggle pin P2.0 every 5000µs to generate
square wave of 100KHz.

The frequency of timer clock = 11.0592MHz/12= 0.9215MHz

∴ The time period of timer clock = 1/0.9215MHz = 1.085µs (time period of one machine cycle)
also, Timer register will be incremented by one every 1.085µs)

Number of timer clock pulses (of 1.085uS) required to make 5000 µs= 5000/1.085= 4608
The Count to be loaded in to TH and TL=65536 – 4608(or 65535– 4608+1) = 60928=EE00H
∴ TH0=0EEH and TL0=00H.

# include <reg51.h>
sbit square_bit = P2 ^ 0; // define P2.0 pin as square_bit
void main ( )
{
square_bit = 1; // set 2.0 pin to logic ‘1’ (high portion of // square //wave
TMOD = 0x01; // Timer 1 configured as timer and in
// mode 1
for (;;) // repeat the following statements forever
// to generate square wave
{
TH0 = 0xEE; // load count in Timer registers TH1-TL1
TL0 = 0x00; // 100H so TH1 TL1
TR0=1; // start timer1
while (TF0 !=1); // wait until TF1 overflows
TR0=0; // stop timer
TF0=0; // clear timer overflow flag.
square_bit=~ square_bit; // toggle p2.0 pin to get square
//wave
}
}

Question 6

a. What is baud rate? Which timer of the 8051 is used to set the baud rate?
The term Baud rate is defined as rate at which data is being transferred serially i.e. rate at which
signal transitions occurs (or frequency of signal transitions).
For example, if signal makes transition every 5ms, the baud rate is (1/5ms) =200Baud.
Rate of data transfer is also measured in bits/s. It is number of bits transmitted per second. The
terms baud rate and bits/s are not always same. For example, if only one bit is coded per signal
transition, then bits/sec and baud rate are same (like BPSK) and when more than one bit is coded
per signal transition, then both are different. Assume 2 data bits are encoded in single signal
transition (like QPSK) and signal is changing every 5ms, so baud rate is 200 Baud as explained
above but bits/s is 2 x 200=400 Bits/s. Hence the relation between bits/s and baud rate is given
as:
Bits/s= Number of data bits encoded per signal transition x Baud rate.
The baud rates 300, 600, 1200, 2400, 4800, 9600, 19200 are used most commonly.

Timer 1 is used to set the baud rate. (most common mode is mode 2 for baud rate generation)

b. Explain SCON register with its bit pattern.

Serial port control (SCON) register

Bit assignment and description of SCON register is given in the following Table.

Table : SCON register

SM0 SM1 SM2 REN TB8 RB8 TI RI

MSB LSB

Bit Symbol Description

7 SM0
Serial Port Mode see table below *
6 SM1
5 Enables multiprocessor I/O in mode 2 and 3. When set to 1, an
interrupt is generated if bit 9 of received data is 1, no interrupt is
SM2
generated if bit 9 is 0. If Set to 1 for mode 1, no interrupt will be
generated unless a valid stop bit is received. Clear to 0 for mode 0.
4 REN Receive enable if REN=1
3 TB8 9th data bit to send in 9 bit mode in Modes 2 and 3
2 9th data bit received in modes 2 & 3. In mode 1, if SM2 = 0, RB8 is
RB8
the stop bit that was received. In mode0, RB8 is not used.
1 Transmit Interrupt flag (Transmitter empty Interrupt Flag) – sending
finished. Set by hardware at the end of the 8th bit time in mode 0, or
TI at the beginning of the stop bit in the other modes. It's a signal to the
microcontroller that the line is available to transmit a new byte.
Must be cleared by software.
0 Receive Interrupt Flag – new byte received. Set by hardware at the
end of the 8th bit time in mode 0, or halfway through the stop bit
RI
time in the other modes. It signals that a byte is received and should
be read quickly prior to being replaced by a new data. Must be
 cleared by software.

Serial port mode is selected by the SM0 and SM1 bits:

SM0 SM1 Mode Description Baud Rate

0 0 0 8-bit shift 1/12 the crystal frequency
register
0 1 1 8-bit UART Determined by the timer 1
1 0 2 9-bit UART 1/32 the crystal frequency (1/64 the crystal frequency)
1 1 3 9-bit UART Determined by the timer 1

c. Write an 8051 program to send the date message “MORNING” of length

seven characters at a baud rate of 4800, b-bit data, 1 stop bit serially.
#include<reg51.h>
void main (void)
{
unsigned char ch;
TMOD = 0x20; // timer 1configured in mode 2
TH1 = 0xFA; // set 4800bps baud rate
SCON = 0x50; // 8-bit data, 1 stop bit, REN enabled
TR1 = 1; // start timer 1 to generate clock (at baud
// rate)
while (1) // repeat the task forever
{
SBUF = ‘M’; // place character value in buffer
while (TI==0); // wait until byte is transmitted
TI = 0; // clear TI before sending next byte
SBUF = ‘O’; // place character value in buffer
while (TI==0); // wait until byte is transmitted
TI = 0; // clear TI before sending next byte
SBUF = ‘R’; // place character value in buffer
while (TI==0); // wait until byte is transmitted
TI = 0; // clear TI before sending next byte

SBUF = N; // place character value in buffer

while (TI==0); // wait until byte is transmitted
TI = 0; // clear TI before sending next byte

SBUF = ‘I’; // place character value in buffer

while (TI==0); // wait until byte is transmitted
TI = 0; // clear TI before sending next byte
 SBUF = ‘G’; // place character value in buffer
while (TI==0); // wait until byte is transmitted
TI = 0; // clear TI before sending next byte

}
}

Question 7

a. Compare polling interrupts. What are the steps microcontrollers performs

upon activation of an interrupt.
There are two ways to determine whether peripheral devices require attention or services of the
microcontroller. The first approach, based on software, requires microcontroller to continuously
monitor the status of a peripheral device and provides services when device requires service.
This method is known as polling. This method is useful when processor has to do only one task
(or a few) and response time is not an issue.
The problems with polling method are:
1) It wastes microcontroller time by monitoring the device continuously.
2) Priorities cannot be assigned to devices because status can be monitored one by one for
all devices irrespective of their priority and importance.
3) It makes system slower because high priority device have to wait for its turn when lower
priority devices being polled and serviced.
To overcome all these problems, second method which is based on the hardware is useful. This
method is referred as interrupt method. In this method, whenever any device requires attention or
services of the microcontroller, it will send interrupt signal to the microcontroller, and in
response to that the microcontroller will stop current activity and serve the device and then after,
resumes the regular activity. This way interrupt method provides advantages like:
1) The time of microcontroller is efficiently used as there is no wastage of time in
continuous and unnecessary monitoring.
2) Priorities can be given to different devices as per their importance and higher priority
device may be programmed to interrupt lower priority devices.
3) It makes system faster because more important activities are handled immediately.
4) More number of devices can be served (though, only one device at a time)
5) System can be programmed to ignore any or all devices while handling critical tasks.
To allow 8051 to respond to any of the interrupts, they must be enabled by setting interrupt
enable flag(s) to 1. The interrupt may be generated by external or internal event. When interrupt
is generated a microcontroller will take the following sequence of steps:
1) It completes execution of current instruction.
 2) Saves (pushes) the return address (PC) on to the stack; low byte (PCL) first.
3) The current status of all the interrupt enable bits (in IE register) are stored internally, and
interrupts of same or lower priority are disabled (blocked).
4) The PC is loaded with the vector address of the corresponding interrupt source.
5) The interrupt service routine is executed *.
6) At the end of the ISR, the RETI instruction will retrieve the saved status of interrupt
enable bits, thus, enabling the same and lower priority interrupts again, and retrieves the
return address from stack into PC and continue to execute from the place it was
interrupted.

b. How the interrupt in 8051 is classified? Explain each interrupt.

Interrupts are classified as external (asynchronous) and internal (synchronous) Interrupts based
on source of the interrupt.
Hardware interrupts and Software interrupts.
External interrupts:
Interrupt source Interrupt Interrupt Interrupt
vector type flag clearing
External interrupt 0 (INT0) 0003H External Auto*
External interrupt 1 (INT1) 0013H External Auto*

Internal Interrupts:
Interrupt source Interrupt Interrupt Interrupt
vector type flag clearing
Timer 0 interrupt (TF0) 000BH Internal Auto
Timer 1 interrupt (TF1) 001BH Internal Auto
Serial port interrupt (TI or RI) 0023H Internal By program

When any interrupt is generated (or asserted), it forces the microcontroller to jump to fixed
address in vector table. For example when INT0 is asserted, microcontroller will automatically
jump to memory address 0003H, similarly for timer1 interrupt, it will jump to address 001BH in
interrupt vector table. Since program execution is transferred to fixed location corresponding to
each interrupt source, the interrupts in the 8051 are also referred as vectored interrupts. The
interrupt vector table of the 8051 is shown in the following figure.
TIMER INTERRUPTS
If timer interrupts are enabled in IE register and timer register overflows, then corresponding
timer overflow flag (TF0 or TF1) will set to 1, and microcontroller will jump to the
corresponding interrupt vector table (000B for timer 0 and 001B for timer 1) and clear the TF0
(or TF1) flag automatically. (Refer topic 16.5 for further details)

EXTERNAL INTERRUPTS
The pins INT0 (P3.2, pin 12) and INT1 (P3.3, pin 13) are used as an external interrupt input pins.
When these pins are activated (made low), the 8051 is interrupted and jumps to interrupt vector
table of corresponding interrupt. The external interrupts can be configured to be either level
triggered or transition (edge) triggered interrupts. (Refer topic 16.6 for further details)

SERIAL PORT INTERRUPTS

The 8051 serial port has transmitter and receiver subsystems. Serial port interrupt is generated
when either transmit interrupt flag (TI) or receive interrupt flag (RI) is set to 1. The transmit and
receive interrupts are combined (ORed) to generate a common serial port interrupt as shown in
figure 16.4. The transmit interrupt is generated when transmission of byte written to SBUF
register is completed i.e. when stop bit is being transferred. It indicates that transmit buffer is
empty and next byte can be placed in it to begin the next byte transmission, because of this TI is
also known as transmitter empty interrupt flag. The receive interrupt is generated when a byte or
character is received in receive buffer i.e. when stop bit is being received. It indicates that a data
byte is received and should be read quickly prior to being replaced by a new data byte. (Refer
topic 16.7 for further details)

c. Write a program using interrupts to get data from P1 and send it to P2

while Timer 1 is turning ON and OFF the LED connected to P0.4 every
second.
Assume crystal frequency is 12 MHz.

Delay of 50 ms is generated using Timer 1 and it is repeated 20 times using a loop in Interrupt
service routine. The LED will be toggled every 20th time the program enters in to ISR (50ms
x20=1s)
Timer works with frequency 12MHz/12 =1MHz and time period is 1/1MHz = 1 µs.
To generate delay of 50 ms, timer clock cycles required is 50 ms/1 µs=50000 cycles.
Therefore, count to be loaded is 65536-50000= 15536 = 3CB0 H
TH1= 3CH and TL1=0B0H.

#include <reg51.h>
sbit SWAVE = P0^4;
void timer1 (void) interrupt 3 // ISR for timer 1
{ TF1=0 ; // clear timer overflow flag
TR1=0; // stop timer
i++;
if (i>20) // If ISR is entered 20 times, the delay of 1s
// is over, therefore toggle the LED
{
SWAVE = ~SWAVE; // toggle pin P0. 4 to ON-OFF LED
i=0;
}
TL1 = 0xB0; // load count in timer registers TH1-TL1
TH1 = 0x3C;
TR1=1 ; // start timer 1

}
 void main (void)
{ char i=0;
P1=0xFF // configure P1 as an input
TMOD = 0x10; // configure timer 1 as a timer in mode 1
TL1 = 0xB0; // load count in timer registers TH1-TL1
TH1 = 0x3C;
IE=0x88; // enable interrupt for timer 1
TR1=1; // start timer 1 to generate delay
SWAVE=1 // turn ON LED
while (1) // perform following task forever
{
P2=P1 // read status of P1 and send to P2
}
}

Question 8

a. Interface ADC0804 to 8051 and write a program to read analog data and
display the converted data at Port 2.

ORG 0000H
SETB P3.0 // configure P1.0 as input for connecting INTR
MOV P1, #0FFH // configure P2 as input for reading data
CLR P3.1 // make CS low
NEXT: CLR P3.2 // make WR low

SETB P1.2 // WR =1, low to high pulse for starting ADC

HERE: JB P3.0, HERE // wait until end of conversion
CLR P3.3 // make RD low to read conversion result
MOV A, P1 // read data from ADC
MOV P2, A // send sample at P2 port
SJMP $

b. Show the interfacing of a stepper motor to 8051 and write a program to

rotate stepper motor 5 steps in clockwise direction and 10 steps in anti-
clockwise direction with a delay between each step.

ORG 0000H
MOV A, #0CCH // full step sequence, the first entry in table is 1011= C.
// Here CC is used for continuous rotation.
MOV R0,#05
REPEAT: MOV P2, A // send sequence to motor
RR A // next step of sequence to rotate in clock wise rotation.
LCALL DELAY // wait before going to next step
DJNZ R0, REPEAT // next step

MOV R0,#10
REPEAT: MOV P2, A // send sequence to motor
RL A // next step of sequence to rotate in ANTI-clock
//wise rotation.
LCALL DELAY // wait before going to next step
DJNZ R0, REPEAT // next step

DELAY: MOV R1, # 60H // delay, it can be varied to change speed of rotation
THERE: MOV R2, #0FFH
HERE: DJNZ R2, HERE
DJNZ R1, THERE
RET
END