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GPS Interface for PTP Master Implementation

The document discusses two proposals for implementing a PTP master in an AFDX Switch using a GPS clock system. Proposal 1 involves interfacing a GPS chipset with a CPU on a MOECN card, which may lead to timing inaccuracies due to delays in packet processing. Proposal 2 suggests direct interfacing of the GPS chipset with an FPGA, allowing for precise timing calculations and the ability to test with multiple Ethernet ports, with a provision for both schemes in hardware for feasibility assessment.

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vijaykumar ponugoti
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6 views2 pages

GPS Interface for PTP Master Implementation

The document discusses two proposals for implementing a PTP master in an AFDX Switch using a GPS clock system. Proposal 1 involves interfacing a GPS chipset with a CPU on a MOECN card, which may lead to timing inaccuracies due to delays in packet processing. Proposal 2 suggests direct interfacing of the GPS chipset with an FPGA, allowing for precise timing calculations and the ability to test with multiple Ethernet ports, with a provision for both schemes in hardware for feasibility assessment.

Uploaded by

vijaykumar ponugoti
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as ODT, PDF, TXT or read online on Scribd

To implement the PTP master in AFDX Switch, a refercence clock system is required.

For that
reason we are interfacing a GPS clock.

Proposal 1:

MOECN card has a UART interface with which we can interface GPS chipset on FPGA. GPS
chipset will send clock details every one second(based on configuration) to the CPU on MOECN
card. In this scheme, the PTP master protocol need to be implemented on CPU(PIC controller). And
the delay will be added to the packet as the packet traverse from CPU to the End system as shown
in fig(Purple color arrow indications). And also it is difficult to copy the PTP timer registers data in
Ethernet Phys to CPU for delay calulations. So the timing may not be so precisely calucaleted in
this scheme.
Proposal 2:

In this scheme, we will interface GPS chipset directly to FPGA. GPS chipset will send clock details
every one second(based on configuration) to the FPGA. In this scheme, the PTP master protocol
and GPS chipset driver need to be implemented on FPGA. We can directly read the PTP timer
registers data in Ethernet Phys as soon as we get a interrupt from PHY (PHY interrupts when
detects a PTP packet). So the timing can be precisely calucaleted in this scheme. In this scheme we
will be having 8 Ethernet ports for testing.

Note: The plan is to give provision for both the schemes in hardware so that based on feasibility we
can implement PTP master.

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