Innovus Place & Route User Guide
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fesapek333Innovus Place & Route User Guide
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Powered by AIIn Innovus, several techniques are employed to minimize the impact of interconnect parasitics, which can degrade performance and timing. These include the strategic use of routing layers, where metals such as M1, M3, and M5 favor horizontal routing while M2, M4, and M6 are preferred for vertical paths. This preference helps reduce parasitic capacitance and resistance by aligning conductive paths with the lowest resistance routes . Additionally, the software supports the incorporation of upper metal layers for power distribution like M7, which further reduce resistance . MMMC configurations also account for interconnect parasitics by modeling them within their RC corner analyses, providing optimized pathways that account for potential variations .
Clock Tree Synthesis (CTS) in Innovus addresses clock skew and fanout issues by incorporating buffers and inverters into the clock tree. These additions help mitigate the delay differences experienced due to various path lengths, ensuring that clock signals reach each sequential element simultaneously. During the design import phase, Innovus selects suitable buffers, inverters, and delay cells from the standard cell .lib files, optimizing the clock tree's performance . The CTS process involves reporting and adjusting the clock structure to ensure that the clock signal is uniformly distributed across the chip, minimizing skew and effectively managing fanout . The process uses the 'ccopt_design' command for optimization and 'report_ccopt_clock_trees' to analyze the clock tree structure, allowing fine-tuning of the clock routes for optimal performance.
Innovus ensures that the design remains logically equivalent to the synthesized netlist through several verification and optimization steps throughout the P&R process. After each major step such as placement, CTS, and routing, checks are conducted using commands like 'checkDesign –all', which validates the design against logical errors that could have arisen during the transformations . Additionally, Logical Equivalence Checking (LEC) is performed, contrasting the post-P&R netlist with the synthesized netlist to ensure that no functional discrepancies exist. The utilization of constraints and verification reports aids in preserving logical integrity, allowing for iterative verification throughout the design cycle .
Setting up floorplanning contributes to the successful placement of standard cells by defining the layout's size and structure. The core size is chosen to maintain a utilization rate between 60% and 70%, directly affecting the area's efficiency for cell placement . Power routing is achieved by creating power/ground (PG) rings and stripes, which serve as critical paths for power distribution across the chip, ensuring all cells are biased properly. The use of multiple metal layers for PG rings and stripes, combined with correct spacing, minimizes electrical resistance and potential IR drop, thus supporting efficient power distribution . Both steps are fundamental in defining a structured, flexible environment for placing standard cells within the designated areas, ensuring operational reliability.
Timing analysis is crucial at various stages of the P&R workflow to ensure the circuit meets performance requirements and operates reliably. Initially, during the pre-place stage, timing analysis helps to identify any inherited timing problems from the synthesis phase . In the pre-CTS stage, another analysis is needed because the initial placement and routing might introduce new issues. Post-CTS analysis is critical to detecting imbalances introduced by clock skew or fanout problems . Finally, during post-route, timing analysis confirms that all previous stages’ adjustments harmonize, ensuring the WNS and TNS are positive and that the design adheres to all setup and hold constraints. This iterative checking and optimization process ensures timing correctness across all stages, preventing costly design failures .
When defining the core size during the floorplanning stage, it is crucial to consider the utilization rate, targeting around 60% to 70% to balance between layout density and routing flexibility . The core height should align with the standard cells' fixed height of 3.2um, and the width should be a multiple of 0.4um to facilitate alignment with the routing grid. Core-to-IO margins are also kept as multiples of 0.4um to maintain consistency and alignment in design rules. These considerations help ensure that adequate space is available for routing and additional components like power rings, which influences the efficiency of the place and route phases significantly .
Power planning, including the addition of power rings and stripes, is integral to maintaining power integrity and enhancing overall chip performance. Power rings serve as primary conduits for delivering stable power across the chip, reducing IR drop and potential latch-up. They are strategically placed using upper metal layers like M6 to M8, which offer lower resistance . Meanwhile, adding stripes within large designs ensures uniform voltage distribution and mitigates IR drop by connecting various power rail segments in distributed locations across the chip. These elements collectively help in delivering consistent power and grounding, enhancing the reliability of the chip under varying operational loads and reducing electromigration risks . Vias are used effectively to link the rings and stripes across multiple layers, further optimizing vertical power distribution within the chip.
Filler cells play a pivotal role in the final stages of the Innovus P&R process by filling empty spaces within the core. This not only ensures that there are no gaps left between placed standard cells but also assists in biasing n-well and p-well regions, preventing electrical issues like latch-up . The addition of filler cells contributes to a more uniform diffusion and layout density, which is crucial for the validity of design rules before fabrication. Moreover, it aids in DRC (Design Rule Check) compliance, preparing the chip layout for the final sign-off, thereby enhancing the chip's manufacturability and reliability .
A Multi-Mode Multi-Corner (MMMC) configuration enhances the reliability of timing analysis by providing a comprehensive view of the timing uncertainties across different operational conditions. This approach involves using different timing libraries for 'best case' and 'worst case' scenarios, captured as delay corners in the form of BC and WC. By including variations in parameters like voltage, temperature, and process conditions, MMC setups encompass the broad range of conditions a chip might encounter in real-world usage. This ensures robustness, as the design is optimized not merely for a nominal scenario but across a spectrum of possible conditions, reducing the likelihood of failure in varying environments .
The initial steps to configure the Innovus Interface for P&R involve setting up the environment and preparing necessary files. First, create a dedicated directory for organizing designs, such as the 'DIGITAL' directory with a subdirectory 'P_and_R'. Within 'P_and_R', create a directory for the specific project, in this case, 'COUNTER4BIT'. Copy the file 'counter4bit_pr.tar' into this directory and extract its contents using the command '$ tar –xvf counter4bit_pr.tar'. Then, run the script '$ source /opt/ic_tools/init/init-innovus20-11-hf000' to initialize the software. Open the Innovus interface with the command '$ innovus', ensuring not to use 'innovus &' as the terminal needs to be used by the software .