UNIT 4-Combinational and sequential digital Systems

Combinational and sequential digital system

Half adder

The half adder is a logical circuit that adds two bits and givesthe result on two output line as sum and
carry; The block diagram of half adder is shown in figure.

Let A and B be the two inputs , sum and carry are the two outputs. A and B takes the values 0 or 1, the
total number of possible inputs is [Link] inputs and the corresponding outputs can be represented in a
truth table. XOR gate is applied to both inputs to produce sum and AND gate is applied to both inputs to
carry.
_ _
SUM= AB + AB
CARRY = AB
Full Adder

A full adder is a combinational circuit .The full adder is difficult to implement than a half-adder. The difference
between a half-adder and a full-adder is that the full-adder has three inputs and two outputs, whereas half adder
has only two inputs and two outputs. The first two inputs are A and B and the third input is an input carry as C-
IN. The two outputs for sum and carry .we can implement a full adder circuit with the help of two half adder
circuits. . At first, half adder will be used to add A and B to producea partial Sum and a second half adder logic
can be used to add C-lN to the Sum produced by the first half adder to get the final S output.

SUM = A B C

CARRY = (A B)C +AB

Half subtractor

Half subtractor is a logic circuit that subtracts one bit from another bit and produces two outputs as difference and
borrow. In binary subtraction, the major digit is 1, we can generate borrow while the subtrahend 1 is superior to
minuend 0 and due to this, borrow will need. The circuit of the half subtractor can be built with two logic gates
namely NAND and EX-OR gates. The block diagram and its truth table are shown.

The rules for binary subtraction is

0–0=0

0–1=1 with a borrow 1

1–0=1

1–1=0

_ _
Difference = AB+AB
_
Borrow = AB

TRUTH TABLE :

A B Difference Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

The applications of half subtractor :

 Half subtractor is used in amplifiers to reduce the Sound distortion.

 Half subtractor is used in ALU of microprocessor.
 It is used to reduce the force of audio or radio signals.
  It can be used to increase and decrease operators and also calculates the addresses.
 Half subtractor is used to subtract the least significant column numbers. Fr subtraction of multi-digit
numbers it can be used for the LSB.

FULL SUBTRACTOR

Full subtractor is an electronic device or logic circuit which performs subtraction of two binary digits.A full
subtractor is formed by two half subtractors , which involves three inputs such as minuend, subtrahend and borrow
The inputs of the full subtractor are A, B , C and outputs are D,Bout. The circuit of full subtractor can be built with
logic gates such as OR, Ex-OR, NAND [Link] bit among the inputs is obtained from subtraction of two
binary digits and is subtracted from next higher order pair of bits, outputs as difference and borrow.

Difference = A B C
_____ _
Borrow = ( A B )C + AB

INPUTS OUTPUTS
A B C DIFFERENCE
BORROW
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Applications of full subtractors

 Subtractors are used in processors to compute tables , address etc,.

  It is also useful for DSP and networking based systems.
 It I also applicable for different microcontrollers for arithmetic subtraction, timers and program
counter(PC).
 Subtractors are used for performing arithmetic functions like subtraction in electric calculators as well as
digital devices.

MULTIPLEXER

Multiplexer(MUX) is a device that combines several analog and digital input signals and forwards them into a
single outut line. A multiplexer of inputs has n select lines ,which are used to select which input line is send to
the output. Multilexers are mainly used to increase the amount of time and bandwidth. A multiplexer is also called
a data [Link] gates such as AND, NOT and OR gates are used to construct a multiplexer. OR gate is used
to get the output signal. Multiplexer is a multi-input, single-output switch

S1 S2 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
DEMULTIPLEXER

De-multiplexer is a combinational circuit that performs the reverse operation of [Link] has a single input, n
selection lines and maximum of outputs. The inputwill be connected to one of these outputs based on the values

of selection lines. Since there are n select lines, there will be possible combinations of zero and ones. So each
combination can select only one output . De-Multiplexer is also called as De-Mux.

1 x 4 De-Multiplexer has one input I , two selection lines, & and four outputs , , & .
COUNTERS

Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known as counter. Counter
is the widest application of flip-flops. It is a group of flip-flops with a clock signal applied. Counters are of two
types

 Asynchronous or ripple counters.

 Synchronous counters.

Asynchronous counters

When the clock pulses are applied to the flip-flops not simultaneously, that is when the flip-flops are clocked at
different instances, then the counters thus designed are called as asynchronous counters.

Synchronous counters

The clock pulses to the different flip-flops may be applied to all the flip-flops simultaneously , thus this case of
counters are called as synchronous counters.

Mod-2 counter

A modulo N (mod-N) counter is a counter that goes through a repeated sequence of N counts. A mod-2 counter
has only two states 0 and 1, i.e. a repeated sequence of two counts.

A single JK fli-flop directly functions as mod-2 counter in the toggle mode. Let us connect J and K together and
connect it to 5 V power supply so that J = 1 and K = [Link] application of each clock pulse, the outut toggles for
each clock pulse, that is the output changes its state from 0 to 1 (or) 1 to 0 repeatedly. AJK flip-flop connected in
toggle mode can be used as a mod-2 counter.

With J = 1 and K = 1, on application of each clock pulse, the outut toggles. We can draw a timing wave from
connecting the input clock pulses and the output Q. For every two clock pulses, we get one pulse at Q. When four
pulses are applied at the input , we get two pulses at the output. Therefore , a single JK master slave flip-flop in the
toggle mode behaves as a divide by 2 circuit. The logic diagram and the ouput waveforms for a mod-2 counter is
shown.

Mod-8 counter
 A mod-8 counter is constructed with three JK flip-flops connected in toggle mode. The logic diagram of mod-8
counter is shown.

The clock pulse is directly applied to the first flip-flop. The output of the first flip-flop is connected as a clock
input to the second flip-flop. Therefore, whenever changes its state from 1 to 0, the output of the next flip-
flop toggles.

The output of the second flip-flop is connected as a clock input to the third flip-flop. Therefore, whenever

changes its state from 1 to 0, the output of the next flip-flop toggles. Thus the application of each clock pulse ,
the counter advances by one . The timing waveform and the count sequence is given.

CLK
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 0
6 1 1 0
7 1 1 1
8 0 0 0
Mod-10 counter
 A mod-10 counter consists of the 4 JK flip-flops which can count to a maximum of 15. A mod-10 counter has
10 distinct states . It counts from 0000 to [Link] J and K inputs of the flip-flops are connected in toggle mode i.e
J=K=1.

But since we require only output upto 9 (i.e 1001), on application of the next clock pulse, the count should reach
0 (i.e 0000) instead of advancing to 10 (1010). The output 1010 combination is used to reset the counter.

For the combination 1010, the outputs and will only be equal to 1. These outputs are fed as inputs to a
NAND gate G. The output of the NAND gate is connected to the clear terminals of all the four flip-flops. The
output of the NAND gate goes to 0 only when both the inputs are 1. As and are connected as inputs to the
NAND gate goes to 0 when the counter counts 1010. As the output of the gate is connected to the clear terminals,
all the flip-flops reset to 0.

Once the counter is reset, all the outputs are 0’s. The input to the NAND gates are also 0’s and therefore the
output of the NAND gate becomes 1. Therefore , the clear inputs of all the flip-flops go to ‘1’ state , allowing the
flip-flops to function normally. Now the counter starts counting up from 0000 again. In this NAND gate is the
decoding gate. This type of decoding gates can be used to alter the sequence of a counter.

The propagation delay of the flip-flops FF3 and FF1 need not be equal. Therefore , when the clear input is given
to these two flip-flops , their outputs may not become ‘0’ simultaneously. Suppose the output of FF3 , that is is

cleared first ahead of the output of FF1, that is , then the output of the counter becomes 0010 instead of
[Link] sequence for mod-10 counter is given in the table

CLK
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
 7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 0 0 0 0

Mod-16 counter

Mod-16 counter requires four JK flip-flops in toggle mode. As an extension of mod-8 counter, we can construct
a mod-16 counter.

Let us call the flip-flops as FF1,FF2,FF3 and FF4. During each clock pulse, toggles .The output of FF1 is

applied as clock input to the FF2. So the output FF2 toggles whenever changes its state from 1 to 0. Similarly,

changes whenever toggles from 1 to 0. The table shows a 4-bit binary sequence count from 0000 to 1111.

A mod-16 counter is also known as 4-bit binary up counter or 4-bit ripple counter or asynchronous counter.
The logic diagram and the output waveforms for a mod-16 is shown.

CLK
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
16 0 0 0 0