Code for 4 bit Shift Register
Expt no 9
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ShiftRegister is
Port (
clk: in STD_LOGIC;
reset: in STD_LOGIC;
shift: in STD_LOGIC;
data_in: in STD_LOGIC_VECTOR(3 downto 0);
data_out: out STD_LOGIC_VECTOR(3 downto 0)
);
end ShiftRegister;
architecture Behavioral of ShiftRegister is
signal register_data: STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin
process(clk, reset)
begin
if reset = '1' then
register_data <= "0000";
elsif rising_edge(clk) then
if shift = '0' then
-- Left shift
register_data(0) <= data_in(0);
register_data(1) <= register_data(0);
register_data(2) <= register_data(1);
register_data(3) <= register_data(2);
elsif shift = '1' then
-- Right shift
register_data(3) <= data_in(3);
register_data(2) <= register_data(3);
register_data(1) <= register_data(2);
register_data(0) <= register_data(1);
end if;
end if;
end process;
data_out <= register_data;
end Behavioral;
Right Shift
Left Shift
Expt no: 5
Code for sequence generator
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity StepperMotorSequenceGenerator is
Port (
clk: in STD_LOGIC;
reset: in STD_LOGIC;
phi1, phi2, phi3, phi4: out STD_LOGIC
);
end StepperMotorSequenceGenerator;
architecture Behavioral of StepperMotorSequenceGenerator is
signal counter: integer := 0;
signal delay_counter: integer := 0;
constant delay_cycles: integer := 35; -- Number of clock cycles for the delay
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
counter <= 0;
delay_counter <= 0;
else
counter <= counter + 1;
delay_counter <= delay_counter + 1;
-- Reset the counter if it reaches the maximum value (40ns)
if counter = 40 then
counter <= 0;
end if;
-- Generate phi1, phi2, phi3, and phi4 signals
phi1 <= '0';
phi2 <= '0';
phi3 <= '0';
phi4 <= '0';
-- Set the desired intervals for each signal
if counter >= 5 and counter <= 10 then
phi1 <= '1';
elsif counter >= 15 and counter <= 20 then
phi2 <= '1';
elsif counter >= 25 and counter <= 30 then
phi3 <= '1';
elsif counter >= 35 and counter <= 40 then
phi4 <= '1';
end if;
-- Reset the delay counter
if delay_counter = delay_cycles then
delay_counter <= 0;
end if;
end if;
end if;
end process;
end Behavioral;
Out put
Password based security system
Expt No : 6
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SecuritySystem is
Port (
clk: in STD_LOGIC;
reset: in STD_LOGIC;
keypad_input: in STD_LOGIC_VECTOR(3 downto 0);
lock: out STD_LOGIC
);
end SecuritySystem;
architecture Behavioral of SecuritySystem is
constant correct_code: STD_LOGIC_VECTOR(3 downto 0) := "1101"; -- Correct security code
begin
process(clk, reset)
begin
if reset = '1' then
lock <= '0';-- door will be locked if reset is 1
elsif rising_edge(clk) then
if keypad_input = correct_code then
lock <='1'; --- door will be open if keypad input = 1101
else lock<='0'; -- else door will be closed
end if;
end if;
end process;
end Behavioral;
Out put
Elevator controller
Expt: 4
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ElevatorControl is
Port (
clk: in STD_LOGIC;
reset: in STD_LOGIC;
FLRCALL: in STD_LOGIC_VECTOR(2 downto 0); -- Floor call signals (binary)
FLRREQ: in STD_LOGIC_VECTOR(2 downto 0); -- Requested floor signals (binary)
door_open: out STD_LOGIC;
elevator_floor: inout STD_LOGIC_VECTOR(2 downto 0)
);
end ElevatorControl;
architecture Behavioral of ElevatorControl is
type State_Type is (WAIT1, MOVE_TO_FLRCALL, OPEN_DOORS_ENTER, CLOSE_DOORS,
MOVE_TO_FLRREQ, OPEN_DOORS_EXIT, TIMED_DELAY);
signal State, NextState: State_Type;
signal TimeCounter: integer := 0;
begin
process(clk, reset)
begin
if reset = '1' then
State <= WAIT1;
TimeCounter <= 0;
elsif rising_edge(clk) then
State <= NextState;
end if;
--end process;
--process(State, FLRCALL, FLRREQ, TimeCounter)
--begin
door_open <= '0';
elevator_floor <= (others => '0');
case State is
when WAIT1 =>
if FLRCALL /= "000" then
NextState <= MOVE_TO_FLRCALL;
elsif FLRREQ /= "000" then
NextState <= MOVE_TO_FLRREQ;
else
NextState <= WAIT1;
end if;
when MOVE_TO_FLRCALL =>
elevator_floor <= FLRCALL;
if FLRCALL = elevator_floor then
NextState <= OPEN_DOORS_ENTER;
end if;
when OPEN_DOORS_ENTER =>
door_open <= '1';
NextState <= TIMED_DELAY;
when TIMED_DELAY =>
if TimeCounter >= 1000 then -- Adjust the count for your time delay
TimeCounter <= 0;
door_open <= '0';
NextState <= CLOSE_DOORS;
else
TimeCounter <= TimeCounter + 1;
end if;
when CLOSE_DOORS =>
NextState <= MOVE_TO_FLRREQ;
when MOVE_TO_FLRREQ =>
elevator_floor <= FLRREQ;
if FLRREQ = elevator_floor then
NextState <= OPEN_DOORS_EXIT;
end if;
when OPEN_DOORS_EXIT =>
door_open <= '1';
NextState <= TIMED_DELAY;
when others =>
NextState <= WAIT1;
end case;
end process;
end Behavioral;
output
Library IEEE;
USE IEEE.Std_logic_1164.all;
entity RisingEdge_DFlipFlop is
port(
Q : out std_logic;
Clk :in std_logic;
D :in std_logic
);
end RisingEdge_DFlipFlop;
architecture Behavioral of RisingEdge_DFlipFlop is
begin
process(Clk)
begin
if(rising_edge(Clk)) then
Q <= D;
end if;
end process;
end Behavioral;
Out put
library iee
e;
use ieee. std_logic_1164.al
l;
use ieee. std_logic_arith.al
l;
use ieee.
std_logic_unsigned.all;
entity SR_FF
is
PORT(
S,R,CLOCK: in std_logic;
Q,
QBAR: out std_logic);
end SR_F
F;
Architecture
behavioral of SR_FF is
beg
in
PROCESS(CLOC
K)
variable tmp: std_logi
c;
beg
in
if (rising_edge(Clk))
then
if(S='0' and R='0')th
en
tmp:=tm
p;
elsif(S='1' and R='1')th
en
tmp:='Z
';
elsif(S='0' and R='1')th
en
tmp:='0
';
el
se
tmp:='1
';
end i
f;
end i
f;
Q <=
tmp;
QBAR
<= not tmp;
end PROCES
S;
end behaviora
l;
Out put
library iee
e;
use ieee. std_logic_1164.al
l;
use ieee. std_logic_arith.al
l;
use ieee.
std_logic_unsigned.all;
entity JK_FF
is
PORT(
J,K,CLOCK: in std_logic;
Q,
QB: out std_logic);
end JK_F
F;
Architecture
behavioral of JK_FF is
beg
in
PROCESS(CLOC
K)
variable TMP: std_logi
c;
beg
in
if(rising_edge(Clk)) th
en
if(J='0' and K='0')th
en
TMP:=TM
P;
elsif(J='1' and K='1')th
en
TMP:= not TM
P;
elsif(J='0' and K='1')th
en
TMP:='0
';
el
se
TMP:='1
';
end i
f;
end i
f;
Q<=TM
P;
Q
<=not TMP;
end PROCES
S;
end behaviora
l;
Out put
library IEE
E;
use IEEE.STD_LOGIC_1164.AL
L;
entity T_FF
is
port(
T: in std_logic;
Clock: in std_logi
c;
Q: out std_logic
);
end T_F
F;
architecture Behavioral of T_FF
is
signal tmp: std_logi
c;
beg
in
process (Cloc
k)
beg
in
if (rising_edge(Clk))
then
if T='0' th
en
tmp <=
tmp;
elsif T='1' th
en
tmp
<= not (tmp);
end i
f;
end i
f;
end proces
s;
Q <=
tmp;
end Behaviora
l;