Verilog HDL Design

▪ VCD Files

Verilog® HDL ▪ Specify Delays

▪ Timing region

Verilog HDL IIT Guwahati 1

 VCD (Value Change Dump) Files
Introduction to VCD Files

▪ In Verilog, Value Change Dump (VCD) files play a crucial role in debugging and analyzing hardware designs. A VCD file is
a textual format that records the value changes of signals over time during a Verilog simulation. It captures the
transitions of signals such as registers, wires, and other variables in the design, providing engineers with a detailed
overview of how their system behaves at each time step.

▪ VCD files are particularly useful for post-simulation analysis, allowing designers to inspect the internal workings of their
hardware designs without re-running simulations. By using waveform viewers such as GTKWave or ModelSim,
engineers can load VCD files to visually track how signals change over time, helping them understand and debug
complex interactions within their designs.

▪ VCD files consist of two primary sections: a header section and a data section. The header provides metadata about
the simulation, such as the date, version, and definitions of all variables. The data section contains timestamps and the
corresponding signal transitions, allowing users to analyze when and how signals change during the simulation.

▪ Given their powerful capabilities, VCD files are widely used for debugging, performance analysis, and even power
estimation in large-scale designs. Understanding how to generate, use, and analyze VCD files is an essential skill for
hardware designers working with Verilog.

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 What is Inside a VCD File?
▪ A Value Change Dump (VCD) file captures the signal transitions during a Verilog simulation. Its structure is divided into two main sections: the
Header and the Data.

Header Section Data Section

The header section contains essential metadata about the simulation: The data section records the actual signal transitions over time:

▪ Date: Indicates when the simulation was run. ▪ Timestamps: Represented by a # symbol followed by a number
Example: $date today $end indicating the simulation time in the given timescale.
Example: #0, #10 (time unit 0 and 10 ns)
▪ Version: Describes the version of the simulator used.
Example: $version Verilog Simulation $end ▪ Value Changes: Shows the state of a signal at a given time. The
format is a value followed by the signal identifier.
▪ Timescale: Defines the time unit used in the simulation (e.g., nanoseconds). Example: b0 ! (the signal clk has the value 0 at this time)
Example: $timescale 1 ns $end

▪ Signal Definitions: Lists all the signals (variables) involved in the simulation,
their types, and unique identifiers.
Example: $var reg 1 ! clk $end (indicating a 1-bit register clk with the
identifier !)

▪ Scope: Defines the module hierarchy, which organizes signals based on their
module.
Example: $scope module test $end

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 Understanding the VCD File Structure
▪ Header Section: Contains date, version, and variable definitions.
▪ Simulation Data Section: Time steps and corresponding signal value changes.
Sample VCD Content:

$date today $end //$date, $version, and $timescale: Provide basic information
$version Verilog Simulation $end
$timescale 1 ns $end

$scope module test $end //$var reg 1 ! clk: Defines a signal clk with identifier !.
$var reg 1 ! clk $end
$var reg 1 " reset $end
$upscope $end
$enddefinitions $end

#0 //#0 and #10: Represent time units.

b0 ! //b0 !: Indicates that the signal clk has changed to 0 at time 0.

b1 "
#10
b1 !

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 Why Use VCD Files?
▪ Debugging and Troubleshooting: VCD files capture every signal transition during a simulation. This makes it
easier to identify bugs, timing issues, and unexpected behavior by visually analyzing how signals change
over time.

▪ Post-Simulation Analysis: With VCD files, designers can analyze the behavior of their design after the
simulation is complete, without re-running the simulation. This helps when dealing with long simulations or
when focusing on specific parts of the design.

▪ Waveform Visualization: VCD files can be opened in waveform viewers like GTKWave or ModelSim,
allowing designers to visually inspect signal transitions and interactions between modules.

▪ Power Estimation: By tracking signal transitions, VCD files can be used in power analysis tools to estimate
the dynamic power consumption of a design based on switching activity.

▪ Selective Signal Dumping: Designers can choose to dump only the relevant signals in a VCD file, reducing
unnecessary data and improving performance in large simulations.

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 Creating VCD Files in Verilog
▪ Use $dumpfile and $dumpvars tasks in Verilog to create and store simulation data in a VCD file.

Verilog Example:
module test;
reg clk;
reg reset;
initial begin
$dumpfile("[Link]"); // Create a VCD file named "[Link]"
$dumpvars(0, test); // Dump all variables in the module "test"
end
initial begin
clk = 0;
reset = 1;
#5 reset = 0;
#100 $finish; // End the simulation after 100-time units
end
always #10 clk = ~clk; // Clock signal toggles every 10-time units
endmodule

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 VCD Dump Commands in Detail
In Verilog simulations, $dump commands are used to generate VCD (Value Change Dump) files, which capture signal
transitions over time for debugging and analysis. These commands are essential for dumping the internal signal values
during simulation.

$dumpfile Command
▪ This command specifies the name of the VCD file where the simulation data will be stored.

Syntax: $dumpfile("[Link]");

Example:
initial begin
$dumpfile("simulation_output.vcd"); // Creates a VCD file named "simulation_output.vcd"
end

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 VCD Dump Commands in Detail
In Verilog simulations, $dump commands are used to generate VCD (Value Change Dump) files, which capture signal transitions
over time for debugging and analysis. These commands are essential for dumping the internal signal values during simulation.

$dumpvars Command
▪ This command selects which signals will be dumped to the VCD file.
▪ You can choose to dump all signals in a module or selectively dump specific signals or modules.

Syntax: $dumpvars(level, scope);

▪ level: Specifies the hierarchy level to dump. A value of 0 dumps all signals in the module.
▪ scope: Specifies the module or specific signals to dump.
Example: Dumping All Variables in a Module
// This dumps all signals in the top module and all levels of its submodules.

initial begin
$dumpvars(0, top); // Dumps all variables in the module "top" and its submodules
end

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 VCD Dump Commands in Detail
Example: Selective Dumping in Specific Hierarchies
// Here, the first line dumps all signals in the top module and its immediate submodules. The
second line focuses only on the clk signal within the top module.

initial begin
$dumpvars(1, top); // Dumps variables in the top module and one level deep into submodules
$dumpvars(0, [Link]); // Dumps only the clk signal from the top module
end

Example: Dumping a Specific Module

// This dumps all signals specifically from the submodule, without affecting other parts of the
design.

initial begin
$dumpvars(0, submodule); // Dumps all signals in "submodule" only
end

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 VCD Dump Commands in Detail
▪ $dumpon and $dumpoff Commands
▪ These commands allow conditional dumping during specific periods of simulation.
$dumpon: Starts dumping signals.
$dumpoff: Stops dumping signals.

Syntax: $dumpon;
$dumpoff;

Example:

// In this example, signal dumping begins at the start of the

simulation, stops after 50-time units, and resumes again after 100-time
units. This is useful for focusing on critical periods of simulation to
reduce the size of VCD files.

initial begin
$dumpon; // Start dumping
#50 $dumpoff; // Stop dumping after 50-time units
#100 $dumpon; // Start dumping again at 100-time units
end

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 VCD Dump Commands in Detail
▪ $dumpall Command
Dumps all currently active signals and their values at the point where the command is issued.
This is often used to take a snapshot of all signal values.

Syntax: $dumpall;

Example:

// In this example, after 100-time units, all signals are dumped to the VCD
file, capturing a snapshot of the system's state.
initial begin
initial begin
$dumpfile("[Link]");
$dumpvars(0, top);
#100 $dumpall; // Dumps the values of all active signals at 100-time units
end

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 $dumpfile and $dumpvars in Testbenches
module testbench;
reg clk, reset;
reg [3:0] counter;
initial begin
$dumpfile("testbench_output.vcd"); // Specify the output VCD file
$dumpvars(0, testbench); // Dump all signals in the "testbench" module
end
// Generate clock signal
initial begin
clk = 0;
forever #5 clk = ~clk; // Toggle clock every 5-time units
end
// Test logic
initial begin
reset = 1;
#10 reset = 0;
#100 $finish; // End simulation after 100-time units
end
always @(posedge clk or posedge reset) begin
if (reset)
counter <= 4'b0000;
else
counter <= counter + 1;
end
endmodule

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 Waveform Viewing Using VCD Files
module testbench;
▪ Access EDA Playground reg clk, reset;
reg [3:0] counter;
Go to the EDA Playground website at initial begin
// Specify VCD file name
[Link]. $dumpfile("[Link]");
// Dump all variables in the testbench module
▪ Write Your Verilog Code
$dumpvars(0, testbench);
In the left-hand editor, write your Verilog code. Be end
initial begin
sure to include the necessary $dumpfile and clk = 0;
reset = 1;
$dumpvars commands to generate the VCD file. #5 reset = 0;
#100 $finish; // End simulation after 100-time units
end
// Generate clock signal every 5-time units
always #5 clk = ~clk;
always @(posedge clk or posedge reset) begin
if (reset)
counter <= 4'b0000;
else
counter <= counter + 1;
end
endmodule

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 Waveform Viewing Using VCD Files
▪ Select a Simulator
From the "Tools + Simulators" dropdown menu on the right, select a simulator that supports VCD file generation. For
example, choose Synopsys VCS.

▪ Enable VCD Waveform Output

In the "Options" section, make sure to enable the "Run time options" box and select the "Enable VCD"
checkbox to ensure the VCD file is created.

▪ Run the Simulation

Click the "Run" button at the top of the page to compile and simulate your Verilog code.
Wait for the simulation to complete. If successful, the message "Simulation finished" will appear at the bottom.

▪ View the Waveform

After the simulation completes, a "View Waveform" button will appear.
Click "View Waveform" to open the waveform viewer in a new window.

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 Specify Delay
▪ A delay between a source (input or inout) pin and a destination (output or inout) pin of a module is called a module path
delay.
▪ Path delays are assigned in Verilog within the keywords specify and endspecify.
▪ The statements within these keywords constitute a specify block.
▪ Specify blocks contain statements to do the following:
-> Assign pin-to-pin timing delays across module paths.
-> Set up timing checks in the circuits.
-> Define specparam constants.

▪ The specify block is a separate block in the module and does not appear under any other block, such as initial or always.
▪ We analyze the statements that are used inside specify blocks :-
-> Parallel Connections.
-> Full Connections

▪ A parallel connection is specified by the symbol =>

▪ A full connection is specified by the symbol *>

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 Pin to Pin Delay using Specify Blocks
module M (out, a, b, c, d);
output out;
input a, b, c, d;
wire e, f;
//Specify block with path delay statements
specify
(a => out) = 9; // Showing Parallel Connection
(b => out) = 9; // bit-to-bit connection. both b and out are single-bit
(c => out) = 11;
(d => out) = 11;
endspecify
//gate instantiations
and a1(e, a, b);
and a2(f, c, d);
and a3(out, e, f);
endmodule

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 Inside Specify Blocks
Parallel Connection:A parallel connection is specified by the symbol =>
( <source_field> => <destination field> ) = <delay_value>;

In a parallel connection, each bit in source field connects to its corresponding bit in the destination field.
If the source and the destination fields are vectors, they must have the same number of bits; otherwise,
there is a mismatch. Thus, a parallel connection specifies delays from each bit in source to each bit in
destination.

0 0

Source Field 1 1 Destination Field

2 2

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 Inside Specify Blocks
Parallel Connection Example :
//bit-to-bit connection. both a and out are single-bit
(a => out) = 9; //vector connection. both a and out are 4-bit vectors a[3:0], out[3:0]
//a is source field, out is destination field.
(a => out) = 9; //this statement is shorthand notation for four bit-to-bit connection statements
(a[0] => out[0]) = 9;
(a[1] => out[1]) = 9;
(a[2] => out[2]) = 9;
(a[3] => out[3]) = 9;
// illegal connection. a[4:0] is a 5-bit vector, out[3:0] is 4-bit.
// Mismatch between bit width of source and destination fields
(a => out) = 9; //bit width does not match.

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 Inside Specify Blocks
▪ Full Connection :
A Full connection is specified by the symbol *>
( <source_field > *> <destination field>)=<delay_value>;
In a full connection, each bit in the source field connects to every bit in the destination field. If the source and the
destination are vectors, then they need not have the same number of bits.
▪ Full Connection Example :
//Full Connection
module M (out, a, b, c, d);
output out;
0 0
input a, b, c, d;
wire e, f;
//full connection
Source Field 1 1 Destination Field
specify
(a,b *> out) = 9;
(c,d *> out) = 11;
2 2
endspecify
and a1(e, a, b);
and a2(f, c, d);
and a3(out, e, f);
endmodule

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 edge Sensitive Paths and specparam statements
An edge-sensitive path :
▪ construct is used to model the timing of input to output delays, which occurs only when a specified edge occurs at the
source signal.
/*In this example, at the positive edge of clock, a module path extends from clock signal to
out signal using a rise delay of 10 and a fall delay of 8. The data path is from in to out,
and the in signal is not inverted as it propagates to the out signal.*/
(posedge clock => (out +: in)) = (10 : 8);

specparam statements :
▪ Special parameters can be declared for use inside a specify block.
▪ They are declared by the keyword specparam.
▪ Instead of using hardcoded delay numbers to specify pin-to-pin delays, it is common to define specify parameters by
using specparam and then to use those parameters inside the specify block.
▪ The specparam values are often used to store values for non-simulation tools, such as delay calculators, synthesis
tools, and layout estimators.
//Specify parameters using specparam statement
specify
//define parameters inside the specify block
specparam d_to_q = 9;
specparam clk_to_q = 11;
(d => q) = d_to_q;
(clk => q) = clk_to_q;
endspecify

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 Conditional Path delays
Conditional Path delays :
▪ Conditional path delays are also known module m(out, a, b, c, d); // module and inputs outputs declaration
as state dependent path delays(SDPD). output out;
▪ Based on the states of input signals to a input a, b, c, d;
circuit, the pin-to-pin delays might wire e, f;
specify //specify block with conditional pin-to-pin timing
change.
//different pin-to-pin timing based on state of signal a.
▪ Verilog allows path delays to be if (a) (a => out) = 9;
assigned conditionally, based on the if (~a) (a => out) = 10;
value of the signals in the circuit. A //Conditional expression has two signals b , c. If b & c is true, delay
conditional path delay is expressed with = 9, Conditional Path Delays
the if conditional statement. The if (b & c) (b => out) = 9;
if (~(b & c)) (b => out) = 13; //Use concatenation operator. Use Full
operands can be scalar or vector
connection
module input or inout ports or their bit- if ({c,d} == 2'b01) (c,d *> out) = 11;
selects or part-selects, locally defined if ({c,d} != 2'b01) (c,d *> out) = 13;
registers or nets or their bit-selects or endspecify
part-selects, or compile time constants and a1(e, a, b); and a2(f, c, d); and a3(out, e, f);
(constant numbers and specify block endmodule
parameters).

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 Timing Checks :$setup and $hold
Timing Checks
▪ The purpose of specifying path delays is to simulate the timing of the actual digital circuit with greater
accuracy than gate delays.
▪ Timing checks are used to see if any timing constraints are violated during simulation.
▪ Timing verification is particularly important for timing critical, high-speed sequential circuits such as
microprocessor.
▪ System tasks are provided to do timing checks in Verilog like $setup and $hold.

$setup(data_event, reference_event, limit); data_event: Signal that is monitored for

specify violations.
reference_event: Signal that establishes a
$setup(data, posedge clock, 3);
reference for monitoring the
endspecify
data_event signal.
limit: Min time required for setup of data event
Violation is reported if
(Treference_event - Tdata_event) < limit.
clock

data

3ns
setup
time
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 $hold task
▪ $hold : Hold checks can be specified with the system task $hold.

$hold( reference_event, data_event,limit);

data_event Signal that is monitored for violations.

reference_event Signal that establishes a reference for monitoring the data_event signal.
limit Min time required for setup of data event Violation is reported if (Tdata_event –
Treference_event) < limit.

specify
$hold(posedge clear, data, 5);
endspecify clock

data

setup 5ns
time hold
time

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 Timing Regions
▪ In Verilog simulations, timing regions control the order in which events (like signal assignments, evaluations, and
updates) happen during a single time step. These regions are crucial for ensuring predictable and accurate simulation
results, particularly when modeling synchronous digital systems.

▪ Verilog timing regions are categorized into several phases. These regions help manage event execution within the same
simulation time unit, following a well-defined order.

▪ Timing Regions Flow are :

▪ Active Region: All blocking assignments and evaluations of logic happen here, ( consists: $display, $write and Evaluation of Blocking
assignments).

▪ Inactive Region: Non-blocking assignments are scheduled but not yet updated, (consists: #0 dealys).

▪ NBA Region: Non-blocking assignments are updated in this region, (consists: Non-blocking assignments).

▪ Postponed Region: Refer to a specific time step (or simulation phase) that occurs after the regular simulation activities in the
current time unit, (consists: $monitor and $strobe).

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 Timing Regions

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 Verilog HDL Design

THANK YOU

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