VLSI DESIGN and TESTING

(BEC602)
MODULE-5
Sequential MOS Logic Circuits

Introduction, Behaviour of Bistable Elements, Clocked Latch and Flip-Flop

Circuits, Clocked SR Latch, Clocked JK Latch.
(Text Book: “CMOS Digital Integrated Circuits: Analysis and Design”, Sung Mo Kang &
Yosuf Leblebici, Third Edition, Tata McGraw-Hill 8.1, 8.2, 8.3, 8.4)

Structured Design and Testing: Introduction, Design Styles, Testing

(Text Book: Principals of CMOS VLSI Design A System approach Neil H E Weste
and Kamran Eshraghain . Addition Wisley Publishing company. 6.1, 6.2, 6.5)

1
Introduction
Combinational logic circuits:
• The output levels at any given time point are directly determined as
Boolean functions of the input variables applied at that time.
• The combinational circuits lack the capability of storing any previous
events, or displaying an output behavior which is dependent upon the
previously applied inputs. Circuits of this type are also classified as non-
regenerative circuits, since there is no feedback relationship between
the output and the input.
Sequential circuits:
• The output is determined by the current inputs as well as the previously
applied input variables. Figure 1 shows a sequential circuit consisting of
a combinational circuit and a memory block in the feedback loop.
2
 The critical components of
sequential systems, are the
basic regenerative circuits,
which can be classified into
Figure 1: Sequential circuit consisting of a
combinational logic block and a memory block in three main groups:
the feedback loop.
1. Bistable circuits
2. Monostable circuits
3. Astable circuits

Figure 2: Classification of logic circuits based

3
on their temporal behavior.
Bistable circuits
• Two stable states or operation modes, each of which can
be attained under certain input and output conditions.

• Most widely used and the most important class.

Examples: latchs, flip-flop circuits, registers, and memory

elements.
Monostable circuits
• Have only one stable operating point (state).

• Even if the circuit experiences an external perturbation, the

output eventually returns to the single stable state after a
certain time period. 4
Astable circuits
• There is no stable operating point or state which the circuit
can preserve for a certain time period.

• The output of an astable circuit oscillate without settling

into a stable operating mode.

Example: The ring oscillator.

Among these three main groups of regenerative circuit types,

the bistable circuits are by far the most widely used 'and the
most important class.

5
Behavior of Bistable Elements

• The basic bistable element consists of two identical crosscoupled

inverter circuits, as shown in Figure 3. Here, the output voltage
of inverter (1) is equal to the input voltage of inverter (2), i.e.,
Vo1 = Vi2, and the output voltage of inverter (2) is equal to the
input voltage of inverter (1), i.e., Vo2 = Vi1.

Figure 3: Circuit Schematic of Two-Inverter Basic

Bistable Element 6
• Static input-output behavior of both
inverters, the voltage transfer
characteristic of inverter (1) with
respect to the Vo1 – Vi1, axis pair.

• The input and output voltages of

inverter (2) correspond to the
output and input voltages of inverter
(1), respectively.

• Consequently, we can also plot the

voltage transfer characteristic of
inverter (2) using the same axis pair,
as shown in Figure 4.

Figure 4: Static behavior of the two-inverter basic

bistable element
(a) Intersecting voltage transfer curves of the two
inverters, showing the three possible operating points.
(b) Qualitative view of the potential energy levels
7
corresponding to the three operating points.
• It can be seen that the two voltage
transfer characteristics intersect at
three points.
• If the circuit is initially operating at
one of these two stable points, it
will preserve this state unless it is
forced externally to change its
operating point.
• The slope of the respective voltage
transfer curves, is smaller than
unity at the two stable operating
points. Thus, in order to change
the state by moving the operating
point from one stable point to the
other, a sufficiently large external
voltage perturbation must be
applied so that the voltage gain of
the inverter loop becomes larger
than unity.
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• The voltage gains of both inverters are larger than unity at the third operating
point. Consequently, even if the circuit is biased at this point initially, a small
voltage perturbation at the input of any of the inverters will be amplified, causing
the operating point to move to one of the stable operating points.

• This leads to the conclusion that the third operating point is unstable. The circuit
has two stable operating points, hence, it is called bistable.

• The bistable behavior of the cross-coupled inverter circuit can also be visualized
qualitatively by examining the total potential energy level at each of the three
possible operating points (Figure 4). It is seen that the potential energy is at its
minimum at two of the three operating points, since the voltage gains of both
inverters are equal to zero.

• By contrast, the energy attains a maximum at the operating point at which the
voltage gains of both inverters are maximum.

• Thus, the circuit has two stable operating points corresponding to the two energy
minima, and one unstable operating point corresponding to the potential energy
maximum.
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CMOS Two-Inverter Bistable Element

• Figure 5(a) shows the circuit diagram of a CMOS two-inverter

bistable element.

• The unstable operating point of this circuit, all four transistors

are in saturation, resulting in maximum loop gain for the circuit.

• If the initial operating condition is set at this point, any small

voltage perturbation will cause significant changes in the
operating modes of the transistors. Thus, we expect the output
voltages of the two inverters to diverge and eventually settle at
VOH and VOL, respectively, as illustrated in Figure 5(b).

10
Figure 5: (a) Circuit diagram of a CMOS bistable element.
(b) One possibility for the expected time-domain behavior of the
output voltages, if the circuit is initially set at its unstable operating
point.

11
The SR Latch Circuit

• The bistable element consisting of two cross-coupled inverters Figure. 3

has two stable operating modes, or states.

• The circuit preserves its state as long as the power supply voltage is
provided; hence, the circuit can perform a simple memory function of
holding its state.

• However, the simple two-inverter circuit examined above has no provision

for allowing its state to be changed externally from one stable
operating mode to the other.

• To allow such a change of state, we must add simple switches to the

bistable element, which can be used to force or trigger the circuit from
one operating point to the other.

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• Figure 6 shows the circuit structure of
is equal to "1."
the simple CMOS SR latch, which has two
such triggering inputs, S (set) and R
(reset).
• The circuit consists of two CMOS NOR2
gates.
• One of the input terminals of each
NOR gate is used to cross-couple to the
output of the other NOR gate, while the
Figure 6: CMOS SR latch circuit based
second input enables triggering of the on NOR2 gates.
circuit.
• The SR latch circuit has two
complementary outputs, Q and • Conversely, the latch is in its reset
•The latch is said to be in its set state state when the output Q is equal to
when Q is equal to logic " 1 " and is logic "0" and is equal to "1."
equal to logic "0." 13
14
15
16
17
Depletion-load nMOS SR latch circuit based on NOR2 gates.

• The NOR-based SR latch can also be

implemented by using two cross-coupled
depletion-load nMOS NOR2 gates, as
shown in Figure 7.

Figure 7: Depletion-load nMOS SR latch based on NOR2 gates

• From the logic point of view, the operation principle of the depletion-load nMOS
NOR-based SR latch is identical to that of the CMOS SR latch.
• In terms of power dissipation and noise margins, the CMOS circuit
implementation offers a better alternative, since both of the CMOS NOR2 gates
dissipate virtually no static power for preserving a state, and since the output
voltages can exhibit a full swing between 0 and VDD.
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 CMOS SR latch circuit based on NAND2 gates.
• In the NAND-based SR latch circuit, to
hold (preserve) a state, both of the
inputs must be equal to logic " 1."

• The operating point or the state of the

circuit can be changed, by pulling the set
(S) input to logic zero or by pulling the
reset (R) input to zero. If S is equal to "0"
and R is equal to " 1," the output Q attains
Figure 8: CMOS SR latch circuit based
a logic " 1 " value and the complementary on NAND2 gates
output Q becomes logic "0."

• Thus, in order to set the NAND SR latch, a logic "0" must be applied to the set input.
Similarly, in order to reset the latch, a logic "0" must be applied to the reset (R) input.
The conclusion is that the NAND-based SR latch responds to active low input signals,
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as opposed to the NOR-based SR latch, which responds to active high inputs.
 Figure 9: Gate-level schematic and block
diagram of the NAND-based SR latch.
The gate-level schematic and the corresponding block diagram representation of
the NAND-based SR latch circuit are shown in Figure 9. The small circles at the S and
R input terminals indicate that the circuit responds to active low input signals. The
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truth table of the NAND SR latch is also shown in the following.
The NAND-based SR latch can also be implemented by using two cross-coupled
depletion-load NAND2 gates, as shown in Figure 10. While the operation
principle is identical to that of the CMOS NAND SR latch Figure 8 from the logic
point of view, the CMOS circuit implementation again offers a better
alternative in terms of static power dissipation and noise margins.

Figure 10: Depletion-load nMOS NAND-based SR latch circuit

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Clocked Latch and Flip-Flop Circuit
Clocked SR Latch

The SR latch circuits examined in the

previous section are asynchronous
sequential circuits, which will respond to
the changes occurring in input signals at
Figure 11: Gate-level schematic of
a circuit-delay-dependent time point the clocked NOR-based SR latch
during their operation.
To facilitate synchronous operation, the
circuit response can be controlled by
adding a gating clock signal to the
circuit, so that the outputs will respond
to the input levels only during the active
period of a clock pulse. 22
• The gate-level schematic of a clocked NOR-based SR latch is shown in Figure
11.
• It can be seen that if the clock (CK) is equal to logic "0," the input signals
have no influence upon the circuit response. The outputs of the two AND
gates will remain at logic "0" which forces the SR latch to hold its current
state regardless of the S and R input signals.
• When the clock input goes to logic " 1," the logic levels applied to the S and
R inputs are permitted to reach the SR latch, and possibly change its state.
• The input combination S = R = "1" is not allowed in the clocked SR latch. With
both inputs S and R at logic " 1," the occurrence of a clock pulse causes both
outputs to go momentarily to zero.

• To illustrate the operation of the clocked SR latch, a sample sequence

of CK, S, and R waveforms, and the corresponding output waveform
Q are shown in Figure 12.
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Figure 12: Sample input and output waveforms illustrating the operation
of the clocked NOR based SR latch circuit.

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• Figure 13 shows a CMOS implementation of the clocked NOR-based SR latch circuit,
using two simple AOI gates.

Figure 13: AOI-based implementation of the clocked

NOR-based SR latch circuit.

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• The NAND-based SR latch can also be implemented with gating clock
input, as shown in Figure 14.
• Both the input signals S and R as well as the clock signal CK are active low
in this case.
• This means that changes in the input signal levels will be ignored when the
clock is equal to logic " 1," and that inputs will influence the outputs only
when the clock is active, i.e., CK = "0."

Figure 14. Gate-level schematic of the clocked NAND-

based SR latch circuit, with active low inputs.

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• A different implementation of the
clocked NAND-based SR latch is
shown in Figure 15.
• Here, both input signals and the CK
signal are active high, i.e., the latch
output Q will be set when CK = " 1," S
= " 1," and R = "O."
• Similarly, the latch will be reset when
CK = "1," S = "O," and R = "1." The
latch preserves its state as long as the
clock signal is inactive, i.e., when CK =
"O. "
Figure 15:
• The drawback of this implementation (a) Gate-level schematic of the
is that the transistor count is higher clocked NAND-based SR latch
than the active low version shown in circuit, with active high inputs.
(b) Partial block diagram
Figure 14 representation of the same circuit.
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Clocked JK Latch
• SR latch/Flip flops circuits examined suffer from the common problem of
having a not-allowed input combination, i.e., their state becomes
indeterminate when both inputs S and R are activated at the same time.

• This problem can be overcome by adding two feedback lines from the
outputs to the inputs, as shown in Figure.16. The resulting circuit is called a JK
latch.

• Figure 16 shows an all-NAND implementation of the JK latch with active high

inputs, and the corresponding block diagram representation.

• The JK latch is commonly called a JK flip-flop.

Figure 16: Gate-level

schematic of the clocked
NAND-based JK latch
circuit. 28
 • The J and K inputs in this circuit
correspond to the set and reset inputs
of the basic SR latch. When the clock
is active, the latch can be set with the
input combination (J = '1," K = "0"),
and it can be reset with the input
combination (J = "0," K = "1").
• If both inputs are equal to logic "0,"

Figure 17. All-NAND implementation of the the latch preserves its current state.
clocked JK latch circuit. • If, on the other hand, both inputs are
equal to " 1 " during the active clock
phase, the latch simply switches its
state due to feedback.
• In other words, the JK latch does not
have a not-allowed input combination.
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Table 1: Detailed truth table of the JK latch circuit.

30
Clocked NOR-based JK latch circuit.

•Figure 18 shows an alternative, NOR-based

implementation of the clocked JK latch, and CMOS
realization of this circuit.
•While there is no not-allowed input combination
for the JK latch, there is still a potential problem.
•If both inputs are equal to logic " 1 " during the
active phase of the clock pulse, the output of the
circuit will oscillate (toggle) continuously until
either the clock becomes inactive or one of the
input signals goes to zero.
Figure 18. (a) Gate-level schematic of
•To prevent this undesirable timing problem, the the clocked NOR-based JK latch circuit.
clock pulse width must be made smaller than the
input-to-output propagation delay.
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•Assuming that the clock timing above is
satisfied, the output of JK latch will toggle
(change its state) only once for each clock
pulse, if both inputs are equal to 1 shown in
Figure 20.
•A circuit operated in this mode is called a
toggle switch.

Figure 19: CMOS AOI realization of

the JK latch.

Figure 20: Operation of the JK latch as a

toggle switch.
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Master-Slave Flip-Flop

• The timing limitations encountered in the clocked latch circuits can be

prevented by using two latch stages in a cascaded configuration.

• The key operation principle is that the two cascaded stages are activated with
opposite clock phases.

• This configuration is called the master-slave flip-flop.

• The input latch in Figure 21, called the "master," is activated when the clock pulse
is high. During this phase, the inputs J and K allow data to be entered into the flip-
flop, and the first-stage outputs are set according to the primary inputs.

• When the clock pulse goes to zero, the master latch becomes inactive and the
second-stage latch, called the "slave,“ becomes active.

• The output levels of the flip-flop circuit are determined during this second phase,
based on the master-stage outputs set in the previous phase.
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 Figure 21: Master-slave flip-flop consisting of NAND-based JK latches.
• The input latch in Figure 21, is called the "master," is activated when the clock pulse is
high. During this phase, the inputs J and K allow data to be entered into the flip-flop,
and the first-stage outputs are set according to the primary inputs.
• When the clock pulse goes to zero, the master latch becomes inactive and the second-
stage latch, called the "slave," becomes active. The output levels of the flip-flop circuit
are determined during this second phase, based on the master-stage outputs set in the
previous phase.
• Since the master and the slave stages are effectively decoupled from each other with
the opposite clocking scheme, the circuit is never transparent, i.e., a change occurring
34
in the primary inputs is never reflected directly to the outputs.
• Figure 22 shows a sample set of input and output waveforms associated with the
JK master-slave flip-flop.

Figure 22: Sample input and

output waveforms of the
master-slave flip-flop circuit

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• Because the master and the slave
stages are decoupled from each
other, the circuit allows for
toggling when J = K = "1," but it
eliminates the possibility of
uncontrolled oscillations since only
one stage is active at any given
time.
• A NOR-based alternative realization Figure 23: NOR-based realization of the JK
for the master-slave flip-flop circuit master-slave flip-flop
is shown in Figure 23.

• Figure 22 shows that the master-slave flip-flop circuit has the potential problem of "one's
catching." When the clock pulse is high, a narrow spike or glitch in one of the inputs, for
instance a glitch in the J line (or K line), may set (or reset) the master latch and thus cause
an unwanted state transition, which will then be propagated into the slave stage during
the following phase.
• This problem can be eliminated to a large extent by building an edge-triggered master-
slave flip-flop.
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 Structured Design and Testing
Introduction
The design description for circuit is described in terms of three domains, namely:

• The behavioral domain,

• The structural domain, and

• The physical domain.

• In each of these domains there are a number of design options that may be
selected to solve a particular problem.

• At the behavioral level, the freedom to choose say a sequential or parallel

algorithm is available.

• In the structural domain, the decision about which particular logic family, clocking
strategy, or circuit style to use is initially unbound.

• At the physical level, how the circuit is implemented in terms of chips, boards, and
cabinets also provides many options to the designer. 37
 Figure 24 (a) illustrates a typical
design flow of a contemporary design
system.
Figure 24 (b) illustrates an ideal
approach to design.

Figure 24 (a) contemporary design (b) ideal approach

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• A good VLSI design system should provide consistent descriptions in all three
description domains (Architectural, RTL/Block, Logic or circuit) at all relevant
levels of abstraction. VLSI design is a continuous tradeoff of below
parameters to achieve adequate results:
• Performance: Speed, power, function and flexibility

• size of die

• Time to design: Cost of Engineering and Schedule

• Ease of use

• Ease of test generation and testability.

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 Hierarchy

• Divide and Conquer strategy.

• Divide system into modules and then into submodules till

the deepest sub module is easily implementable.

• Or Prebuilt component is available ( Stdcell from library)

• Equivalence tools need to ensure consistency in each

domain.

• Hierarchy allows the use of virtual components.

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41
Modularity

• In IC, modularity corresponds to a clearly defined behavioral, structural and

physical interface.

• Interface indicates the function, name, signal type, electrical and timing
constraints on ports of the design.

• Too Large fan-in and too small drive capability can lead to unexpected
timing problems.

Some of the attributes associated with these modularity:

Position, Connection layer, wire width of interfaces, Input, output ,
bidirectional, power or ground port specification analog or digital pin etc

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Regularity
• Divide a system through hierarchy alone cannot solve the
complexity.

• We may divide the system into large number of submodules.

• With regularity as guide, a designer always tries to divide the

hierarchy into a set of similar blocks.

• Regularity can exist at all levels of design hierarchy

• Circuit level: Uniformly sized transistors can be used

• Gate Level: Logic gates

• Logic Level: RAMs and ROMs

• Architectural Level: Identical Cores.

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Locality

• Modularity and Locality together are a form of information

hiding which reduces complexity
Locality means temporal locality or adherence to a clock or
timing protocol
Examples:

• Analog blocks (ADC and DAC are place adjacent to I/O

pads)

• Floor Planning

• Routing
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Handcrafted Mask Layout
• Handcrafted Mask-Level Layout is the layout of functional subsystems at
the mask level.

• It is the oldest form of chip design and still the most widely used by
semiconductor vendors.

• The design is divided among designers with expertise in logic, circuit,

and process details.

• This has progressed from cutting RUBILITH3 (A two-layer photographic

film), to drawing on MYLAR (Clear polyester drafting film) and digitizing.

• Attending to each transistor and optimizing layout and circuit

parameters, the highest performance and smallest die size results.

45
• Extremely time-consuming due to hundreds of thousands or
millions of transistors.

• Total freedom is allowed at the physical level, the structural

specification and hence the behavioral description may differ
from that required.

46
 Gate array design
• Gate arrays are currently enjoying widespread popularity as an
LSI¬VLSI implementation medium.
• This arises through a combination of readily available vendors,
design tools, and a compatibility with TTL design that makes it
easy for the system designer to transfer a design to silicon with
the minimum amount of effort
• Gate arrays come in various flavors, but can be categorized by
a design that uses a large number of identical "sites,"
• each site consisting of a number of circuit elements.
• In CMOS, these sites consist of a number of n-transistors and
p-transistors.
• Some typical sites are shown in Fig. 6.2.

47
48
49
50
A typical gate array floor plan

51
gate array design flow chart

52
 Standard cell design
• Standard cell systems rely on a set of predefined
logic/circuit cells to complete a design

Typical standard cell floor plan

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Standard cell formats
54
 Symbolic Layout Methods
• Design methods that simplify lower level details
of IC design by hiding process design rules and
capturing structural and physical domain
information in loose format.
• These are the symbolic layout approaches.
• This allows simplified design at very low level of
design hierarchy

55
 Testing
• A critical factor in all LSI and VLSI design is the need to incorporate
methods of testing circuits.
• This task should proceed concurrently with any architectural considerations.
• Fig. 6.13a shows a combinational circuit with n-inputs.
• To test this circuit exhaustively a sequence of 2n inputs (or test vectors) must
be applied and observed to fully exercise the circuit.
• This combinational circuit is converted to a sequential circuit with addition of
m-storage latches, as shown in Fig. 6.13b.
• The state of the circuit is determined by the inputs and the previous state. A
minimum of 2n+m test vectors must be applied to exhaustively test the
circuit.

56
 Three main areas are of importance in Testing:
➢ Test generation
➢ Test verification
➢ Design for test.

Test generation relates to the problems of the generation ofa

number (minimum) of tests’ to verify the behavior of a circuit and
the "goodness" of a given percentage of internal nodes.
The problem of test verification is concerned with finding
measures of the effectiveness of a given set of tests.
This is commonly gauged by performing "fault simulations."
Design for test is the task of designing circuits from the outset, so
that the previous two endeavors are limited in magnitude. 57
 Fault models

"Stuck-At" model
• With this model, a faulty gate input is modeled as a Stuck-At-0 (S-A-0) or a Stuck-At-1
(S-A-1) value
• fault coverage relates to the number of S-A-0 or S-A-1 faults that could be detected by
the input sequence as a percentage of the total number of single faults that might occur.
Short or open circuited faults
• Many faults are caused by short- or open-circuited networks

• In Fig. it can be seen that short Sl is modeled

• by a S-A-0 fault at input A,
• while short S2 modifies the function of the gate.

• Faults should be modeled at the transistor level, as

it is only at this level that the complete circuit
structure is known.
• Test generation must be done in such a way as to
take account of possible shorts and open circuits
at the switch level

58
• A particular problem that arises with CMOS is that it is possible
• for a fault to convert a combinational circuit into a sequential circuit.
• This is illustrated for the case of a 2-input NOR gate in which one of the transistors is
rendered ineffective (stuck open or stuck closed). This might be due to a missing source,
drain, or gate connection. If one of then-transistors (A connected to gate) is stuck open,
then the function displayed by the gate will be

• where F is the previous state of the gate. Similarly if the B n transistor is missing, the
function is

• If either p-transistor is missing, the node would be arbitrarily charged until one of the n-
transistors discharged the node
• This problem has caused researchers to search for new methods of test generation to
detect such behavior

59
A model for CMOS
circuits that allows
test generation using
methods such as the D-
algorithm

60
 Design for testability
• The key to designing circuits that are testable are two concepts
called controllability and observability.
• Simply stated, controllability is the ability to set and reset every
node internal to the circuit.
• Observability is the ability to observe either directly or indirectly
the state of any node in the circuit.
• There are three main approaches to what is commonly called
"design for testability."
• These may be categorized as:
➢ Ad hoc testing
➢Structured design for testability
➢Self-test and built-in testing.

61
 Ad hoc testing

• The techniques grouped under the ad hoc category are basically techniques to reduce the
combinational explosion of testing.
• Common techniques involve partitioning large sequential circuits and adding test points.
• Long counters are good examples of circuits that can be partitioned into smaller
counters that may be exercised with fewer test vectors.
• Another technique classified in this category is the use of the bus .

62
 Structured design for testability
• A popular approach is called Level Sensitive Scan Design or the LSSD approach, introduced
by IBM
• The latches in the circuit are all what are termed "shift register latches" or SRLs.
• In the normal mode of operation, the registers act as the regular storage latches in the circuit.
• In the test-mode, all of the latches in the circuit are connected in series.
• In this mode, data may be shifted into or out of the cascaded registers.
• With this capability, testing is reduced to inputting a known sequence (controllability),
exercising the combinational circuitry and storing the results, and shifting the stored values
out of the register (observability).

LSSD Testing

63
 Structured design for testability

A static latch based on the static-D latch

discussed in Fig. 6.18a.
D is the regular input to the latch, while I
feeds from the Q of the preceding latch in
the chain.
Note that a 2-input mul tiplexer has been
added to the circuit.
It may be possible to implement this as
shown in Fig. 6.18b, as the shift path can
be relatively slow.
Further versions are shown in Fig. 6.18c
and 6.18d 64
LSSD Implementations

65
 Self-test and built-in test
• One method of incorporating a built-in test module is to use signature analysis or cyclic
redundancy checking.
• This involves the use of a linear feedback shift register shown in Fig. 6.19
• After initialization, the value in the register will be a function of the value and number of
latch inputs and the counting function of the signature analyzer
• A good part will have a particular number or signature in the register.
• A bad part will have a different number in the register.
• Signature analysis can be merged with the LSSD technique to create a structure known as
BILBO - for Built-In Logic Block.

66
 Self-test and built-in test
• A 3-bit register is shown with the associated circuitry.
• In mode A (C0 = C1 = 1), the registers act as conventional parallel registers.
• In mode B (C0 = C1 = 0), the registers act as scan registers.
• In mode C (C0 = 1 C1 = O), the registers act as a signature analyzer or pseudo-random
sequence generator (PRSG).
• The registers are reset if C0 = O and C1 = 1.
• Thus a complete test generation and observation arrangement can be implemented as
shown in Fig. 6.21

67
 Design for Autonomous Test
• Another approach to built-in test is called
Design for Autonomous Test.
• In this approach, modules are partitioned into
small modules, which are then tested
exhaustively.
• The main method for partitioning involves
the use of multiplexers.
• Fig. 6.22a shows a typical circuit with
multiplexers included.
• Fig. 6.22b shows the circuit configured for
normal use, while Fig. 6.22c shows the circuit
configured to test module A.
• No fault models or test generation techniques
are required for this technique.
• A complete module would include a pattern Multiplexer segmenting for
autonomous tests
generator in the form of a linear feedback shift
register, a signature analyzer, and test control
circuitry.
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End of Module 5

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