MICROCONTROLLER & ITS APPLICATION
PABITRA MANDAL
LECTURER IN ETCE
RAGHUNATHPUR GOVERNMENT POLYTECHNIC
(Special thanks to my beloved students of 2025 batch EE)
8051 INTERRUPTS
8051 supports 5 interrupts.
2 External Interrupts are on the following pins
𝐼𝑁𝑇1, 𝐼𝑁𝑇𝑂
2 Internal Timer interrupts are:
Timer 1 Overflow Interrupt
Timer 0 Overflow Interrupt
1 Serial Port Interrupt (Common for RI or TI)
All interrupts are vectored i.e. they cause the program to execute an ISR from a pre-
determined address in the Program Memory. this Interrupts are controlled mainly by IE and
IP SFR's and also by some bits of TCON SFR.
Timer Overflow Interrupts (TF1 and TFO)
When any of the 2 Timers overflow, their respective bit TFX (TF1 or TFO) is set in TCON SFR.
If Timer Interrupts are enabled then the timer interrupt occurs.
The TFX bits are cleared when their respective ISR is executed.
Serial Port Interrupt (RI or TI)
While receiving serial data, when a complete byte is received the RI (receive interrupt) bit is
set in the SCON.
During transmission, when a complete byte is transmitted the TI (transmit interrupt) bit is
set in the [Link] of these events can cause the Serial Interrupt (provided Serial Interrupt
is enabled).
The RI/TI bit is not cleared automatically on executing the ISR. The program should explicitly
clear this bit to allow further Serial Interrupts.
External Interrupts ( 𝑰𝑵𝑻𝟏 and 𝑰𝑵𝑻𝑶)
Pins 𝑰𝑵𝑻𝟏 and 𝑰𝑵𝑻𝟎 are inputs for external interrupts.
These interrupts can be ve edge or low-level triggered depending upon the ITO and IT1 bit in
TCON SFR. (ITX = 1-ve edge triggered) When any of these interrupts occur the respective bits
TE1 or IEO are set in the TCON SFR. If External Interrupts are enabled then the ISR is
executed from the respective address.
Interrupt Sequence
The following sequence is executed to service an interrupt: Address of next instruction of
the main program i.e. PC is Pushed into the Stack. All interrupts are disabled, by making EA
bit in IE SFR 0. Program Control is shifted to the Vector Address (location) of the ISR. The ISR
begins.
INTERRUPT PRIORITIES
8051 has only two priority levels for the interrupts: Low
and High. Interrupt priorities are set using the IP SFR.
As the name suggests, a high priority interrupt can
interrupt a low priority interrupt. It two or more
interrupts at the same level occur simultaneously then
priorities are decided as follows:
8051 PROGRAMMING
Q1. Write a Program to add the contents of Internal RAM locations 40H and
41H. Store Result at 42H and Carry at 43H.
MOV 43H, #O0H ; Initialize Carry as "0"
MOV A, 40H ; Read first number
ADD A, 41H ; Add second number
JNC SKIP ; If no Carry, directly store the Sum
INC 43H ; Store Carry as "1"
SKIP: MOV 42H, A ; Store Sum
HERE: SJMP HERE ; End of program
Q2. Write a Program to multiply the numbers B2H and 2FH. Store
Result in registers RO (LSB) and R1 (MSB) of Bank 2.
SOLN: MOV A, #0B2H ; Read first number
MOV OFOH, #2FH ; Read second number
MUL AB ; multiply the operands
SETB PSW.4 ; Select Bank
CLR PSW.3
MOV RO, A ; store LSB of result
MOV R1, OFOH ; store MSB of result
HERE: SJMP HERE ; End of program
[Link] to add a series of 10 numbers. The series begins from location 20H in
Internal RAM. Store the result at locations 30 and 31H.
SOLN: MOV RO, #20H ; Initialize Source address
MOV R1, #0AH ; Initialize count of 10
CLR A ; A register will accumulate the Sum
MOV OFOH, #00H ; B register will accumulate the Carry
REPEAT: ADD A, @RO ; Add the current element
JNC SKIP ; If no carry, then directly proceed ahead
INC OFOH ; If there is a carry, increment B Register
SKIP: INC RO ; Increment source address
DJNZ R1, REPEAT ; Decrement count. If Count is NOT ZERO then repeat.
MOV 30H, A ; Store Sum
MOV 31H, OFOH ;Store Carry
HERE: SJMP HERE