NON- CONTIGUOUS MEMORY

ALLOCATION

R Lakshman Naik

Operating System Concepts – 9th Edition 8.1 Silberschatz, Galvin and Gagne ©2013
 Non-Contiguous Memory Allocation
Segmentation

Paging

Structure of Page Table

Operating System Concepts – 9th Edition 8.2 Silberschatz, Galvin and Gagne ©2013
 Segmentation
Memory-management scheme that supports user view of memory
A program is a collection of segments
A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays

Operating System Concepts – 9th Edition 8.3 Silberschatz, Galvin and Gagne ©2013
 User’s View of a Program

Operating System Concepts – 9th Edition 8.4 Silberschatz, Galvin and Gagne ©2013
 Logical View of Segmentation

4
1

3 2
4

user space physical memory space

Operating System Concepts – 9th Edition 8.5 Silberschatz, Galvin and Gagne ©2013
 Segmentation Architecture
Logical address consists of a two tuple:
<segment-number, offset>,

Segment table – maps two-dimensional physical addresses; each

table entry has:
base – contains the starting physical address where the
segments reside in memory
limit – specifies the length of the segment

Segment-table base register (STBR) points to the segment

table’s location in memory

Segment-table length register (STLR) indicates number of

segments used by a program;
segment number s is legal if s < STLR

Operating System Concepts – 9th Edition 8.6 Silberschatz, Galvin and Gagne ©2013
 Segmentation Architecture (Cont.)
Protection
With each entry in segment table associate:
 validation bit = 0  illegal segment
 read/write/execute privileges
Protection bits associated with segments; code sharing
occurs at segment level
Since segments vary in length, memory allocation is a
dynamic storage-allocation problem
A segmentation example is shown in the following diagram

Operating System Concepts – 9th Edition 8.7 Silberschatz, Galvin and Gagne ©2013
 Segmentation Hardware

Operating System Concepts – 9th Edition 8.8 Silberschatz, Galvin and Gagne ©2013
 Paging
Physical address space of a process can be noncontiguous;
process is allocated physical memory whenever the latter is
available
Avoids external fragmentation
Avoids problem of varying sized memory chunks
Divide physical memory into fixed-sized blocks called frames
Size is power of 2, between 512 bytes and 16 Mbytes
Divide logical memory into blocks of same size called pages
Keep track of all free frames
To run a program of size N pages, need to find N free frames and
load program
Set up a page table to translate logical to physical addresses
Backing store likewise split into pages
Still have Internal fragmentation

Operating System Concepts – 9th Edition 8.9 Silberschatz, Galvin and Gagne ©2013
 Address Translation Scheme
Address generated by CPU is divided into:
Page number (p) – used as an index into a page table which
contains base address of each page in physical memory
Page offset (d) – combined with base address to define the
physical memory address that is sent to the memory unit

page number page offset

p d
m -n n

For given logical address space 2m and page size 2n

Operating System Concepts – 9th Edition 8.10 Silberschatz, Galvin and Gagne ©2013
 Paging Hardware

Operating System Concepts – 9th Edition 8.11 Silberschatz, Galvin and Gagne ©2013
 Paging Model of Logical and Physical Memory

Operating System Concepts – 9th Edition 8.12 Silberschatz, Galvin and Gagne ©2013
 Implementation of Page Table
Page table is kept in main memory
Page-table base register (PTBR) points to the page table
Page-table length register (PTLR) indicates size of the page
table
In this scheme every data/instruction access requires two
memory accesses
One for the page table and one for the data / instruction
The two memory access problem can be solved by the use of
a special fast-lookup hardware cache called associative
memory or translation look-aside buffers (TLBs)

Operating System Concepts – 9th Edition 8.13 Silberschatz, Galvin and Gagne ©2013
 Implementation of Page Table (Cont.)
Some TLBs store address-space identifiers (ASIDs) in each
TLB entry – uniquely identifies each process to provide
address-space protection for that process
Otherwise need to flush at every context switch
TLBs typically small (64 to 1,024 entries)
On a TLB miss, value is loaded into the TLB for faster access
next time
Replacement policies must be considered
Some entries can be wired down for permanent fast
access

Operating System Concepts – 9th Edition 8.14 Silberschatz, Galvin and Gagne ©2013
 Associative Memory

Associative memory – parallel search

Page # Frame #

Address translation (p, d)

If p is in associative register, get frame # out
Otherwise get frame # from page table in memory

Operating System Concepts – 9th Edition 8.15 Silberschatz, Galvin and Gagne ©2013
 Paging Hardware With TLB

Operating System Concepts – 9th Edition 8.16 Silberschatz, Galvin and Gagne ©2013
 Memory Protection
Memory protection implemented by associating protection bit
with each frame to indicate if read-only or read-write access is
allowed
Can also add more bits to indicate page execute-only, and
so on
Valid-invalid bit attached to each entry in the page table:
“valid” indicates that the associated page is in the
process’ logical address space, and is thus a legal page
“invalid” indicates that the page is not in the process’
logical address space
Or use page-table length register (PTLR)
Any violations result in a trap to the kernel

Operating System Concepts – 9th Edition 8.17 Silberschatz, Galvin and Gagne ©2013
 Valid (v) or Invalid (i) Bit In A Page Table

Operating System Concepts – 9th Edition 8.18 Silberschatz, Galvin and Gagne ©2013
 Structure of the Page Table
Memory structures for paging can get huge using straight-
forward methods
Consider a 32-bit logical address space as on modern
computers
Page size of 4 KB (212)
Page table would have 1 million entries (232 / 212)
If each entry is 4 bytes -> 4 MB of physical address space /
memory for page table alone
 That amount of memory used to cost a lot
 Don’t want to allocate that contiguously in main memory
Hierarchical Paging
Hashed Page Tables
Inverted Page Tables

Operating System Concepts – 9th Edition 8.19 Silberschatz, Galvin and Gagne ©2013
 Hierarchical Page Tables

Break up the logical address space into multiple page

tables
A simple technique is a two-level page table
We then page the page table

Operating System Concepts – 9th Edition 8.20 Silberschatz, Galvin and Gagne ©2013
 Two-Level Page-Table Scheme

Operating System Concepts – 9th Edition 8.21 Silberschatz, Galvin and Gagne ©2013
 Two-Level Paging Example
A logical address (on 32-bit machine with 1K page size) is divided into:
a page number consisting of 22 bits
a page offset consisting of 10 bits

Since the page table is paged, the page number is further divided into:
a 12-bit page number
a 10-bit page offset

Thus, a logical address is as follows:

where p1 is an index into the outer page table, and p2 is the

displacement within the page of the inner page table
Known as forward-mapped page table

Operating System Concepts – 9th Edition 8.22 Silberschatz, Galvin and Gagne ©2013
 Address-Translation Scheme

Operating System Concepts – 9th Edition 8.23 Silberschatz, Galvin and Gagne ©2013
 64-bit Logical Address Space

Even two-level paging scheme not sufficient

If page size is 4 KB (212)
Then page table has 252 entries
If two level scheme, inner page tables could be 210 4-byte entries
Address would look like

Outer page table has 242 entries or 244 bytes

One solution is to add a 2nd outer page table
But in the following example the 2nd outer page table is still 234 bytes in
size
 And possibly 4 memory access to get to one physical memory
location

Operating System Concepts – 9th Edition 8.24 Silberschatz, Galvin and Gagne ©2013
 Three-level Paging Scheme

Operating System Concepts – 9th Edition 8.25 Silberschatz, Galvin and Gagne ©2013
 Hashed Page Tables
Common in address spaces > 32 bits
The virtual page number is hashed into a page table
This page table contains a chain of elements hashing to the same
location
Each element contains (1) the virtual page number (2) the value of the
mapped page frame (3) a pointer to the next element
Virtual page numbers are compared in this chain searching for a
match
If a match is found, the corresponding physical frame is extracted
Variation for 64-bit addresses is clustered page tables
Similar to hashed but each entry refers to several pages (such as
16) rather than 1
Especially useful for sparse address spaces (where memory
references are non-contiguous and scattered)

Operating System Concepts – 9th Edition 8.26 Silberschatz, Galvin and Gagne ©2013
 Hashed Page Table

Operating System Concepts – 9th Edition 8.27 Silberschatz, Galvin and Gagne ©2013
 Inverted Page Table

Rather than each process having a page table and keeping track
of all possible logical pages, track all physical pages
One entry for each real page of memory
Entry consists of the virtual address of the page stored in that
real memory location, with information about the process that
owns that page
Decreases memory needed to store each page table, but
increases time needed to search the table when a page
reference occurs
Use hash table to limit the search to one — or at most a few —
page-table entries
TLB can accelerate access
But how to implement shared memory?
One mapping of a virtual address to the shared physical
address

Operating System Concepts – 9th Edition 8.28 Silberschatz, Galvin and Gagne ©2013
 Inverted Page Table Architecture

Operating System Concepts – 9th Edition 8.29 Silberschatz, Galvin and Gagne ©2013
 Thank you

Operating System Concepts – 9th Edition Silberschatz, Galvin and Gagne ©2013