ELECTRONIC CIRCUIT ANALYSIS LABORATORY

LIST OF EXPERIMENTS
(HARD WARE)

[Link] Name of the Experiment

1 Determination of fT of a given transistor

2 Voltage-Series Feedback Amplifier

3 Current-Shunt Feedback Amplifier

4 RC Phase Shift

5 Colpitt’s Oscillator

6 Two Stage RC Coupled Amplifier

7 Darlington Pair Amplifier

8 Boot strapped Emitter Follower

9 Class A Series-fed Power Amplifier

10 Transformer-coupled Class A Power Amplifier

11 Class B Push-Pull Power Amplifier

12 Complementary Symmetry Class B Push-Pull Power Amplifier

13 Single Tuned Voltage Amplifier

14 Double Tuned Voltage Amplifier
 LIST OF EXPERIMENTS
(SIMULATION)

[Link] Name of the Experiment

1 Determination of fT of a given transistor

2 Voltage-Series Feedback Amplifier

3 Current-Shunt Feedback Amplifier

4 RC Phase Shift

5 Colpitt’s Oscillator

6 Two Stage RC Coupled Amplifier

7 Darlington Pair Amplifier

8 Boot strapped Emitter Follower

9 Class A Series-fed Power Amplifier

10 Transformer-coupled Class A Power Amplifier

11 Class B Push-Pull Power Amplifier

12 Complementary Symmetry Class B Push-PullPowerAmplifier

13 Single Tuned Voltage Amplifier

14 Double Tuned Voltage Amplifier

ADDITIONALEXPERIMENTS

[Link] Name of the experiment

1 SERIES VOLTAGE REGULATOR
2 SHUNT VOLTAGE REGULATOR
 HARDWARE

EXPERIMENT NO.1

DETERMINATION OF fT OF GIVEN TRANSISTOR

AIM:
To determine the fT of a given transistor

APPARATUS REQUIRED:
1. TransistorBC107: 1 No
2. Capacitors10µf/25V: 3No‟s
3. Resistors1kΩ,2.2kΩ,4.7kΩ,8.2kΩ,33kΩ:1Noeach
4. Function generator: 1 No
5. 20MHz Dual trace oscilloscope: 1 No
6. Bread board : 1No
7. 0-30 V DC power supply: 1 No
8. Connecting wires: 1set

THEORY:

Common Emitter amplifier has the emitter terminal as the common terminal
Between input and output. The emitter base junction is forward biased and collector base
junction is reverse biased, so that transistor remains in active region throughout the operation.
When a sinusoidal AC signal is applied at input terminals of circuit during positive half cycle the
forward bias of base emitter junction VBE is increased resulting in an increase in IB, The
collector current IC is increased by β times the increase in IB, VCE is correspondingly
decreased. i.e., output voltage gets decreased. Thus in a CE amplifier a positive going signal is
converted into a negative going output signal i.e., 180 0 phase shift is introduced between output
and input signal and it is an amplified version of input signal.

Characteristics of CE amplifier:

1. Large current gain (AI)

2. Large voltage gain (AV)

3. Large power gain (AP=[Link])

4. Phase shift of 1800

5. Moderate input & output impedances.

CIRCUITDIAGRAM:

MODELGRAPH:
TABULAR FORM:

Input Voltage Vin =10Mv

[Link]. Frequency VOUT(volt) A=Vout/VIN Gain=20logVout/VIN(db)

1. 20Hz 0.5 10 20
2. 50Hz 1.3 26 28.3
3. 100Hz 2.3 46 33.25
4. 200Hz 3.8 76 37.61
5. 500Hz 5 100 40
6. 1KHz 5.2 104 40.34
7. 2KHz 5.2 104 40.34
8. 5KHz 5.2 104 40.34
9. 10KHz 5.2 104 40.34
10. 20KHz 5.2 104 40.34
11. 50KHz 4.7 94 39.46
14. 100KHz 3.5 70 36.90
15. 200KHz 2 40 32.04
16. 500KHz 0.8 16 24.08
17. 1MHz 0.4 8 18.06

OBSERVATIONS:

[Link] gain (Av) = 40.34 db

[Link] cut-off frequency (FL) = 20HZ
[Link] cut-off frequency (FH)= 500kHZ
[Link] width (B.W) = (FH– FL) = 480KHZ
[Link] band width product fT=Av(B.W)=19.26kHZ
The voltage gain of the amplifier is given calculate the gain in by Gain=20 log Av
Where, Vo is the output voltage. VS is input voltage of applied AC signal.

PROCEDURE:
1. Connect the circuit as shown in the circuit diagram.
2. Connect the signal generator output to input terminals of the circuit and CH-I of dual trace
CRO.
3. Connect the output terminal of the circuit CH-II of the dual trace CRO
4. Set the power supply voltage to 9V and connect to the circuit.
5. Set the signal generator output sine wave of 100Hz at 10mV constant.
6. Vary the function generator frequency from 100Hz to 500kHz (as per in the given tabular
form) and note the corresponding output voltage.
7. Calculation the gain AV=Vo/Vi.
8. Plot the graph frequency versus gain(dB) on a semi-log sheet.

RESULT:

Hence the fT of a given transistor are Observed.

 EXPERIMENT NO.2

VOLTAGE-SERIES FEEDBACK AMPLIFIER

AIM: -To obtain the frequency response of VOLTAGE SERIES FEEDBACK amplifier and
measure its bandwidth.

APPARATUS:-
1. Transistor (BC-107)-1no
2. Breadboard
3. Resistors–2.2KΩ,1KΩ -2,5.6KΩ,1.5KΩ
4. Capacitors -10µf–2no
5. C.R.O. with probes
6. Function Generators
7. Regulated Power Supply
8. Connecting wires

THEORY:
In voltage- series feedback amplifier the voltage developed in the output is in series
with the input voltage as far as the base –emitter junction is concerned. This is a single stage RC
coupled amplifier without emitter by pass capacitor across RE. R1and R2 provides the base bias.
The emitter follower inherently exhibits 100 percent negative feedback since the voltage at the
emitter follows the input voltage.
As the output voltage is taken across RE=RL, the feedback ratio, β=RE/RL=1.

The emitter follower simultaneously increases input resistance and decreases output
resistance.
Therefore, the overall voltage gain, Af=A/1+A.
CIRCUITDIAGRAM:

VOLTAGESERIESFEEDBACKAMPLIFIER

PROCEDURE:-

1. The circuit is connected as per the circuit diagram.

2. A Sinusoidal input of 50mv peak to peak is applied at 1KHz frequency from

Function Generator and O/P waveform is observed on the C.R.O.

3. VCC=10Volts is given to the circuit from the R.P.S.

4. The Output Voltage VO is directly read from the C.R.O. screen.

5. The frequency of the I/P signal is changed in steps and the individual O/P
voltages are noted down from the C.R.O.

6. A Graph is plotted between 20log VO/VI and frequency.

OBSERVATIONS:-

VIN=1volt at 1KHz

S VFOUT(volt) A=Vout/VIN Gain=20 log Vout/VIN(db)

120Hz 0.4 0.4 -7.95

250Hz 0.4 0.4 -7.95

3100Hz 0.4 0.4 -7.95

4200Hz 0.4 0.4 -7.95

5500Hz 0.4 0.4 -7.95

61KHz 0.4 0.4 -7.95

72KHz 0.4 0.4 -7.95

85KHz 0.4 0.4 -7.95

910KHz 0.4 0.4 -7.95

120KHz 0.4 0.4 -7.95

150KHz 0.4 0.4 -7.95

1 1 0.4 0.4 -7.95

1 2 0.4 0.4 -7.95

1 5 0.4 0.4 -7.95

11MHz 0.4 0.4 -7.95

PRECAUTIONS:-

1. The continuity of wires and C.R.O. probes must be checked.

2. The voltages levels in the RPS must be kept in minimum position before switching
it “ON” or “OFF”.

3. The terminals of the transistor should be identified properly.

4. Readings should be taken without errors.

5. Inter connections should not be made on the breadboard with power switched on.

RESULT:-

Hence the frequency response of voltage series feedback amplifier is obtained.

 EXPERIMENTNO.3

CURRENT SERIES FEEDBACK AMPLIFIER

AIM: -
To obtain the frequency response of CURRENT SERIES FEEDBACK amplifier and
measure its bandwidth.

APPARATUS:-
1. Transistor(BC-107)-1no
2. Breadboard
3. Resistors–22KΩ,1KΩ-2,3.3KΩ,5.6KΩ
4. Capacitors -10µf–2no,
5. C.R.O. with probes
6. Function Generators
7. Regulated Power Supply
8. Connecting wire

THEORY:-

In current series feedback, a voltage is developed which is proportional to the output current.
This is called current feedback even though it is a voltage that subtracts from the input voltage
.Because of the series connection at the input and output, the input and output resistance gets
increased. This type of amplifier is called trans-conductance amplifier. In this circuit to place a
resistor Re between emitter lead of a common emitter amplifier and ground.

When Re is properly bypassed with a large capacitor (Ce), the output voltage is Voand the
voltage gain without feedback is A. Resistor (Re ) d.c. bias stabilization, but no a.c feedback.
When the Ce is removed, an a.c. voltage will be developed across Re due to the emitter current
flowing through Re and this current is approximately equals to the output collector current. This
voltage drop across Re will serve too decrease the voltage between base and emitter, so that the
output voltage will decrease to Vo, The gain of the amplifier with negative feedback is now Af.
CIRCUIT DIAGRAM:

CURRENTSERIESFEEDBACKAMPLIFIER

OBSERVATIONS:-

VIN=1volt at1KHz

[Link]. Frequency VOUT(volt) A=Vout/VIN Gain=20logVout/VIN(db)

1. 20Hz 0.20 4 12.04

2. 50Hz 0.22 4.4 12.86
3. 100Hz 0.22 4.4 12.86
4. 200Hz 0.22 4.4 12.86
5. 500Hz 0.22 4.4 12.86
6. 1KHz 0.22 4.4 12.86
7. 2KHz 0.22 4.4 12.86
8. 5KHz 0.22 4.4 12.86
9. 10KHz 0.22 4.4 12.86
10. 20KHz 0.22 4.4 12.86
11. 50KHz 0.19 3.8 11.59
14. 100KHz 0.16 3.2 10.10
15. 200KHz 0.14 2.8 8.94
16. 500KHz 0.10 2 6.02
17. 1MHz 0.06 1.2 1.58
PROCEDURE:-

1. The circuit is connected as per the circuit diagram.

2. A Sinusoidal input of 50mv peak to peak is applied at1KHz frequency from

Function Generator and O/P waveform is observed on the C.R.O.

3. The Output Voltage VO is directly read from the C.R.O. screen.

4. The frequency of the I/P signal is changed in steps and the individual O/P
voltages are noted down from the C.R.O.

5. A Graph is plotted between 20log VO/Vi and frequency.

PRECAUTIONS:-

1. The continuity of wires and C.R.O. probes must be checked.

2. The voltages levels in the RPS must be kept in minimum position before switching
it “ON” or “OFF”.

3. The terminals of the transistor should be identified properly.

4. Readings should be taken without errors.

5. Inter connections should not be made on the breadboard with power switched on.

RESULT:-

Hence the frequency response of CURRENT SERIES FEEDBACK amplifier is

obtained and bandwidth is calculated.
 EXPERIMENTNO.4(a)

RC PHASE SHIFT OSCILLATOR

AIM:-
To design a RC PHASE SHIFT OSCILLATOR for a given frequency.

APPARATUS:-

i. Transistor(BC-107)-1no
2. Bread board

3. Resistors–1.5KΩ-2,1KΩ-2,15KΩ,3.3KΩ,5.6KΩ

4. Capacitors – 0.01µf–3,4.7µf,

5. C.R.O. with probes

6. Regulated Power Supply

7. Connecting wire

THEORY:

All the oscillators using tuned LC circuits operate well at high frequencies. At low
frequencies, as the inductors and capacitors required for the time circuit would be very bulky.
RC oscillators are more suitable.
In this RC oscillator the required phase shift of1800 in the feedback loop from output to
input is obtained by using R and C components instead of tank circuit.
A common emitter amplifier is followed by three sections of RC phase shift network, the
out of the last section being returned to the input. In order to make the three RC sections
identical, R3 is chosen as R3=R-RI, where Riis the input impedance of the circuit.
If the values of R and C are chosen so that, for the given frequency Fr, the phase shifts of
each RC section is [Link] such a R C ladder network produces at otal phase shift of1800
between its input and output voltage for only the given frequency.
Therefore, at the specific frequency fr, the total phase shift from the base of the
transistor around the circuit and back to the base will exactly 3600 and 00.
The RC phase shift oscillator is suitable for audio frequencies only.
 CIRCUITDIAGRAM:

RCPHASE SHIFT OSICILLATOR

PROCEDURE:-

1. The circuit is connected as per the circuit diagram.

2. VCC=10V is given to the circuit from the R.P.S.

3. The Output Voltage VO is directly read from the C.R.O. screen.

4. The time period (T) of the O/P waveform is observed from the C.R.O. is measured

5. Theoretical and practical values of frequency are compared.

OBSERVATIONS:-

Theoretical frequency (f) = 1/2πRC√6+4K

K = RC/R= 5.6k/1.5k= 3.3733

f=1/(2∏*1.5*0.01*10-3*√(6+4*3.733))

=2.319 kHz.

Practical frequency (f) =1/T=1/0.476ms

=2.1kHz

PRECAUTIONS:-

 The continuity of wires and C.R.O. probes must be checked.

 The voltages levels in the RPS must be kept in minimum position before switching
it “ON” or “OFF”.

 The terminals of the transistor should be identified properly.

 Readings should be taken without errors.

 Inter connections should not be made on the breadboard with power switched on.

RESULT:-

Hence the output waveform for a RC PHASE SHIFT OSCILLATOR is observed and frequency
of Oscillations is calculated.
 EXPERIMENT NO.4(b)

WIEN BRIDGE OSCILLATOR

AIM:-
To design a WIEN BRIDGE OSCILLATOR for a given frequency.

APPARATUS:-
a. Transistor(BC-107)-1no
b. Breadboard
c. Resistors–1.2KΩ-2,400KΩ,200 KΩ -4,33KΩ,8.2KΩ
d. Capacitors–10µf–2,50µf,53pf
e. C.R.O. with probes
f. Regulated Power Supply
g. Connecting wires

CIRCUITDIAGRAM:

WEINBRIDGE OSCILLATOR
THEORY:-

The circuit consisting of two –stage R C coupled amplifier which provides a phase
shift of 3600 or 00. A balanced bridge is used as feedback network which has no need to provide
any additional phase shift. The feedback network consisting of a lead- lag network (R1- C1and
R2-C2) and a voltage divider (R3-R4). The lead-lag network provides a positive feedback to the
input of the first stage and the voltage divider provides a negative feedback to the emitter of
[Link] ratio of R3 to R4greater than 2 will provide a sufficient gain for the circuit to oscillate at
the desired frequency. This oscillator is used in commercial audio signal generators.

If the bridge is balanced, R3/R4=(R1-JXC1)/[R2(-JXC2)/R2-JXC2]

Where XC1 andXC2 are the reactance of the capacitors.
We get the frequency of oscillation as, fr =1/(2πR1R2 C1C2).
=1/(2πRC),
If R1=R2=RandC1=C2=C.
The amplifier voltage, A=(R3+R4)/R4=R3/R4+1=3.
This corresponding with the feedback network attenuation to equal to 1/3. For sustained
oscillations, A ≥ 3.

PROCEDURE:-
1. The circuit is connected as per the circuit diagram.
2. VCC=10Vis given to the circuit from the R.P.S.

3. Connect the output to C.R.O. and vary R4 till the sustained oscillations are observed.

4. Connect different values of C corresponding to different frequencies.

5. The Output Voltage VO is directly read from the C.R.O. screen.

6. The time period (T) of the O/P waveform is observed from the C.R.O. is measured

Design:

For f=10 KHz.

Let R1=R2= 1.2kΩ.

R4 =200KΩ, R3 = 400 KΩ

The frequency of oscillation is f=1/2∏RC

C = 1 / 2πRC

=1/2πx10x103x200x103=79 PF for 15KHz.

Observations:

Theoretical Practical
C R3 R4
frequency frequency

100PF 400 400 7.957KHz 7.1KHz

PRECAUTIONS:-

 The continuity of wires and C.R.O. probes must be checked.

 The voltages levels in the RPS must be kept in minimum position before switching
it “ON” or “OFF”.

 The terminals of the transistor should be identified properly.

 Readings should be taken without errors.

 Interconnections should not be made on the bread board with power switched on.

RESULT:-

Hence the output waveform for a WIEN BRIDGE OSCILLATOR is observed and the
desired frequency is calculated.
 EXPERIMENT NO.5(a)

HARTLEY OSCILLATOR

AIM:-
To design a HARTLEY OSCILLATOR for a given frequency.

APPARATUS:-
i. Transistor (BC-107)-1no
b. Breadboard
c. Resistors–2.2KΩ-2,47KΩ,10KΩ
d. Capacitors –10µf–2no,50µf-1no
e. Inductance Boxes -2
f. C.R.O. with probes
g. Regulated Power Supply
h. Connecting wires

THEORY:-

Any circuit, which is used to generate a.c. voltage without a.c. input signal, is called
an Oscillator. The circuit consisting LC network (feedback network) which consisting, inductors
L1, L2and capacitor C determines the frequency of the oscillator. Resistors R1, R2 and RE provide
the necessary d.c. bias to the transistor. CE is a bypass capacitor. C1 and C2 are coupling
capacitors. When the supply voltage +Vcc is switched ON, a transient current is produced in
the tank circuit and consequently, damped harmonic oscillations are setup in the circuit. The
oscillatory current in the tank circuit produces a.c. voltage across L1, L2. The LC network
provides1800phase shift and the transistor provides1800phase difference between the input and
output. Therefore the total phase shift is 3600. Thus, at the frequency determinant for the tank
circuit, the necessary condition for sustained oscillations is satisfied.

CIRCUITDIAGRAM:

HARTLEYOSICILLATOR
PROCEDURE:-

1. The circuit is connected as per the circuit diagram.

2. VCC=10V is given to the circuit from the R.P.S.

3. Keep L1=0.6mH, L2=0.6mH

4. Theoretical frequency f=1/(2π√(L1+L2)C) for different values of L1, L2 and C.

5. The Output Voltage VO is directly read from the C.R.O. screen.

6. The time period (T) of the O/P waveform is observed from the C.R.O. is measured.

OBSERVATIONS:-

C=0.1*10-6

Theoretical frequency (f)= 1/(2π√(L1+L2)C)

=1/(2π√(0.6x10-3+0.6x10-3)x0.1x10-6)

= 14.5kHz.

Practical frequency (f)=1/T= 1/(0.08ms).

`=12.5kHz.

RESULT:-

Hence the output waveform for a HARTLEY OSCILLATOR is observed and the desired
frequency is calculated.
 EXPERIMENT NO . 5(b)

COLPITTSOSCILLATOR

AIM:-
To design a COLPITTS OSCILLATOR for a given frequency.

APPARATUS:-
i. TransistorBC-107
2. Breadboard
3. Resistors–2.2KΩ,10KΩ-,1KΩ,220Ω
4. Capacitors–0.1µf–2,4.7µf,10µf-2
5. C.R.O. withprobes
6. Inductor100µH
7. Regulated Power Supply
8. Connectingwires

THEORY:-

Any circuit which is used to generate a.c. voltage without a.c. input signal is called an
Oscillator. The circuit consisting LC network (feedback network) which consisting, inductor L
and capacitors C1,C2 determines the frequency of the oscillator. Resistors R1, R2 and RE provide
the necessary d.c. bias to the transistor. CE is a bypass capacitor. C1 and C2 are coupling
capacitors. When the supply voltage +Vcc is switched ON, a transient current is produced in the
tank circuit and consequently, damped harmonic oscillations are setup in the circuit. The
oscillatory current in the tank circuit produces a.c. voltage across C1, C2. The LC network
provides1800 phase shift and the transistor provides1800 phase difference between the input and
output. Therefore the total phase shift is 3600. Thus, at the frequency determinant for the tank
circuit, the necessary condition for sustained oscillations is satisfied.

CIRCUITDIAGRAM:
 COLPITT’SOSCILLATOR.

PROCEDURE:-

1. The circuit is connected as per the circuit diagram.

2. VCC=10V is given to the circuit from the R.P.S.

3. The Output Voltage VO is directly read from the C.R.O. screen.

4. The time period (T) of the O/P waveform is observed from the C.R.O. is measured

5. Theoretical and practical values of frequency are compared.

PRECAUTIONS:-
1. The continuity of wires and C.R.O. probes must be checked.
2. The voltages levels in the RPS must be kept in minimum position before switching it
“ON” or “OFF”.
3. The terminals of the transistor should be identified properly.
4. Readings should be taken without errors.
5. Inter connections should not be made on the breadboard with power switched on.
OBSERVATIONS:-

Theoretical frequency (f)=1/(2π√LCT)

CT= (C1C2)/(C1+C2)

Ceq = (0.1*0.1*10-12)/(0.2*10-6)=0.05µF

f = 1/ (2∏√100*0.05*10-6)

= 71.7kHz

Practical frequency(f) =1/T= 1/(0.0144ms)= 69.3kHz

RESULT:-
Hence the output waveform for a COLPITTS OSCILLATOR is observed andfrequency of
oscillations is calculated.
 EXPERIMENTNO.6

TWO STAGE RC COUPLED AMPLIFIER

AIM:

To design and stimulate Two Stage RC coupled amplifier circuit

1. Using spice software and calculate voltage gain and frequency response characteristics of
the circuit.

2. To verify Two Stage RC coupled amplifier circuit practically using hardware and
calculate voltage gain and frequency response.

APPARATUS:

[Link](BC-107)-1no

2.R.P.S (0-30V).

[Link]-
1kΩ(2),3.3kΩ(2),560Ω(2),33kΩ(2),220Ω(1),5.6kΩ(1).

4.C.R.O.

[Link]-49µf(2),10µf(3).

[Link] Board.

[Link] Wires.

THEORY:

The cascade amplifier consists of a common emitter amplifier stage in series with a
common base amplifier stage as shown in the figure. It is one approach to solve the low
impedance problem of a common base circuit. Transistor, T 1 and its associated components
operate as a common emitter amplifier stage. While the circuit T 2functions as a common base
output stage. The cascade amplifier gives the high input impedance of a common emitter
amplifier, as well as the good voltage gain and high frequency performance of a common base
circuit.

For the DC bias conditions of the circuit, it is seen that the emitter current for T 1 is set by
VE1and RE1. Controller current IC1approximately equals IE 1and IE 2is same as IC1. Therefore
IC2approximately equals [Link] current remains constant regardless of the level of V B2as long as
VCE1remains large enough for current operation of T1.
CIRCUITDIAGRAM:

MODELGRAPHS:
OBSERVATIONS:-

VIN=25mV

[Link]. Frequency V1(volt) V2(volt) Gain1=20log Gain2=20log

V0/V1(db) V0/V2(db)
1. 20Hz 0.4 0.85 24 30.6
2. 30Hz 0.45 1 25 32
3. 50Hz 05 1.05 26 32.4
4. 100Hz 0.5 1.1 26 33.8
5. 200Hz 0.5 1.25 26 33.8
6. 300 0.5 1.25 26 33.8
7. 500 0.5 1.25 26 33.8
8. 1K 0.5 1.25 26 33.8
9. 2K 0.5 1.25 26 33.8
10. 3K 0.5 1.25 26 33.8
11. 5K 0.5 1.25 26 33.8
12. 10K 0.5 1.25 26 33.8
13. 20K 0.5 1.1 26 32.8
14. 30K 0.5 1.05 26 32.4
15. 50K 0.45 1 25 32
16. 100K 0.35 0.6 18 27.6
17. 200K 0.2 0.3 12 22
18. 500K 0.1 0.2 10 18
19. 1000K 0.075 0.1 8 12

PROCEDURE:-
1. The circuit is connected as per the circuit diagram.
2. A Sinusoidal input of 20mV peak to peak is applied from Function Generator and O/P
waveform is observed on the C.R.O.
3. The Output Voltage VO is directly read from the C.R.O. screen.
4. The frequency of the I/P signal is changed in steps and the individual O/P voltages are
noted down from the C.R.O.
5. Observe and vary frequency of signal generator from 10Hz to1MHz and tabulate them.
6. Now, connect the first stage and observe the Output at output terminals of second stage.
7. Now, Keep the output frequency constant at 1 kHz and observe the output of second stage
on C.R.0.
8. Increase the amplitude of output signal till the distortion.
PRECAUTIONS:-
1. The continuity of wires and C.R.O. probes must be checked.
2. The voltages levels in the RPS must be kept in minimum position before switching it
“ON” or “OFF”.
3. The terminals of the transistor should be identified properly.
4. Readings should be taken without errors.
5. Inter connections should not be made on the breadboard with power switched on.

RESULT:-

Hence the frequency response of two stage R.C coupled amplifier is obtained and
bandwidth is calculated.
 EXPERIMENT NO . 7

DARLINGTONPAIRAMPLIFIER

AIM:

To perform the frequency response of a Darlington amplifier. Calculate gain and Bandwidth.

APPARATUS REQUIRED:

1. Transistor (NPN,Si)-(BC547) : 2nos.

2. Electrolytic Capacitor -10µF :2nos.
3. Carbon film Resistors-82kΩ,22kΩ,2.2kΩ,390Ω,1kΩ :[Link]
4. 20MHz Dual trace CRO :1no.
5. 1MHz Function Generator :1no.
6. (0–30V) DC Power Supply:1no.
7. Connecting wires : 1Lot.

THEORY:
In Darlington connection of transistors, emitter of the first transistor is directly connected to
the base of the second transistor. Because of direct coupling dc output current of the first stage is
(1+hfe) Ib1. If Darlington connection for n transistor is considered, then due to direct coupling the
dc output current for last stage is (1+h fe) n times Ib1. Due to very large amplification factor event
stage Darlington connection has large output current and output stage may have to be a power
stage. As the power amplifiers are not used in the amplifier circuits it is not possible to use more
than two transistors in the Darlington connection.

In Darlington transistor connection, the leakage current of the first transistor and
over all leakage current may be high, which is not desired.
CIRCUITDIAGRAM:

TABULARFORM:
VIN=1voltat1KHz

[Link]. Frequency VOUT(volt) A=Vout/VIN Gain=20logVout/VIN(db)

1. 20Hz 0.20 4 12.04

2. 50Hz 0.22 4.4 12.86
3. 100Hz 0.22 4.4 12.86
4. 200Hz 0.22 4.4 12.86
5. 500Hz 0.22 4.4 12.86
6. 1KHz 0.22 4.4 12.86
7. 2KHz 0.22 4.4 12.86
8. 5KHz 0.22 4.4 12.86
9. 10KHz 0.22 4.4 12.86
10. 20KHz 0.22 4.4 12.86
11. 50KHz 0.19 3.8 11.59
14. 100KHz 0.16 3.2 10.10
15. 200KHz 0.14 2.8 8.94
16. 500KHz 0.10 2 6.02
17. 1MHz 0.06 1.2 1.58
MODELGRAPH:

PROCEDURE:-

1. Connect the circuit diagram as shown in figure. Set the RPS voltage at 12V and input
signal amplitude (sine wave) 50mV, 1 KHz in the function generator.
2. Feed the sine wave signal to the input of the amplifier and observe an amplified
voltage at the output without distortion.{input at CH-1&output at CH-2}
3. By keeping input signal voltage, constant 50mV, select the Ranges witch of FG input
signal frequency from {10 Hz to 1MHz} insteps. Noted own the output Vo peak-to-
peak amplitude of signal for different frequencies in tabular column.
Calculate the Bandwidth from the plot of graph.

RESULT:

Hence the Bandwidth of Darlington pair amplifier is calculated.

 EXPERIMENT NO .8

BOOTSTRAPEMITTERFOLLOWER

AIM:

To measure sweep time and run time of boot strap Emitter Follower.

APPARATUS REQUIRED:
1. Transistors (Si) (BS547) : 2no.
2. Diode (IN4007) : 1no.

3. Ceramic Disc Capacitor 100µF,10nF: [Link]

4. Electrolytic Capacitor 47µF : [Link]
5. 20MHz Cathode Ray Oscilloscope : 1no.

6. 1MHz Signal generator : 1no.

7. Regulated DC power supply(0-30V): 1no.
8. Bread board Trainer Module : 1no.
9. Connecting wires : 1lot

THEORY:

Bootstrap circuit is one where part of the output of an amplifier stage is applied to the
input, so as to alter the input impedance of the amplifier. When applied deliberately, the
intention is usually to increase rather than decrease the impedance. Generally, any technique
where part of the output of a system is used at startup is described as bootstrapping.
In the domain of MOSFET circuits, "bootstrapping" is commonly used to mean pulling up
the operating point of a transistor above the power supply rail. The same term has been used
somewhat more generally for dynamically altering the operating point of an operational amplifier
(by shifting both its positive and negative supply rail) in order to increase its output voltage swing
(relative to the ground). [4]In the sense used in this paragraph, bootstrapping anoperational
amplifier means "using a signal to drive the reference point of the op-amp's power supplies". A
more sophisticated use of this rail bootstrapping technique is to alter the non-linear C/V
characteristic of the inputs of a JFET op-amp in order to decrease its distortion
CIRCUIT DIAGRAM:

BOOTSTRAPSWEEPGENERATOR

MODEL WAVEFORM:
OBSERVATIONS:

Ts=2.2v

Tr=1.5v

Output Ramp Voltage=3.3v

Ve(sat) – Vb(sat) = 0.98v

PROCEDURE:

1. Connect the components as per circuit diagram.

2. Apply supply voltage from the DC regulated power supply.
3. Square wave generates from the function generator to the circuit and
channel to show the output in CRO.
4. Compare the practical values and with theoretical values.
5. Draw the input and output wave forms on the graph.

RESULT:
Hence the values and drawn the input and output waveforms areo bserved
 EXPERIMENTNO:9

CLASS A SERIES-FED POWER AMPLIFIER

AIM:

To obtain the frequency response of class A series fed power Amplifier.

APPARATUS REQUIRED:
a. Transistor (NPN,Si) (BC107) :1nos.
b. Electrolytic Capacitor (100nf) :2nos.
c. Carbon film Resistors 1kΩ, 33Ω and 20kΩ :[Link]
d. 20MHz Dual trace CRO :1no.
e. Multi meter :2no.
f. Connectting Wires :1lot

THEORY:

The circuit is called “series fed” because the load R L is connected in series with transistor
output. It is also called as direct coupled amplifier. I CQ=Zero signal collector current
VCEQ=Zero signal collector to emitter voltage power amplifiers are mainly used to deliver
more power to the load. To deliver more power it requires large input signals, so generally
power amplifiers are proceeded by a series of voltage amplifiers. In class-A power
amplifiers, Q- point is located in the middle of DC-load line .So output current flows from
complete cycle of input signal. Under zero signal condition, maximum power dissipation
occurs across the transistor. As the input signal amplitude increases power dissipation
reduces. The maximum theoretical efficiency is 25%.
CIRCUIDIAGRAM:

TABULAR FORM:

Vin=100mV

[Link]. Frequency VOUT(volt) A=Vout/VIN Gain=20logVout/VIN(db)

1. 20Hz 0.5 10 20
2. 50Hz 1.3 26 28.3
3. 100Hz 2.3 46 33.25
4. 200Hz 3.8 76 37.61
5. 500Hz 5 100 40
6. 1KHz 5.2 104 40.34
7. 2KHz 5.2 104 40.34
8. 5KHz 5.2 104 40.34
9. 10KHz 5.2 104 40.34
10. 20KHz 5.2 104 40.34
11. 50KHz 4.7 94 39.46
14. 100KHz 3.5 70 36.90
15. 200KHz 2 40 32.04
16. 500KHz 0.8 16 24.08
17. 1MHz 0.4 8 18.06
MODELGRAPH:

PROCEDURE:

1. Connect the circuit diagram and supply the required DC supply.

2. Apply the Ac signal at the input and keep the frequency at 1kHz and connect the power
output meter at the output. Change the load resistance in steps for each value of impedance
and note down the output power.
3. Plot the graph between o/p power and load impedance. From this graph find the impedance
for which the o/p power is maximum. This is the value of optimum load.
4. Select load impedance which is equal to 0V or near about the optimum load. See the
waveform of the o/p of the CRO.
5. Calculate the power sensitivity at a maximum power o/p using the relation.

RESULT:

Hence the frequency response of class A series fed power amplifier is obtained.
 EXPERIMENTNO:10

CLASS A POWER AMPLIFIER (TRANSFORMER COUPLED)

AIM:

1. To study and plot the frequency response of a Class A Power

2. To calculate efficiency of Class A Power Amplifier.

APPARATUS REQUIRED:

1. NPN Transistor (BC107) :1No.

2. Resistors (560Ω,100kΩ,470Ω) :1No.
3. Capacitor : 22µF
4. Inductor : 50mH
5. Ammeter (0to100mA) : 1No.
6. CRO
7. Function generator
8. Connecting Wires

THEORY:

Power amplifiers are mainly used to deliver more power to the load. To deliver more
power it requires large input signals, so generally power amplifiers are preceded by a series of
voltage amplifiers. In class-A power amplifiers, Q-point is located in the middle of DC-load
line. So output current flows for complete cycle of input signal. Under zero signal condition,
maximum power dissipation occurs across the transistor. As the input signal amplitude
increases power dissipation reduces. The maximum theoretical efficiency is 50%.
 CIRCUITDIAGRAM:

EXPECTEDGRAPH:
TABULARFORM:

Vin=150Mv

[Link]. Frequency VOUT(volt) A=Vout/VIN Gain= 20 log

Vout/VIN(db)
1. 50Hz 3.0 3.0 25.67
2. 100Hz 3.6 3.6 28.70
3. 200Hz 3.8 3.8 27.70
4. 500Hz 4.0 4.0 27.73
5. 1KHz 4.0 4.0 27.73
6. 2KHz 4.0 4.0 27.73
7. 5KHz 4.0 4.0 27.73
8. 10KHz 4.0 4.0 27.73
9. 20KHz 4.0 4.0 27.73
10. 50KHz 4.0 4.0 27.73
11. 100KHz 4.0 4.0 27.73
14. 200KHz 3.6 3.6 25.67
15. 500KHz 3.5 3.5 25.70
16. 1MHz 2.8 2.8 20.59

PROCEDURE:

1. Connect the circuit as shown in figure.

2. Adjust input signal amplitude in the function generator and observe an amplified voltage at
the output without distortion.
3. By keeping input signal voltage, say at150 mV, vary the input signal frequency from 0-
1MHz as shown in tabular column and note the corresponding output voltage.
4. Measure and note down the zero signal dc current by disconnecting the function generator
from the circuit.
5. Calculate the efficiency according to the expressions given.
6. Plot the graph between the o/p gain and frequency and calculate the bandwidth
PRECAUTIONS:

1. No loose contacts at the junctions.

2. Check the connections before giving the power supply
3. Observations should be taken carefully.

RESULT:

Hence the frequency Response of CLASS-A Power amplifier is plotted.

 EXPERIMENTNO:11

CLASS B PUSH-PULL POWER AMPLIFIER

AIM:

To Plot the Graph between Load and Power of a Class B Push pull Power
Amplifier.
APPARATUS REQUIRED:

1. [Link] :1 No
2. Function Generator : 1No
3. Push-Pull Power amplifier Module
4. ConnectingWires:1lot
5. CRO Probes

THEORY:

The Class B push pull amplifier is almost similar to the Class A push pull amplifier and
the only difference is that there is no biasing resistors for a Class B push pull amplifier. This
means that the two transistors are biased at the cut off point. The Class B configuration can
provide better power output and has higher efficiency (upto78.5%). Since the transistor are
biased at the cutoff point, they consumes no power during idle condition and this adds to the
efficiency.

CIRCUIT DIAGRAM:
TABULAR FORM:

Out put Power Power in db

[Link] RL( KΩ)
P o (mW) (10logP0)
1 2 1.5 1.76
2 4 2.4 3.80

3 6 2.56 4.08

4 8 2.89 4.60

5 10 3.05 4.84

6 12 3.66 5.63

7 14 3.98 5.99

8 16 4.90 6.90

9 18 5.0 6.98

10 20 5.5 7.40

PROCEDURE:

1. Connect the circuit diagram as shown in the figure.

2. Determine the maximum signal handling capacity of the push pull amplifier.
3. Apply sinusoidal signal of 4mv peak to peak voltage at a frequency of 1kHz.
4. Connect Power meter at the O/P terminals.
5. By changing the load at the O/P terminals measure the power in the Power
meter.
6. Tabulate the readings.
7. Plot the graph between Power vs load
MODELGRAPH:

RESULT:

Hence plot is drawn between Load and Power of Amplifier.

 EXPERIMENTNO:12

COMPLEMENTARY SYMMETRY CLASS B PUSH-PULL POWER

AMPLIFIER

AIM:

To design a complementary-symmetry class-B push-pull power amplifier in

order to achieve maximum output AC power and efficiency.
APPARATUS REQUIRED:

1. CRO(Dual channel) DC–20MHz

2. Function generator :1 no.
3. Connecting wires :1lot.

THEORY:

Power amplifiers are designed using different circuit configuration with the sole
purpose of delivering maximum distorted output power to load. Push-pull amplifiers
operating either in class-B are class-AB are used in high popup audio system with
high efficiency.

In complementary–symmetry class-B power amplifier two types of transistors,

NPN and PNP are used. These transistors acts as emitter follower with both emitters

connected together saturation region. So, that only 180 0of the input signal is flowing
in the output.
In complementary-symmetry power amplifier, during the positive half cycle of

Input signal NPN transistor conducts and during the negative half cycle PNP
transistor conducts. Since, the two transistors are complement of each other and they
are connected symmetrically so, the name complementary symmetry has come.

Theoretically efficiency of complementary symmetry power amplifier is 78.5%.

CIRCUIT DIAGRAM:

OUTPUTWAVEFORM
PROCEDURE:

1. Connect the circuit as shown in the circuit diagram.

2. Measure base, emitter and collector D.C voltages of both transistor
sand compare against estimated values.
3. Apply the input at input terminals of the circuit from the function
generator.
4. Keep the input signal at constant frequency under mid frequency
region and adjust the amplitude such that output voltage
undistorted.
5. Calculate the power efficiency and compare it with theoretical
efficiency.

OBSERVATIONS:

Efficiency is defined as the ratio of A.C output power to D.C input

power

DC input power=VCC×ICQ;

AC output power=VP-P2/8RL

CALCULATIONS:

Input DC power=VCC×ICQ;

Output AC power=VrmsxIrms=VPP2/8RL,

RESULT:
1. The maximum input signal amplitude which produces undistorted
output signal

2. The practical efficiency of the circuit is78%

 EXPERIMENT NO.13

SINGLE TUNED VOLTAGE AMPLIFIER

AIM:
To observe and analyze the output wave of tuned Class C Tuned Voltage Amplifier.

APPARATUS REQUIRED:
1. Transistor-(BC107)-1no
2. Signal source.
3. Resistors-1kΩ (2), 10kΩ(1),220Ω(1),47kΩ(1).
4. Capacitors-10µf(3).
5. C.R.O.
6. Digital Multi meter.
7. Bread Board.
8. Connecting Wires.

THEORY:

The power amplifier is said to be class C amplifier if the Q point and the input signal are
selected such the output signal is obtained for less than a half cycle, for a full input cycle. Due
to such a selection of the Q point, transistor remains active, for less than a half cycle. Hence
only that much part is reproduced at the output. For remaining cycle of the input cycle the
transistor remains cut-off and no signal is produced at the output. The angle of the collector
current flow is less than 180 degrees. The current and voltage wave forms of a class C
amplifier operation are observed. But the efficiency of this class of operation is much higher
and can reach very close to 10%.
CIRCUITDIAGRAM:

MODELGRAPH:

Gain

in dB

fr f
OBSERVATION:

VIN=50mVat1KHz

[Link]. Frequency VOUT(volt) Gain=20logVout/VIN(db)

(KHz)
1. 12.7 0.8 24.08
2. 13.8 1.2 27.60
3. 14.2 2.4 33.62
4. 14.0 2.8 34.96
5. 14.3 3.2 36.12
6. 14.69 12 47.60
7. 14.7 10 46.02
8. 14.9 8 44.08
9. 15.1 6 41.58
10. 16.2 5.2 40.34
11. 15.3 2 26.02
12. 15.4 1.2 27.60
13. 15.5 1.1 24.08
14. 18 0.7 22.92
15. 20 0.4 18.06
16 50 0.1 6.02

PROCEDURE:

 Take the components from the components tool bar and Connections are made as
per the circuit diagram.

 Simulate the circuit and observe and draw the output wave form.

 Then perform A.C analysis for the above circuit in the frequency.

 In the output variable tab select the output node.

 Now run the simulation and take phase, magnitude analysis graph.

CALCULATIONS:

Theoretical Calculation:

fr= 1
1 = 15.9KHz.
2LC 2101030.01106

2fL/r =9.99852; Take R =100ohm.

Q
Bandwidth= fr
=1.59KHz.
Q

Practically:

fr=14.69KHz

Bandwidth=1.7KHz.

PRECAUTION:

 Loose and wrong connections are avoided.

 Power supply should be kept in minimum position initially.

 Reading should be taken with parallel axes error.

RESULT:
Hence the response curve for Class C voltage amplifier is thus observed.
 EXPERIEMENTNO:14

DOUBLE TUNED VOLTAGE AMPLIFIER

AIM:

To study the characteristics of DOUBLE TUNED amplifiers.

APPARATUS REQUIRED:

1. Signal generator
2. Oscilloscope
3. Tuned amplifier
4. Power supply

THEORY:
Tuned amplifier provide high constant gain over a specified bandwidth centered at a
specified frequency f and 8S much rejection as possible outside this band practical gain and
phase characteristics A single stage tuned amplifier is seldom used in practice. Generally,
double- tuned type as shown in Fig.(2) are preferred, due to using it in cascaded amplification.
However, alignment problem is more difficult in double tuned amplifiers, further the band
width in multistage tuned amplifiers are less. This shrinking of bandwidth can be avoided by
the use of stagger tuning in which the input and the output circuits of each stage is tuned to a
slightly different frequencies.
CIRCUIRDIAGRAM:
TABULAR FORM:

S Frequency VOUT(volt) Gain=20logVout/VIN(db)

. (KHz)
N
O
.
1 12.7 0.8 24.08
.
2 13.8 1.2 27.60
.
3 14.2 2.4 33.62
.
4 14.0 2.8 34.96
.
5 14.3 3.2 36.12
.
6 14.69 12 47.60
.
7 14.7 10 46.02
.
8 14.9 8 44.08
.
9 15.1 6 41.58
.
1 16.2 5.2 40.34
0
.
1 15.3 2 26.02
1
.
1 15.4 1.2 27.60
2
 .
1 15.5 1.1 24.08
3
.
1 18 0.7 22.92
4
.
1 20 0.4 18.06
5
.
1 50 0.1 6.02
6

CALCULATIONS:
Fr= 1 1
2LC 2101030.01106 = 15.9KHz.

2frL
Q =9.99852; Take R =100ohm.
R

Bandwidth= fr
=1.59KHz.
Q

Practically:

fr=14.69KHz

Bandwidth=1.7KHz.

EXPECTEDGRAPH:

PROCEDURE:

1. Connect the components as per circuit diagram.

2. Give the supply form DC generator and give the input signal from function generator.
3. Take the readings at different frequencies.
4. Observe the input and output waveforms and plot the graph.

RESULT:

Hence observed the input and output wave forms and drawn the graph.
SOFTWARE (Using Simulation)
 EXPERIMENT NO .1

DETERMINATION OF Ft OF GIVEN TRANSISTOR

AIM:
To determine the fT of a given transistor using simulation.

APPARATUS REQUIRED:

1. TransistorBC107: 1 No
2. Capacitors10µf/25V: 3No‟s
3. Resistors1kΩ,2.2kΩ,4.7kΩ,8.2kΩ,33kΩ:1Noeach
4. Function generator: 1 No
5. 20MHzDualtraceoscilloscope: 1No
6. Bread board : 1No
7. 0-30VDCpowersupply: 1No
8. Connecting wires: 1 set

SOFTWAR TOOL:

 MULTISIM

THEORY:
Common Emitter amplifier has the emitter terminal as the common terminal
Between input and output. The emitter base junction is forward biased and collector base junction is reverse
biased, so that transistor remains in active region throughout the operation. When a sinusoidal AC signal is
applied at input terminals of circuit during positive half cycle the forward bias of base emitter junction VBE is
increased resulting in an increase in IB, The collector current IC is increased by β times the increase in IB, VCE
is correspondingly decreased. i.e., output voltage gets decreased. Thus in a CE amplifier a positive going signal
is converted into a negative going output signal i.e., 180 0 phase shift is introduced between output and input
signal and it is an amplified version of input signal.

Characteristics of CE amplifier:

1. Large current gain (AI)

2. Large voltage gain (AV)

3. Large power gain (AP=[Link])

4. Phase shift of 1800

5. Moderate input & output impedances.

 CIRCUITDIAGRAM:

MODEL GRAPH:

TABULAR FORM:

Input Voltage Vin=10mv

[Link]. Frequency VOUT(volt) A=Vout/VIN Gain=20logVout/VIN(db)
 1. 20Hz 0.5 10 20
2. 50Hz 1.3 26 28.3
3. 100Hz 2.3 46 33.25
4. 200Hz 3.8 76 37.61
5. 500Hz 5 100 40
6. 1KHz 5.2 104 40.34
7. 2KHz 5.2 104 40.34
8. 5KHz 5.2 104 40.34
9. 10KHz 5.2 104 40.34
10. 20KHz 5.2 104 40.34
11. 50KHz 4.7 94 39.46
14. 100KHz 3.5 70 36.90
15. 200KHz 2 40 32.04
16. 500KHz 0.8 16 24.08
17. 1MHz 0.4 8 18.06

OBSERVATIONS:

1. Maximum gain (Av) = 40.34 db

2. Lower cut-off frequency (FL) = 20HZ
3. Upper cut-off frequency (FH)= 500kHZ
4. Band width (B.W) = (FH– FL) = 480KHZ
5. Gain band width product fT=Av(B.W)=19.26kHZ
6. The voltage gain of the amplifier is given calculate the gain in by Gain=20 log Av Where, V o
is the output voltage. VS is input voltage of applied AC signal.

PROCEDURE:

1. Open multi-sim software to design determine the fT of a given transistor circuit.

2. Select the new editor window and place the required components
3. Make the connections using wire and check the connections and oscillator
4. Go for simulation using Run key Observe the output wave form on CRO.
5. Indicate the node names and go for AC analysis with the output mode.
6. Observe the waveforms on the Screen.
7. Calculate the Bandwidth of the amplifier.
RESULT:
Hence observe the calculations of frequency and gain product.

EXPERIMENT NO.2

VOLTAGE-SERIESF EEDBACK AMPLIFIER

 AIM:
To Study the voltage gain, frequency response, and Bandwidth of a Voltage series feed- back
amplifier with and without feedback.
APPAERTS REQUIRED:-

1. Transistor (BC-107)-1no
2. Breadboard
3. Resistors–2.2KΩ,1KΩ -2,5.6KΩ,1.5KΩ
4. Capacitors -10µf–2no
5. C.R.O. with probes
6. Function Generators
7. Regulated Power Supply
8. Connecting wires

THEORY:

In voltage- series feedback amplifier the voltage developed in the output is in series with the input
voltage as far as the base –emitter junction is concerned. This is a single stage RC coupled amplifier without
emitter by pass capacitor across RE. R1and R2 provides the base bias. The emitter follower inherently exhibits
100 percent negative feedback since the voltage at the emitter follows the input voltage.
As the output voltage is taken across RE=RL, the feedback ratio, β=RE/RL=1.

The emitter follower simultaneously increases input resistance and decreases output resistance.
Therefore, the overall voltage gain, Af=A/1+A.

CIRCUIT DIAGRAM:
PROCEDURE:-

1. Connect the circuit diagram as shown in figure. Adjust input signal amplitude
50mV, 1KHz in the function generator and observe an amplified voltage at the output
without distortion.
2. By keeping input signal voltage, constant 50mV, vary the input signal frequency
from 1to1MHz in steps as shown in tabular column and note the corresponding
output voltages. By keeping feed- back terminals open and calculate the Bandwidth from
the graph.
3. Connect the Feedback short A and B terminal and now vary the input signal
frequency from 1 to 1MHz in steps as shown in tabular column and note the
corresponding output voltage.
4. Calculate the Bandwidth with feed-back from the plot of graph.

EXPECTED GRAPH:
PRECAUTIONS:

1. Avoid loose connections and give proper input Voltage

RESULT:

Hence the voltage gain, frequency response, and Bandwidth of voltage series feed-back
amplifier with and without feedback are observed.
 EXPERIMENTNO:3

CURRENT-SHUNTFEEDBACKAMPLIFIER
AIM:

1. To study the current shunt feedback amplifier

2. To measure the voltage gain of the amplifier at1KHz.
To obtain the frequency response characteristic and the bandwidth of the amplifier using
Simulation

APPARATUS:

1. Transistor(BC107)-1no

2. Bread board

3. Resistors–22KΩ,1KΩ-2,3.3KΩ,5.6KΩ

4. Capacitors -10µf–2no

5. C.R.O. with probes

6. Function Generators

7. Regulated Power Supply

8. Connecting wire

THEORY:

In current series feedback, a voltage is developed which is proportional to the output

current. This is called current feedback even though it is a voltage that subtracts from the input
voltage. Because of the series connection at the input and output, the input and output resistance
gets increased. This type of amplifier is called trans-conductance amplifier. In this circuit to
place a resistor Re between emitter lead of a common emitter amplifier and ground. When Re is
properly bypassed with a large capacitor (Ce), the output voltage is Voand the voltage gain with-
out feedback is A. Resistor (Re)provides d.c. bias stabilization, but no a.c. feedback. When the
Ceis removed, an a.c. voltage will be developed across Re due to the emitter current flowing
through Re and this current is approximately equals to the output collector current. This voltage
drop across Rewill serve too decrease the voltage between base and emitter, so that the output
voltage will decrease to Vo, The gain of the amplifier with negative feedback is now Af.
CIRCUITDIAGRAM:

CURRENT SHUNT FEEDBACK AMPLIFIER

VCC 10 0 DC 15V
* Input voltage is 20mv peak for frequency
response. VIN 1 0 AC 20MV SIN(0 10MV 1KHZ)
 * A dummy voltage source of 0v to measure the input
current. VX 1 12 DC 0V
RS122150
C12310UF
R1103200K
R23050K
* Transistors Q1 and Q2 have model name
QM Q1 4 3 5 QM
Q2 7 6 8 QM
* Model statement for NPN transistors whose name is QM
.MODEL QM NPN (IS=3.29E-14BF=175BR=1 RC=1RE=0 TF=0.2NS TR=5NS
+ CJE=29.4PFVJE=0.8CJC=19.5PFVJC=0.8CCS=1PFVA=100) RC1 10 4
12K
RE503.6K

CE15015UF
C24610UF
R3106120K
R46030K
RC2 1076.8K
RE2803.6K

CF81110UF
RF11325K
C37910UF
RL9010K
* AC analysis from10Hz to 10MHz with a decade increment and
* 10 points per decade

.ACDEC1010HZ10MEGHZ
* Plot the results of the ac analysis for the magnitude and phase angle of output voltage at
node 9
.PLOTACVM(9) VP(9)
* Transient analysis for 03ms with 50us increment
.TRAN50US 3MS
.PROBE ;Graphical waveform analyzer

.END ;End of the circuit file

OUTPUT:

PROCEDURE:

1. Open multisim software to design determine the fT of a given transistor circuit.

2. Select the new editor window and place the required components
 3. Make the connections using wire and check the connections and oscillator
4. Go for simulation using Run key Observe the output waveform on CRO.
5. Indicate the node names and go for AC analysis with the output mode.
6. Observe the transient response and AC response for current shunt feedback amplifier
draw the magnitude response curve.
7. Calculate the Band width of the amplifier.

RESULT:
Hence the phase plot and magnitude plot of current shunt feedback amplifier are observed.
 EXPERIMENTNO:4(a)

RCPHASESHIFTOSCILLATOR

OBJECTIVE:
[Link] simulate RC phase shift oscillator in Multisim and study the transient response.
[Link] determine the phase shift of RC network in the circuit.

SOFTWARETOOL:
 Multisim
APPARATUS:
[Link] power supply - 1No.
[Link] generator - 1No.
[Link] - 1No.
[Link] (BC107or 2N2222) - 2No.
[Link](47 KΩ,2.2KΩ,1k) - [Link]
[Link] (10 KΩ) - 3Nos.
[Link] (10 µF, 100 µF) - [Link]
(1nf,or 10nf) - 3 No.
PROCEDURE:

1. Open Multisim Software to design RC Phase shift oscillator

2. Select on New editor window and place the required component on the circuit window.
3. Make the connections using wire and check the connections and oscillator.
4. Go for simulation and using Run Key observe the output waveforms on CRO
5. Observe the Transient Response and Calculate the Frequency of the oscillator

OBSERVATIONS/GRAPHS:

TRANSIENT RESPONSE:

TABULAR COLUMN:
[Link] C R Theoretical Practical Vo(p-p)
(F) (Ω) Frequency Frequency (Volts)
(KHz) (KHz)
1 0.01uf 1.5k 2.319 2.1 5

RESULT:-
Hence the theoretical and practical frequency of oscillations and waveforms are observed.
 EXPERIMENTNO:4(b)

WIEN BRIDGE OSCILLATOR

AIM:

To study and calculate frequency of oscillations of Wein Bridge Oscillator and compare it with
theoretical value.

APPARATUS:

1. Transistor–(BC 107)-2no
2. Resistors–1K,5K,10K,100K,
3. Capacitors –0.01uf,100nF(3),10nf
4. RPS
5. CRO
6. Breadboard
7. Connecting wires and probes

SOFTWARE TOOL:
Multisim

CIRCUIT DIAGRAM
 PROCEDURE:-

1. Open Multisim Software to design Colpitts oscillator circuit

2. Select on New editor window and place the required component on the circuit window.
3. Make the connections using wire and check the connections and oscillator.
4. Go for simulation and using Run Key observe the output waveforms on CRO
5. Calculate the frequency theoretically and practically.

OBSERVATIONS/GRAPHS:

TABULAR COLUMN:

[Link] C (F) R Theoretical Practical Vo(p-p)

(Ω) Frequency Frequency (Volts)
(KHz) (KHz)
1 100pF 400 7.95 7.1 5

RESULT:-
Hence the waveform and frequency of oscillations are obtained.
 EXPERIMENTNO:5(a)

HARTLEY OSCILLATOR

AIM:
To design Hartley oscillator using Multisim software and calculate the frequency

APPARATUS:
1. Transistor–(BC107)-1no
2. Resistors–1K,5K,10K,100K,
3. Capacitors– 100nF(3),10nf
4. Inductor-10mHor 1mH.
5. RPS
6. CRO
7. Breadboard
8. Connecting wires and probes

SOFTWARE TOOL:
Multisim
PROCEDURE:

1. Open Multisim Software to design Hartley oscillator circuit

2. Select on New editor window and place the required component on the circuit window.
3. Make the connections using wire and check the connections and oscillator.
4. Go for simulation and using Run Key observe the output waveforms on CRO
5. Calculate the frequency theoretically and practically

OBSERVATIONS/GRAPHS:

TABULATION:

[Link] L1and Theoretical Practical Vo(peak

L2(mH) C(F) frequency frequency to peak)
(KHz) (KHz)
1 0.6 0.1U 14.5 12.5 5

RESULT:

Hence the frequency of oscillations of Hartley oscillator are obtained

 EXPERIMENT NO.5(b)

COLPITT’S OSCILLATOR

AIM:

To design Colpitt’s oscillator using Multisim software and calculate the frequency

APPARATUS REQUIRED

1. Transistor–(BC 107)-1no
2. Resistors–1KΩ,5KΩ,10KΩ,100KΩ,
3. Capacitors– 100nF-3,10nf
4. RPS
5. CRO
6. Breadboard
7. Connecting wires and probes

SOFTWARE TOOL:
Multisim
PROCEDURE:-
1. Open Multisim Software to design Colpitt’s oscillator circuit
2. Select on New editor window and place the required component on the circuit window.
3. Make the connections using wire and check the connections and oscillator.
4. Go for simulation and using Run Key observe the output waveforms on CRO
5. Calculate the frequency theoretically and practically.

OBSERVATIONS/GRAPHS:

TABULAR COLUMN:

[Link] L(H) C1(F) C2 (F) Theoretical Practical Vo(V)

Frequency Frequency Peakto
(KHz) (KHz) peak
1 100uH .1u 0.1p 71.7 69.3 3

RESULT:

Hence the frequency of oscillations of colpitt’s oscillator is obtained.

 EXPERIMENT NO.6

TWO STAGE RC COUPLED AMPLIFIER

AIM:

[Link] simulate the Two Stage RC Coupled Amplifier in Multisim and study
the transient and frequency response.
2. To determine the phase relationship between the input and output
voltages by performing the transient analysis.
3. To determine the maximum gain, 3dBgain, lower and upper cut-
off frequencies and bandwidth of Two Stage RC Coupled Amplifier
by performing the AC analysis.
4. To determine the effect of cascading on gain and bandwidth.

SOFTWARE TOOL:
Multisim

APPARATUS REQUIRED:

1. Regulated power supply-1 no.

2. Function generator-1no.
3. CRO-1No.
4. Transistor (BC107or2N2222)-2no.
5. Resistors (5KΩ,47KΩ,2KΩ,,1KΩ)-2No. each
6. Resistor (10KΩ)-4Nos.
7. Capacitors(10µF,1µF)-2,3 [Link]
8. BreadBoard-1No.
9. Connecting wires

THEORY:
An amplifier is the basic building block of most electronic systems. Just as one brick does not
make a house, a single-stage amplifier is not sufficient to build a practical electronic system. The gain of
the single stage is not sufficient for practical applications. The voltage level of a signal can be raised to the
desired level if we use more than one stage. When a number of amplifier stages are used in succession
(one after the other) it is called a multi stage amplifier or a cascade amplifier. Much higher gains can be
obtained from the multi-stage amplifiers.

Figure shows how to couple two stages of amplifiers using RC coupling scheme. This is the most
widely used method. In this scheme, the signal developed across the collector resistor RC (R2) of the first
stage is coupled to the base of the second stage through the capacitor CC . (C2) The coupling capacitor
blocks the dc voltage of the first stage from reaching the base of the second stage.
 CIRCUITDIAGRAM:

PROCEDURE:

1. Open Multisim Software to design Two stage RC coupled amplifier circuit

2. Selection New editor window and place the required component CS amplifier on the
circuit window.
3. Make the connections using wire and check the connections and oscillator.
4. Go for simulation and using Run Key observe the output waveforms on CRO
5. Indicate the node names and go for AC Analysis with the output node
6. Observe the Transient response and Ac Analysis for the first stage and second stage
separately and draw the magnitude response curve
7. Calculate the bandwidth of the amplifier.
OBSERVATIONS/GRAPHS:

TRANSIENT RESPONSE:
FREQUENCYRESPONSE:

RESULT :
Hence the phase plot, magnitude and frequency response of two stage RC coupled
amplifier are observed.
 EXPERIMENT NO .7

DARLINGTON PAIR AMPLIFIER

AIM:

1. To simulate the Darlington Pair amplifier in Multisim and study the transient and
frequency response.
2. Obtain the frequency response characteristics of Darlington pair amplifier by
hardware implementation.
3. To determine the maximum gain, 3dBgain, lower and upper cutoff frequencies
and bandwidth of Darlington pair Amplifier by performing the AC analysis.

SOFTWARE TOOL:

 Multisim

APPARATUS REQUIRED:
1. Regulated power supply - 1No.
2. Function generator - 1No.
3. CRO - 1No.
4. Transistor (BC107, BC372,or 2N3904) - 3No.
5. Resistors(1KΩ,82KΩ,22KΩ,2.2KΩ,22KΩ,390Ω) - [Link]
6. Capacitors(10µF) - 2No.
7. Bread Board - 1No.
8. Connecting wires

THEORY:

Darlington transistor (often called a Darlington pair) is a compound structure consisting

of two bipolar transistors (either integrated or separated devices) connected in such a way that
the current amplified by the first transistor is amplified further by these can done. This
configuration gives a much higher common/emitter current gain than each transistor taken
separately and, in the case of integrated devices, can take less space than two individual
transistors because they can use a shared collector. Integrated Darlington pairs come packaged
singly in transistor-like packages or as an array of devices (usually eight) in an integrated
circuit.
 The Darlington configuration was invented by Bell Laboratories engineer Sidney
Darlington in1953. He patented the idea of having two or three transistors on a single chip
sharing a collector.

CIRCUIT DIAGRAM:

PROCEDURE:

1. Open Multisim Software to design the Darlington pair amplifier circuit

2. Selection New editor window and place the required component on the circuit window.

3. Make the connections using wire and check the connections and oscillator.

4. Go for simulation and using Run Key observe the output waveforms on CRO
5. Indicate the node names and go for AC Analysis with the output node

6. Observe the Ac Analysis and draw the amplitude response curve

7. Calculate the bandwidth of the amplifier

OUTPUT:

FREQUENCY RESPONSE CURVE:

RESULT:

Hence we observe the phase plot, magnitude and frequency response of Darlington
pair amplifier.
 EXPERIMENT NO .8

BOOTSTRAPPED EMITTER FOLLOWER

AIM:

To design Bootstrapped Emitter follower using Multisim software and calculate the frequency

APPARATUS REQUIRED:
1. Transistors (Si) : 2No.
2. Diode (IN4007) : 1No.

3. Ceramic Disc Capacitor100µF,10nF : [Link]

4. Electrolytic Capacitor 47µF : [Link]
5. 20MHz Cathode Ray Oscilloscope : 1No.

6. 1MHz Signal generator : 1No.

7. Regulated DC power supply (0-30V) : 1No.
8. Bread board Trainer Module : 1No.
9. Connecting wires : 1lot
SOFTWARE TOOL:

 MULTISIM

THEORY:

Bootstrap circuit is one where part of the output of an amplifier stage is applied to the
input, so as to alter the input impedance of the amplifier. When applied deliberately, the
intention is usually to increase rather than decrease the impedance. Generally, any technique
where part of the output of a system is used at startup is described as bootstrapping.

In the domain of MOSFET circuits, "bootstrapping" is commonly used to mean pulling

up the operating point of a transistor above the power supply rail. The same term has been
used somewhat more generally for dynamically altering the operating point of an operational
amplifier (by shifting both its positive and negative supply rail) in order to increase its output
voltage swing (relative to the ground).[4] In the sense used in this paragraph, bootstrapping an
Operational amplifier means "using a signal to drive the reference point of the op-amp's power
supplies". A more sophisticated use of this rail bootstrapping technique is to alter the non-linear
C/V characteristic of the inputs of a JFET op-amp in order to decrease its distortion

CIRCUITDIAGRAM:

PROCEDURE:
1. Open Multisim Software to design the Darlington pair amplifier circuit

2. Select on New editor window and place the required component on the circuit window.

3. Make the connections using wire and check the connections and oscillator.

4. Go for simulation and using Run Key observe the output waveforms on CRO

5. Indicate the node names and go for AC Analysis with the output node

6. Observe the Ac Analysis and draw the amplitude response curve

7. Calculate the bandwidth of the amplifier

 OUTPUT:

RESULT:

Hence the output waveform of Bootstrapped emitter follower are observed.

 EXPERIMENTNO.9

CLASS A SERIES-FED POWER AMPLIFIER

AIM:
To design a series fed class-A power amplifier in order to achieve max output ac power
and efficiency using Simulation.

APPARATUS REQUIRED:
a. Transistor (NPN, Si) (BC107) :1nos.
b. Electrolytic Capacitor (100nf) :2nos.
c. Carbon film Resistors 1kΩ,33Ωand20kΩ:[Link]
d. 20MHz Dual trace CRO :1no.
e. Multi meter :2 no.
f. Connecting Wires :1lot

THEORY:

The circuit is called “series fed” because the load R L is connected in series with
transistor output. It is also called as direct coupled amplifier. I CQ=Zero signal collector
current VCEQ=Zero signal collector to emitter voltage power amplifiers are mainly used to
deliver more power to the load. To deliver more power it requires large input signals, so
generally power amplifiers are proceeded by a series of voltage amplifiers. In class-A
power amplifiers, Q- point is located in the middle of DC-load line .So output current flows
from complete cycle of input signal. Under zero signal condition, maximum power
dissipation occurs across the transistor. As the input signal amplitude increases power
dissipation reduces. The maximum theoretical efficiency is 25%.
CIRCUIT DIAGRAM:

PROCEDURE:

1. Open Multisim Software to design the Darlington pair amplifier circuit

2. Select on New editor window and place the required component on the circuit window.
3. Make the connections using wire and check the connections and oscillator.

4. Go for simulation and using Run Key observe the output waveforms on CRO

5. Indicate the node names and go for AC Analysis with the output node

6. Observe the Ac analysis and draw the amplitude response curve

7. Calculatethebandwidthoftheamplifier
OUTPUT:

RESULT:

HencetheinputandoutputwaveformsofSeriesfedclass-Apower amplifierare observed.

 EXPERIMENT NO.10

TRANSFORMER-COUPLED CLASS A POWER AMPLIFIER

AIM:
To study and plot the frequency response of a Class A Power amplifier using simulation.
APPARATUS:

1. NPN Transistor (BC107) :1No.

2. Resistors (560Ω,100kΩ,470Ω) :1No.
3. Capacitor : 22 µF
4. Inductor : 50mH
5. Ammeter (0to100mA) : 1No.
6. CRO
7. Function generator
8. Connecting Wires

SOFTWARE TOOL:

 MULTISIM

THEORY:

Power amplifiers are mainly used to deliver more power to the load. To deliver
more power it requires large input signals, so generally power amplifiers are preceded
by a series of voltage amplifiers. In class-A power amplifiers, Q-point is located in the
middle of DC-load line. So output current flows for complete cycle of input signal.
Under zero signal condition, maximum power dissipation occurs across the transistor.
As the input signal amplitude increases power dissipation reduces. The maximum
theoretical efficiency is 50%.
CIRCUITDIAGRAM:

PROCEDURE:
1. Open Multisim Software to design the Darlington pair amplifier circuit

2. Select on New editor window and place the required component on the circuit window.
3. Make the connections using wire and check the connections and oscillator.

4. Go for simulation and using Run Key observe the output waveforms on CRO

5. Indicate the node names and go for AC Analysis with the output node

6. Observe the Ac Analysis and draw the amplitude response curve

7. Calculate the bandwidth of the amplifier

 OUTPUT:

RESULT:

Hence the input and output waveforms of Series fed class-A power amplifier are observed.
 EXPERIMENT NO.11

CLASS B PUSH-PULL POWER AMPLIFIER

AIM:

To Plot the Graph between Load and Power of a Class-B Push pull Power
Amplifier using simulation.
APPARATUS:

1. [Link] :1 No
2. Function Generator : 1No
3. Push-Pull Power amplifier Module
4. ConnectingWires:1lot
5. CRO Probes

SOFTWARETOOL:

 MULTISIM

THEORY:

The Class B push-pull amplifier is almost similar to the Class A push pull amplifier and
the only difference is that there is no biasing resistors for a Class B push pull amplifier. This
means that the two transistors are biased at the cut-off point. The Class B configuration can
provide better power output and has higher efficiency (upto78.5%). Since the transistor are
biased at the cutoff point, they consumes no power during idle condition and this adds to the
efficiency.
CIRCUIT DIAGRAM:

PROCEDURE:

1. Open Multisim Software to design the amplifier circuit

2. Selection New editor window and place the required component on the circuit window.

3. Make the connections using wire and check the connections and oscillator.

4. Go for simulation and using Run Key observe the output waveforms on CRO

5. Indicate the node names and go for AC Analysis with the output node

6. Observe the Ac Analysis and draw the amplitude response curve

7. Calculate the bandwidth of the amplifier

OUTPUT:

RESULT:

Hence the input and output waveforms of class-B push-pull power amplifier are observed.
 EXPERIMENTNO.12

COMPLEMENTARY SYMMETRY CLASS B PUSH-PULL POWER

AMPLIFIER

AIM:

To design a complementary-symmetry class-B push-pull power amplifier in order to

achieve maximum output AC power and efficiency by using Simulation software.
APPARATUS:

1. CRO(Dual channel)DC–20MHz
2. Function generator :1No.
3. Connecting wires :1Lot.
SOFTWARE TOOL:
 MULTISIM
THEORY:

Power amplifiers are designed using different circuit configuration with the sole
purpose of delivering maximum distorted output power to load. Push-pull amplifiers
operating either inclass-B are class-AB are used in high power audio system with high
efficiency.

In complementary–symmetry class-B power amplifier two types of transistors,

NPN and PNP are used. These transistors acts as emitter follower with both emitters

connected together. Saturation region. So, that only 180 0of the input signal is flowing
in the output. In complementary-symmetry power amplifier, during the positive half
cycle of input signal NPN transistor conducts and during the negative half cycle PNP
transistor conducts. Since, the two transistors are complement of each other and they
are connected symmetrically so, the name complementary-symmetry has come.
Theoretically efficiency of complementary-symmetry power amplifier is78.5%.
CIRCUIT DIAGRAM:

OUTPUTWAVEFORM
PROCEDURE:
1. Open Multisim Software to design the complementary-symmetry push-pull amplifier circuit

2. Select on New editor window and place the required component on the circuit window.

3. Make the connections using wire and check the connections and oscillator.

4. Go for simulation and using Run Key observe the output waveforms on CRO

5. Indicate the node names and go for AC analysis with the output node

6. Observe the Ac analysis and draw the amplitude response curve

7. Calculate the bandwidth of the amplifier

RESULT:

Hence the input and output waveforms of complementary-symmetry class-B push pull
power amplifier are observed.
 EXPERIMENTNO.13

SINGLE TUNED VOLTAGE AMPLIFIER

AIM:
To observe and analyze the output wave of single tuned Class C Tuned Voltage Amplifier
using simulation software.

APPARATUS:

 Transistor(BC107)-1no
 Signal source.
 Resistors-1kΩ(2),10kΩ(1),220Ω(1),47kΩ(1).
 Capacitors-10µf(3).

 C.R.O.

 Digital Multi meter.

 Bread Board.
 Connecting Wires.

SOFTWARE TOOL:

 MULTISIM

THEORY:

The power amplifier is said to be class C amplifier if the Q point and the input signals are
selected such the output signal is obtained for less than a half cycle, for a full input cycle.

Due to such a selection of the Q point, transistor remains active, for less than a half cycle.
Hence only that much part is reproduced at the output. For remaining cycle of the input cycle the
transistor remains cut off and no signal is produced at the output. The angle of the collector
current flow is less than 180 degrees. The current and voltage wave forms of a class C amplifier
operation are observed. But the efficiency of this class of operation is much higher and can reach
very close to 10%.
CIRCUIT DIAGRAM:

PROCEDURE:

1. Open Multisim Software to design the single tuned class c amplifier circuit

2. Select on New editor window and place the required component on the circuit window.
3. Make the connections using wire and check the connections and oscillator.

4. Go for simulation and using Run Key observe the output waveforms on CRO

5. Indicate the node names and go for AC analysis with the output node

6. Observe the Ac analysis and draw the amplitude response curve

7. Calculate the bandwidth of the amplifier

 OUTPUT:

RESULT:
Hence the input and output waveforms of single tuned voltage amplifier are observed.
 EXPERIMENTNO.14

DOUBLE TUNED VOLTAGE AMPLIFIER

AIM:

To study the characteristics of DOUBLE TUNED amplifiers using simulation software.

APPARATUS:

1. Signal generator
2. Oscilloscope
3. Tuned amplifier
4. Power supply

SOFTWARETOOL:

 MULTISIM

THEORY:

Tuned amplifier provide high constant gain over a specified bandwidth centered at a
specified frequency f and 8S much rejection as possible outside this band practical gain and
phase characteristics A single stage tuned amplifier is seldom used in practice.

Generally, double-tuned type as shown are preferred, due to using it in cascaded

amplification. However, alignment problem is more difficult in double tuned amplifiers, further
the bandwidth in multistage tuned amplifiers are less. This shrinking of bandwidth can be
avoided by the use of stagger tuning in which the input and the output circuits of each stage is
tuned to a slightly different frequencies.
 CIRCUITDIAGRAM:

PROCEDURE:

1. Open Multisim software to design the Double Tuned pair amplifier circuit

2. Select on New editor window and place the required component on the circuit window.

3. Make the connections using wire and check the connections and oscillator.

4. Go for simulation and using Run Key observe the output waveforms on CRO

5. Indicate the node names and go for AC analysis with the output node
6. Observe the Ac analysis and draw the amplitude response curve

7. Calculate the bandwidth of the amplifier

OUTPUT:

RESULT:
Hence the input and output waveforms of double tuned voltage amplifier are observed.
 ADDITIONAL EXPERIMENTS
EXPERIMENT NO. 1(HARDWARE)

SERIES VOLTAGE REGULATOR

AIM:

1. To study and stimulate a series voltage regulator and obtain the regulator
characteristics, load line and stabilization factor.
2. To verify the voltage regulation, regulation characteristics (load-line) and stabilization
factor using Spice software.

APPARATUS:

 Transistor.

 R.P.S(0-30V).

 Resistors-10kΩ(2),2.2Ω (2).

 Zener diode.

 Capacitor-0.01µf(2),0.1µf(3),10µf(1), 1µf 2).

 Digital Multimeter.

 Bread Board.

 Connecting Wires.

THEORY:-

A voltage regulator converts a DC input voltage into a chosen DC voltage which is stable
under conditions regulator is the pass transistor Q. The heart of the regulator is the pass transistor
Q. It is connected in series with the unregulated power supply V Iand the load. It is called the pass
transistor as ILpass through it.

The voltage divider network samples the output voltage. It provides a voltage proportional
to the output voltage V0. The sample voltage is compared with the V R by the operational
amplifier comparator. The comparator element (Q) which is connected in the emitter follower.
CIRCUITDIAGRAM:-

SERIES VOLTAGE REGULATOR

MODELGRAPH:-

LINEREGULATION
 LOAD REGULATION

OBSERVATIONS:

LINEREGULATION:

[Link] INPUTVOLTAGE(V) OUTPUTVOLTAGE(V)

1 1 0.48
2 2 1.46
3 3 2.55
4 4 3.57
5 5 4.45
6 6 4.85
7 7 4.97
8 8 5.02
9 9 5.05
10 10 5.07
11 11 5.08
12 12 5.09
13 13 5.10

14 14 5.11
15 15 5.12
LOADREGULATION:VNL=5.23V

LOAD LOAD LOAD % OF

[Link] RESISTORRL CURRENT VOLTAGE REGULATION
(Ω) (IL)inmA (VL)VOLTS
1 100 51.5 5.24 5.15
2 220 23.2 4.97 4.58
3 410 10.7 5.00 4.58

4 560 9.1 5.00 4.58

5 1K 5.0 5.00 4.58
6 2.2K 2.3 5.01 4.07
7 3.9K 1.3 5.03 3.81
8 4.7K 1.1 5.04 3.62
9 5.6K 0.9 5.05 3.62

10 10K 0.5 5.06 3.52

PROCEDURE:

Line Regulation:

 Connect the circuit as per circuit diagram.

 Vary the input voltage from 0 to 15V and Note the readings.

 Draw the Graph between VIN and Voutput.

Load Regulation:

 Set the input 8 v constant.

 Calculate the percentage of regulation.

 Set the input 8V constant and connect the ammeter in series with load resistor.

 Vary the load resistor from100ohms to 5KΩ and a gain take readings of V no-load and
calculate percent of regulation.
  Draw graph between VL vs. RL.

Load Line Regulation:

 Set the input 1V constant and connect the ammeter in series with load resistor and no load
resistor.

 By varying RL,set IL=5mA.

 Now Vary input voltage from10V to 15V and note VL reading and calculate percent of
regulation.

PRECAUTIONS:-

 The continuity of wires must be checked.

 The voltages levels in the RPS must be kept in minimum position before switching it “ON”
or “OFF”.

 The terminals of the transistor should be identified properly.

 Readings should be taken without errors.

 Inter connections should not be made on the breadboard with power switched on.

Result:

Hence the regulation Characteristics is thus verified by hardware implementation.

 SERIES VOLTAGE REGULATOR (Using Simulation)

AIM:
1. To study and stimulate a series voltage regulator and obtain the regulator characteristics,
load line and stabilization factor.
2. To verify the voltage regulation, regulation characteristics (load-line) and stabilization
factor using Spice software.

APPARATUS:

 Transistor.

 R.P.S(0-30V).

 Resistors-10kΩ(2),2.2Ω (2).

 Zener diode.

 Capacitor-0.01µf(2),0.1µf(3),10µf(1), 1µf 2).

 Digital Multimeter.

 Bread Board.

 Connecting Wires.

SOFTWARETOOL:

 MULTISIM

THEORY:-

A voltage regulator converts a DC input voltage into a chosen DC voltage which is stable under
conditions regulator is the pass transistor Q. The heart of the regulator is the pass transistor Q. It
is connected in series with the unregulated power supply V Iand the load. It is called the pass
transistor as ILpass through it.

The voltage divider network samples the output voltage. It provides a voltage proportional
to the output voltage V0. The sample voltage is compared with the V R by the operational
amplifier comparator. The comparator element (Q) which is connected in the emitter follower.
CIRCUITDIAGRAM:-

SERIESVOLTAGEREGULATOR

PROCEDURE:
1. Open Multisim Software to design the series voltage regulator circuit

2. Select on New editor window and place the required component on the circuit window.

3. Make the connections using wire and check the connections and oscillator.

4. Go for simulation and using Run Key observe the output waveforms on CRO

5. Indicate the node names and go for AC Analysis with the output node

6. Observe the Ac analysis and draw the amplitude response curve

7. Calculate the bandwidth of the amplifier

 OUTPUT:

RESULT:

Hence the regulation Characteristics are thus verified by software implementation.

 EXPERIMENTNO:2(HARDWARE)

SHUNT VOLTAGE REGULATOR

AIM:

1. To study and stimulate a shunt voltage regulator and obtain the regulator
characteristics, load line and stabilization factor.
2. To verify the voltage regulation, regulation characteristics (load-line) and stabilization
factor using Spice software.

APPARATUS:

 Transistor.

 R.P.S(0-30V).

 Resistors-10kΩ(2),2.2Ω (2).

 Zener diode.

 Capacitor-0.01µf(2),0.1µf(3),10µf(1), 1µf 2).

 Digital Multimeter.

 Bread Board.

 Connecting Wires.

THEORY:-

The heart of ant voltage regulator circuit is a control element. If such a control element is
connected in shunt with the load, the regulator circuit is called shunt voltage regulator. The
unregulated input voltage VIN, tries to provide the load current. But part of the current is taken by
the control element to maintain the constant voltage across the load. If there is any change in the
load voltage, the sampling circuit provides the feedback signal to the comparator circuit.

The comparator circuit compares the feedback signal with the reference voltage and generates a
control signal which decides the amount of current required to be shunted to keep the load
voltage increases then, comparator circuit decides the control signal based on feedback
information.
CIRCUITDIAGRAM:-

SHUNTVOLTAGE REGULATOR

MODELGRAPH:-

LINEREGULATION
 LOADREGULATION

OBSERVATIONS:

LINEREGULATION:

[Link] INPUTVOLTAGE(V) OUTPUTVOLTAGE(V)

1 1 1
2 2 2.02
3 3 3.00
4 4 4.03
5 5 4.95
6 6 5.64
7 7 6.00
8 8 6.03
9 9 6.05
10 10 6.06
11 11 6.06
12 12 6.07
13 13 6.07
14 14 6.07
15 15 6.07
LOADREGULATION:VNL=5.23V

LOAD LOAD LOAD % OF

[Link] RESISTORRL CURRENT VOLTAGE REGULATION
(Ω) (IL)inmA (VL)VOLTS
1 100 11.12 1.09 82.04
2 220 10.01 2.16 64.41
3 330 9.14 3.01 50.41

4 470 8.20 3.93 35.25

5 560 7.81 4.31 28.99
6 1K 5.81 5.76 5.10
7 1.8K 3.41 6.01 0.988
8 2.2K 2.79 6.02 0.823
9 3.9K 1.55 6.04 0.494

10 5.6K 1.09 6.05 0.329

11 10K 0.61 6.05 0.329

PROCEDURE:

Line Regulation:

 Connect the circuit as per circuit diagram.

 Vary the input voltage from 0 to 15V and Note the readings.

 Draw the Graph between VIN and Voutput.

Load Regulation:

 Set the input 8v constant.

 Calculate the percentage of regulation.

 Set the input 8Vconstant and connect the ammeter in series with load resistor.

 Vary the load resistor from100 ohms to5 KΩ and again take readings of V no-load and
calculate percent of regulation.
  Draw graph between VL vs .RL.

Load Line Regulation:

 Set the input 1V constant and connect the ammeter in series with load resistor and no load
resistor.

 By varying RL,set IL=5mA.

 Now Vary input voltage from 10V to 15V and note VL reading and calculate percent of
regulation.

PRECAUTIONS:-

 The continuity of wires must be checked.

 The voltages levels in the RPS must be kept in minimum position before switching it
“ON” or “OFF”.

 The terminals of the transistor should be identified properly.

 Readings should be taken without errors.

 Interconnections should not be made on the breadboard with power switched on.

Result:

Hence the regulation Characteristics are verified by hardware implementation.

 SHUNT VOLTAGE REGULATOR
(Using Simulation)

AIM:
1. To study and stimulate a shunt voltage regulator and obtain the regulator
characteristics, load line and stabilization factor.
2. To verify the voltage regulation, regulation characteristics (load-line) and stabilization
factor using Spice software.

APPARATUS REQUIRED:

 Transistor.

 R.P.S(0-30V).

 Resistors-10kΩ(2),2.2Ω (2).

 Zener diode.

 Capacitor-0.01µf(2),0.1µf(3),10µf(1), 1µf 2).

 Digital Multimeter.

 Bread Board.

 Connecting Wires.

THEORY:-

The heart of ant voltage regulator circuit is a control element. If such a control element is
connected in shunt with the load, the regulator circuit is called shunt voltage regulator. The
unregulated input voltage VIN, tries to provide the load current. But part of the current is taken by
the control element to maintain the constant voltage across the load. If there is any change in the
load voltage, the sampling circuit provides the feedback signal to the comparator circuit.

The comparator circuit compares the feedback signal with the reference voltage and
generates a control signal which decides the amount of current required to be shunted to keep the
load voltage increases then, comparator circuit decides the control signal based on feedback
information.
 CIRCUITDIAGRAM:-

SHUNTVOLTAGEREGULATOR

PROCEDURE:
1. Open Multisim Software to design the Shunt voltage regulator circuit

2. Select on New editor window and place the required component on the circuit window.

3. Make the connections using wire and check the connections and oscillator.
4. Go for simulation and using Run Key observe the output waveforms on CRO

5. Indicate the node names and go for AC analysis with the output node

6. Observe the Ac analysis and draw the amplitude response curve

7. Calculate the bandwidth of the amplifier

OUTPUT:
RESULT:

Hence the regulation Characteristics are verified by software implementation.