microprocessor_ CHAPTER 1 :-8086

Microprocessor

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-1
microprocessor_ CHAPTER 1 :-8086

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-2
microprocessor_ CHAPTER 1 :-8086

Chapter-1. 8086

Features of 8086:-
1) It-has a 20-bit address bus, hence it can access maximum 220 bytes of main memory
.i.e..
1MB. The address range of main memory is from 00000H to FFFFFH.
2) It has a 16-bit data bus and it has a 16-bit ALU, hence it is called as a 16-bit. microprocessor.
3) It supports 2-stage pipelining. The process of fetching next instruction while executing the current
instruction is known as pipelining.
4) It supports Memory Banking i.e. In 8086, the main memory chip is divided in to two banks in order to
fetch 16-bits of data in one cycle. The banks are termed as Lower or Even bank and Higher or Odd bank.
5) It has two operating one modes,
i. Minimum mode.
ii. Maximum mode.
In Minimum mode, there is only one processor in the system (uniprocessor).
In Maximum mode, there are processors other than 8086 in the system such as 8087,
étc. (Multiprocessor).
6) It supports Memory Segmentation.
Segmentation means dividing the memory in to logical components.
In 8086, the memory is divided in to 4 segments and they are as follows:
i. Code Segment
ii. Stack Segment.
iii. Data Segment.
iv. Extra Segment.
7) It has 256 interrupts.
8) It has a 16-bit IO address, hence it can access 226 10 ports (= 64k ports).

Memory Banking in 8086:-

In 8086, the size of data bus is 16 bits but we know one memory location can store only one byte of data
(i.e. 8 bits). So to make optimum use of data bus there is a need to fetch data from two memory locations
but an address bus cannot carry two addresses (or address of two memory locations) simultaneously. So
to solve above problem the main memory chip is divided in to two banks in such a way that the two
consecutive memory locations lie in different banks. Hence each bank contains alternate locations.
Therefore one bank contains all the even or lower addresses and is called as Even bank or Lower bank
and the other bank contains all the odd or higher addresses and is called as Odd bank or Higher bank. Now
by dividing the main memory chip in to two banks we can fetch 16-bit data in one cycle in
following way:-

1. Address bus carries the address of the location present in Even or Lower bank from which data needs
to be fetched .
2. Both the banks are enabled.
Even or Lower bank is enabled when Ao line is low i.e. Ao =0.
And Odd or Higher bank is enabled when BHE line is low i.e. BHE =0.
This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-3
microprocessor_ CHAPTER 1 :-8086

3. Since both the banks are enabled therefore one byte of data is fetched from the Even
or Lower bank and one more byte of data is fetched from Odd or Higher bank in one
cycle thereby 16-bit of data is fetched in one cycle.

Using memory banking concept we can fetch byte 16-bit of data in one cycle thereby we
are able to make optimal use of 16-bit data bus.

Banks are enabled in following way:-

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-4
microprocessor_ CHAPTER 1 :-8086

Architecture of 8086:-

Architecture of 8086 is divided in to two parts and they are as follows:-

1) Bus interface unit (BIU).
2) Execution unit (EU).

Bus interface unit consists of the following components:-

1) ES:-
It is a 16-bit segment register which stores the segment or base address of the extra
segment.

2) CS:-
It is a 16-bit segment register which stores the segment or base address of the code segment.

3) DS:-
It is a 16-bit segment register which stores the segment or base address of the data segment.

4) SS:-
It is a 16-bit segment register which stores the segment or base address of the extra segment.

5) Instruction Pointer(IP):-
It is a 16-bit offset register which stores an offset address of the next instruction which is to be
fetched from a code segment.
This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-5
microprocessor_ CHAPTER 1 :-8086

6) Address Generation Circuit:-

In 8086 Address Generation Circuit calculates 20-bit physical address using offset and segment
addresses using the following formula:-
Physical Address (PA) = Segment Address* 10H + Offset Address.

7) 6-Byte Pre-Fetch Queue :-

It is a 6-byte FIFO RAM used to implement pipelining.
The process of fetching the next instruction while executing the current instruction is known as
pipelining.
BIU fetches the next six instruction bytes from the code segment and stores in the queue.
Execution Unit removes the instruction bytes from the queue and executes them.
Since the size of data bus in 8086 is 16-bit bus therefore queue is refilled when atleast two bytes
of the queue are empty.
Pipelining increases the efficiency of the microprocessor.
Pipelining fails when a branch occurs, as the pre-fetched instructions are no longer useful.
Hence as soon as microprocessor detects a branch [Link] clears or discards the
instructions present or stored in the queue and new instructions are fetched from the
new location and stored in the queue and pipelining continues.

Execution Unit consists of the following components:-

1) General Purpose Registers:-

Those registers which are available to the programmers for their own use are termed as general
purpose registers.
In 8086 there are 4 16-bit general purpose registers and they are AX, BX, CX and DX
These 4 16-bit general purpose registers can also be operated as 8 8-bit general purpose registers and
they are AH, AL, BH, BL, CH, CL, DH and DL.

2) Stack Pointer(SP) :-
It is a 16-bit special purpose register which is used to store the offset address of the stack top symbol.

3) Base Pointer(BP):-
It is a 16-bit special purpose register which is used to store the offset address of any random location
in the stack segment

4) Source Index(SI):-
It is a 16-bit special purpose register which is used to store the offset address of a location in a data
segment.

5) Destination Index(DI):-
It is a 16-bit special purpose register which is used to store the offset address of a location in an extra
segment.

6) ALU:-
In 8086 there is a 16-bit ALU which is used to perform arithmetic and logic operations.

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-6
microprocessor_ CHAPTER 1 :-8086

7) Operand Register :-
It is 16-bit special purpose register which is used to store the data temporarily.

8) Control System :-
Inside control system there are instruction register and instruction decoder.
EU fetches the instruction from the queue and stores in the instruction register then the instruction
decoder decodes the instruction and sends the information to the control circuit for execution.

9) Flag Register :-
8086 has a 16-bit flag register.
It has 6 status flags and 3 control flags.
Status flags are those flags which are affected or updated due to ALU operations are known as Status
flag.
Control flags are those flags which are used by the programmer to control certain operations.

Diagram :-

Status Flags :-

1) Carry Flag(CY):-
It is set whenever there is a carry generated out of the MSB of the result.

2) Parity Flag(PF) :-
It is set when there is even parity (.i.e. even number of one's) in the result.

3) Auxiliary Carry Flag(AC) :-

It is set whenever there is a carry generation from lower nibble to higher nibble.

4) Zero Flag(ZF):-
It is set whenever the result of an operation is equal to zero.

5) Sign Flag(SF) :-
It is set whenever the MSB of a result is 1.

6) Over Flow Flag(OF) :-

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-7
microprocessor_ CHAPTER 1 :-8086

It is set whenever overflow is occurred (i.e. if result of a signed operation is large enough to fit in the
number of bits available to represent it then this situation is termed as an overflow).

Control Flags :-

1) Direction Flag(DF) :-
When this flag is set (i.e. DF=1) the microprocessor enters the auto-decrement mode.

2) Interrupt Enable Flag(IF) :-

When this flag is set (i.e. IF=1) the masked interrupts are enabled.

3) Trap Flag(TF) :-
When this flag is set (i.e. TF=1) the microprocessor enters the single stepping mode.

MEMORY SEGMENTATION IN 8086:-

Diagram:-

Memory segmentation refers to dividing the main memory in to logical components.

8086 has a 20-bit address bus therefore it can access maximum 220 bytes of main memory i.e.
1MB.
In 8086 we divide the main memory in to four components i.e. segments and they are as
follows
1) Code Segment.
This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-8
microprocessor_ CHAPTER 1 :-8086

2) Stack Segment
3) Data Segment.
4) Extra Segment
In 8086 the maximum size of a segment can be 64KB and minimum size of a segment can be 16 bytes.
In 8086 a programmer can define multiple segments of a particular type but it can access maximum 4
segments at a time.
In 8086 there are 4 16-bit registers such as CS,SS,DS and ES to hold the base address of the
segments and it also has 16-bit offset registers to hold the offset address for each of the segments.

Code Segment:-
This segment is used to store programs and instructions.
CS is a 16-bit segment register which stores the Segment or base address for the code segment.
IP is a 16-bit offset register which stores the offset address of the next instruction which is to be fetched
from the code segment.

Stack Segment :-
This segment is used to store the data in a particular manner i.e. in LIFO manner.
SS is a 16-bit segment register which stores the segment or base address for the stack segment.
SP is a 16-bit offset register which stores the offset address of the stack top symbol.
BP is a 16-bit offset register which stores the offset address of any random in stack segment.

Data Segment :-
This segment is used to store the data.
Ds is a 16-bit segment register which stores the segment or base address for the data segment.
SI(Source Index) is a 16-bit offset register which stores the offset address of a location in the data
segment.

Extra Segment :-
This segment is used store the data.
ES is a 16-bit segment register which stores the segment or base address for the extra segment.
DI(Destination Index) is a 16-bit offset register which stores the offset address of a location in
the extra segment.

Address Calculation:-
8086 calculates 20-bit physical address using segment address and offset address using the
following formula:-
Physical Address = Segment Address * 10H + Offset Address.

Advantages of Segmentation :-
Using segmentation we can access 1MB of main memory using 16-bit address.

Disadvantages of Segmentation :-
Due to segmentation, at a time we can access only 4* 64KB of main memory i.e. 256KB instead

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-9
microprocessor_ CHAPTER 1 :-8086

Pin Diagram of 8086:-

CLK:-
In 8086 clock is provided to microprocessor by 8284 clock generator.
8086 has a 33% duty cycle so to provide 6MHZ clock we will need to connect 18MHZ external clock
frequency.

RESET:-
In 8086 the microprocessor is reset or formatted through reset pin.
8086 is reset by connecting an external 8284 clock generator.
When microprocessor is reset, it clears the flag register, the instruction queue, registers such as DS,ES,SS
and IP and sets the bits of CS register.
Therefore the reset vector address of 8086 is FFFFOH (i.e. after microprocessor is reset CS=FFFFH and
IP= 0000H therefore Physical or reset address = CS*10H+offset address i.e.
FFFFH*10H+0000H=FFFFOH).

READY:-
This pin is used to synchronize the microprocessor with the slower peripheral devices.
Devices inform the microprocessor whether they are ready or not through this pin.
The microprocessor checks this pin during T3 state of machine cycle and if suppose a device is not readyit
sends 0 on this pin thereby indicating to microprocessor that it is not ready.
Then the microprocessors insert wait states between T3 and T4 states and will come out of the
wait state only when the device is ready for further computation I.e. when it sees 1 on the
ready pin.
TEST:-
This pin is dedicated or reserved for 8087 co-processor.
The microprocessor checks this pin only when it encounters wait instruction.
This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-10
microprocessor_ CHAPTER 1 :-8086

If the 8087 co-processor is busy it makes this pin high indicating to microprocessor that it is that busy.
Then microprocessor enters the wait state and come out of the wait state only after this pin is made low
by the 8087 co-processor i.e. when 8087 is free or ready for further computations.

MN/MX:-
This pin is a multiplexed pin and it is used to indicate the operating mode in which the
microprocessor is operating or working in (i.e. minimum mode or maximum mode).
If this pin is high then the microprocessor is operating in minimum mode.
If this pin is low then the microprocessor is operating in maximum mode.

NMI:-
NMI is a non-maskable, edge triggered, high priority interrupt pin.
On receiving an interrupt on NMI line, the microprocessor executes INT2 i.e. control is shifted
to location 2*4=00008H in the IVT, to get the value of CS and IP register to locate the ISR and
service or execute it.

INTR:-
This is a maskable, level triggered, low priority interrupt pin.
On receiving an interrupt on INTR line, the microprocessor issues 2 INTA Pulses.
On the first INTA Pulse, PIC calculates vector number N and on the second INTA Pulse, PIC
sends the vector number N to the microprocessor through the data bus.
Now the microprocessor will multiply N*4 and go to the IVT to obtain the ISR address (I.e. CS & IP).

RD:-
When this pin is low it indicates the microprocessor is performing read operation either from memory
or I0.

VCC and GND:-

These pins are used to provide power supply to the microprocessor.

AD15-AD0:-
In 8086 there is a multiplexed address and data bus.
When ALE pin is high it indicates that the multiplexed bus contains address in it and when the ALE pin
is low it indicates that the multiplexed bus contains data in it.

A16/S3-A19/S6:-
A16-A19 lines carries the address during T1 of every machine cycle and from T2 onwards status signals
S3-S6 are active.
S3 and 54 signals are used to indicate the memory segment which is currently used.
S5 gives the status of the Interrupt Enable Flag.
S6 goes low when 8086 controls the System bus.

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-11
microprocessor_ CHAPTER 1 :-8086

BHE/S7:-
It carries BHE during the T1 machine cycle.
BHE line is used to enable the higher bank.
From T2 machine cycle onwards it carries S7 signal which is reserved for further development.

MIN/MAX MODE SIGNALS:-

HOLD....RQO/GTO:-
In minimum mode this line carries Hold Sie
Hold signal is used to perform direct memory access(DMA).
In 8086 DMAC issues the Hold signal to request the microprocessor to become the bus master of the
System bus.
In maximum mode this line carries RQ0/GTO signal.
The external bus master sends an active low pulse to the microprocessor to request for the access of System
bus.
In response 8086 completes the current bus cycle and releases the System bus and sends an active low
grant pulse on the same line to the external bus controller.
8086 gets back the System bus only after external bus master sends an active low release pulse on the
same line.

HLDA....RQ1/GT1:-
In minimum mode this line carriers HLDA signal.
This signal is issued by the microprocessor in response to DMAC'S HOLD signal i.e. when the
microprocessor is about to releases the System bus it acknowledges the Dmac with the help of this signal.
In maximum mode this line carriers RQ1/GT1.

WR....LOCK:-
In minimum mode this line carriers WR Signal.
When WR signal is low it indicates that the microprocessor is performing a write operation.
In maximum mode this line functions as LOCK output line.
When this signal is low the external bus master cannot take the control of the System bus.
This signal is activated when the microprocessor executes an instruction with Lock prefix.

DENSO:-
In minimum mode this line carriers DEN signal. When this signal is low the data trans-receivers are
enabled. In maximum mode this line carriers SO.

DT/RS1:-
In minimum mode this line carriers DT/R signal.
When this signal is high the data is being transmitted and when this is low the data is being received.
In maximum mode this line carriers S1 signal.

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-12
microprocessor_ CHAPTER 1 :-8086

M/10 ...S2:-
In minimum mode this line carriers M/10 signal.
When this signal is high it indicates a memory operation is being performed and when this signal is low
it indicates an IO operation is being performed. Perto
In maximum mode this line carriers S2 signal.

ALE... QSO:-
In minimum mode this line carriers ALE signal.
When ALE signal is high then it is concluded that the multiplexed bus carriers the address in it and when
ALE signal is low then it is concluded that the multiplexed bus carriers data in it. In maximum mode this
line carriers QSO signal.

INTA... QS1:-
In minimum mode this line carriers INTA signal.
On first pulse of INTA signal, PIC calculates the vector number N.
On second pulse of INTA signal, PIC sends the vector number N to the microprocessor through the data
bus.
In maximum mode this line carriers QS1 signal.

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-13
microprocessor_ CHAPTER 1 :-8086

Interrupts in 8086:-

• Interrupt can be described as a special condition that arises during the execution of the program
• There are two types of interrupts and they are maskable interrupts and non-maskable interrupts.
• In 8086 there are total 256 interrupts.
• In 8086 interrupts can be generated in three ways and they are as follows:-

1. Internally generated interrupts:-

In this type, the microprocessor is interrupted due to some special conditions that arises during the
execution of certain instructions in the program.
Eg. An error in division automatically causes the INT O interrupt.

2. Software Interrupts:-
In this type an interrupt is invoked by writing a software instruction INT n where
"n" can be any value from 0 to 255.
Eg. INT 03H is a software interrupt for breakpoint.

3. Hardware Interrupts:-
In this type, the interrupts occurs as a signal on the of the microprocessor.
In 8086 there two hardware pins and they are NMI and INTR.

• The microprocessor services an interrupt by executing a subroutine called as ISR (Interrupt Service
Routine).
• The address of the ISR is stored in a table called as IVT (Interrupt Vector Table)

Interrupt Vector Table (IVT):-

• An IVT contains the ISR addresses for the 256 interrupts.
• Each ISR address is stored as CS and IP.
• Therefore to store each ISR's address 4 bytes are required (2 bytes to store CS and 2 bytes to store
IP).
• Therefore in 8086 the size of IVT is 1KB (because to store each ISR address it requires 4 bytes
and there are such 256 interrupts in 8086 i.e. 4 * 256 = 1KB).
• The first 1KB of the memory is reserved for the IVT (i.e. addresses from 00000H to 003FFH are
reserved for IVT).
• Whenever an interrupt INT N occurs, the microprocessor performs N* 4 to get the address of the
ISR (i.e. values of IP and CS) from the IVT and hence executes the ISR.

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-14
microprocessor_ CHAPTER 1 :-8086

Interrupt Vector Table can be classified mainly in to three parts and they are as follows:-
1) Dedicated Interrupts:-
In 8086, Dedicated Interrupts are further classified in to five and they are as follows:-

1) INT 0 (Divide Error):-

This interrupt occurs whenever there is a division error i.e. when the result of a division is too large to be
stored.
This condition normally occurs whenever the dividend is large and divisor is comparatively too small or
it is zero.
Its ISR address is stored at location 0*4=00000H in the IVT.

II) INT 1 (Single Step):-

Whenever the trap flag is set (i.e. TF=1), the microprocessor enters in single stepping mode i.e. it stops
after executing every instruction.
Its ISR address is stored at location 1*=00004H in the IVT,
Single stepping is used in debugging and its ISR displays the contents of all the registers.

III) INT 2 (NMI):-

Whenever an interrupt occurs on the NMI line, the microprocessor goes to fetch the ISR address
which is stored at location 24-00008H in the IVT and executes the ISR.

IV) INT 3 (Breakpoint):-

This interrupt is used to create Breakpoints in the program.
It can be done by simply writing INT 03H and INT instruction.
Breakpoints are generally used in large programs where inefficient. using single stepping is

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-15
microprocessor_ CHAPTER 1 :-8086

inefficient.
Its ISR displays the contents of all the registers
Its ISR address is stored at a location 3*4=0000CH in the IVT

V) INT 4 (Overflow Interrupt):-

Whenever the overflow flag is set (i.e. OF=1), the microprocessor executes INTO instruction.
It is used to detect overflow error in signed arithmetic operations.
Its ISR address is stored at location 4* *4 =00010H in the IVT.

2) Reserved Interrupts:-
Interrupts INT 5 to INT 31 are reserved in 8086 for the further development and these
interrupts are not available to the user.

3) User Defined Interrupts:-

Interrupts INT 32 to INT 255 are user defined, software interrupts.
The ISRs for these interrupts are written by the users to service the user defined
conditions.
These interrupts are invoked by writing the instruction INT N.
To execute the ISR of the user defined interrupts, the microprocessor fetches the ISR address which
is stored at the location N *4 in the IVT.

ADDRESSING MODES OF 8086:-

In 8086 addressing modes is mainly classified in to five types and they are as follows:-

1. Immediate Addressing Mode

In this type of an addressing mode operands are directly specified in the instruction itself.
In this type operands can be easily identified.
In this type the length of the instructions are longer.
Eg:- 1) MOV BL, 23H.
2) MOV CX, 2332H.

2. Register Addressing Mode :-

In this type of an addressing mode the operands are specified using registers.
In this type operands cannot be easily indentified.
In this type the length of the instructions are shorter as compared to immediate
addressing mode.
Eg: 1) MOV BL, CL, 2) MOV BX,CX.
3. Direct Addressing Mode:-
In this type of an addressing mode the address of the operand is directly specified in the instruction
Itself.
Here only offset address is specified, the segment being indicated by the instruction.
Eg: 1) MOV BX, [1234H].

4. Indirect Addressing Mode:-

i) Register Indirect Addressing mode
In this type of an addressing mode the addresses are specified using registers.
This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-16
microprocessor_ CHAPTER 1 :-8086

In this type any of the two base registers BP,BX or any of the two index registers SI,DI to provide
the offset address for the data byte.
BX indicates Data Segment and BP indicates stack segment
Eg: 1)MOV DL, [BX].
2)MOV [BP], DL.

ii) Register Relative Addressing Mode:-

In this type of an addressing mode the address of the operands are specified using one of the base
registers and a 8-bit or a 16-bit displacement.
Eg. 1)MOV DL, [BX+8].
2)MOV 12H[BP], CL.

iii) Base Indexed Addressing Mode:-

In this type of an addressing mode the address of the operand is specified using a base register
and an index register.
Eg. 1)MOV DL, [BX+SI].
2)MOV [BP+DI], DL.

iv) Base Relative Plus Index Addressing Mode:-

In this type of an addressing mode the address of the operand is specified using a base register
and an index register and a 8-bit or a 16- bit displacement
Eg.1)MOV DL, [BX+SI+8].
2)MOV [BP+SI+12],DL.

5. Implied Addressing Mode:-

In this type of an addressing mode the address of the operands are already implied i.e. there is no
need to specify the operands.
Eg. 1)CMC.
2)STD.

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-17
microprocessor_ CHAPTER 1 :-8086

8282-8 bit (octal) latch:-

1. In 8086, the address bus is multiplexed with the data bus and the status signals.
2. When ALE is high it indicates the multiplexed bus contains the address.
3. 8282 is used to latch the address from the multiplexed bus.
4. Therefore ALE signal is connected to the STB(strobe) of 8282.
5. When STB signal of 8282 is high, the input is latched and transferred to the output. Hence address is
latched.
6. When STB signal of 8282 is low, the input is discarded so the data is not latched and the previously
latched address remains at the output.
7. The size of an address bus in 8086 is 20 bits and BHE signal is latched, so in all 21 bits are latched
and 8282 is a 8 bit octal latch so 3 latches are required.
8286-8 bit Data Trans-receiver:-

1. 8286 is a 8-bit data trans receiver.

2. It allows 8086 to either transmit the data or to receive the data through it (i.e. it acts as a bi-directional
buffer).
3. In 8086 the size of data bus is 16-bits, hence 2 8-bit trans receivers are required.
4. In minimum mode OE of 8286 is connected with DEN of 8086 and in maximum mode OE of 8286

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-18
microprocessor_ CHAPTER 1 :-8086

is connected with DEN of 8288.

5. T of 8286 is connected with DT/R of 8086.
If T=1 then data is transmitted.
If T=0 then data is being received.
6. 8286 is enabled when OE is low.
7. 8286's main function is to prevent the address and allow the data to be transferred on the data bus.
8. During the 1st T-state the bus contains address l.e. bus does not contains data,
therefore DEN of 8086 is high hence the OE of 8286 is high therefore the trans receiver is disabled.
Thereafter when bus contains data then DEN of 8086 is low hence the OE of 8286 is low and the
trans receiver is enabled and thus it only allows data to flow.

8284-Clock Generator:-
BLOCK DIAGRAM:-

8284 interfaced with 8086:-

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-19
microprocessor_ CHAPTER 1 :-8086

1. 8284 is a clock generator and it provides clock to 8086.

2. Besides providing clock it also synchronizes Ready and Reset signal where Ready signal indicates
that an interface is ready for data and Reset signal is used to initialize the system.
3. 8086 has a 33% duty cycle i.e. output clock frequency=1/3rd of the input clock frequency.
4. In two ways frequency can be provided to 8284 and they are as follows:-
i. Through X1,X2.
An oscillator can be connected across X1,X2 to provide clock signal at constant frequency.
ii. Through EFI pin.
A pulse generator circuit can be connected to EFI pin to provide an external frequency signal.
5. Clock selection is done using F/C pin, F/C = 1 then input clock is provided through EFI pin and if
F/C=0 then input clock is provided through X1,X2 pins.

8086 Minimum Mode:-

HOONG MIN MODE

1) When 8086 is operating in minimum mode it indicates that there is only one processor (8086) in
the system i.e. it is an uniprocessor system.
2) When MN/MX=1, then 8086 operates in minimum mode.
3) In minimum mode, 8284 clock generator is to the microprocessor to provide CLK, RESET and
READY Signals.
4) In minimum mode, 8282 8-bit latch is connected to the microprocessor to latch the address from the
multiplexed bus,
5) In 8086, the size of address bus is 20-bit therefore three such 8-bit latches are required.
6) The ALE of 8086 is connected to the STB of 8282.
This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-20
microprocessor_ CHAPTER 1 :-8086

7) In minimum mode, the microprocessor either transmits or receives data through 8-bit trans-receiver.
8) In 8086, the size of data bus is 16-bit therefore such two trans-receivers are required.
9) DT/R pin of 8086 is connected to T pin of 8286 and DEN pin of 8086 is connected to OE of 8286.

10) M/10, RD, WR signals are decoded using 3:8 decoder like IC 74138.
11) In minimum mode, HOLD and HLDA signals are used to perform direct memory access.
12) when microprocessor is interrupted on the INTR line, it issues INTA signal.

TIMING DIAGRAMS:-

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-21
microprocessor_ CHAPTER 1 :-8086

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-22
microprocessor_ CHAPTER 2 Instruction set of 8086

Chapter-2. Instruction Set of 8086:-

Data Transfer Instructions:

1. MOV Destination, Source

Moves a byte/word from source to the destination specified in the instruction.
Source Register, Memory location, Immediate number
Destination Register or memory location

Eg: MOV CX,0037H which means CX-0037H

MOV BL, [4000H] which means BLDS: [4000H]

2. PUSH Src
Push the source (word) into the stack and decrement the stack pointer by two
Src Register, Memory location

Eg PUSH CX; SS[SP-1]←CH, SS[SP-2]←CL

; SP ←SP-2

PUSH DS ;DS←SS[SP,SP+1]
; SP←-SP-2

3. POP Destination
POP a word from stack into given destination and increment stack pointer by 2.
Destination must be word(16 bit)
Destination Register (except CS), Memory location
Eg POP CX; CH← SS[SP],CL←SS:[SP+1]
; SP-←SP+2

4. PUSHF
Push the value into flag register and decrement stack pointer by 2
Eg PUSHF ;SS[SP-1]←Flag, SS[SP-2] ←Flag, SP SP-2

5. POPF
POP a word from the stack into the Flag register
Eg POPF Flag SS: [SP], Flag, SS: [SP+1] , SP SP +2

6. XCHG Destination, Source

Exchange a byte/word between the source and destination specified in the instruction
Source →Register, Memory location
Destination → Register, Memory location
Eg XCHG CX,BX CX →BX

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-1
microprocessor_ CHAPTER 2 Instruction set of 8086

[Link]
Move Into AL, the contents of the formed by the sum of BX and AL. memory location in Data Segment,
whose effective address
EG: XLAT ALDS:[BX+AL];
i.e if DS 1000H; BX =0200H; AL = 03H
10000 .... DS 16;
+0200 ….BX
+ 03 .....AL
= 10203H AL+[10203H);

8) LAHF
Loads AH with lower byte of the Flag Register.

9) SAHF
Stores the content of AN into the lower byte of the Flag Register.

10) LEA register, source

Loads effective address (offset address) of the source into the given register.
eg LEA BX, Total; BX offset address of Total in Data Segment

11)LDS destination register, source

Loads the destination register and DS register with offset address and segment address
specified by the source.
Eg: LDS BX, Total ; BX (DS: [Total], DS: [Total + 1]))
;DS{DS: [Total + 2],DS; [Total + 3]))

12) LES destination register, source

Loads the destination register and ES register with the offset address and the segment address
indirectly specified by the source
Eg: LES BX, Total ; BX {DS: [Total], DS: [Total + 1]}
;ES (DS: [Total + 2], DS: [Total + 3])
13)IN destination register, source port
Loads the destination register with the contents of the I/O port specified by the source.
Source: 8-bit address of I/O Port [Direct addressing] Or: DX register [Indirect addressing]
Destination: AL/AH for 8-bit Port (NOT necessarily 8-bit port address),
AX for a 16-bit Port

Eg: IN AL, 8OH ;AL← [80H]/o as I/O Port 80H in an 8-bit port
IN AX, 8OH ; AX [80H]vo as I/O Port 80H in an 16-bit port
IN AL, DX ; AL← [DX]1/0 as I/O Port pointed by DX in an 8 bit port
IN AX, DX ; AX← [DX]1/o as I/O Port pointed by DX in an 16 bit port

14)OUT destination port, source register

Loads the destination I/O port with the contents of the source register.
Eg OUT 80H, Al ; [80H]1/0 ←AL as I/O Port 80H in an 8-bit port
OUT 80H, AX : [80H]1/0 ←AX as I/O Port 80H in an 16-bit port
OUT DX, AL ; [DX]VO AL as I/O Port pointed by DX in an 8 bit port
OUT DX, AX ; [DX]1/0 AX as I/O Port pointed by DX in an 16 bit port

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-2
microprocessor_ CHAPTER 2 Instruction set of 8086

Arithmetic Instructions :-
1) ADD/ADC destination, source
Adds the source to the destination and stores the result back in the destination.
Source: Register, Memory Location, Immediate Number
Destination: Register
Both, source and destination have to be of the same size.
ADC also adds the carry into the result.
Eg: ADD AL, 25H ; AL ←AL + 25H
ADD BL,.CL ; BL ←BL + CL;
ADC BX, CX ; BX ←BX + CX + Carry Flag

2) SUB/SBB destination, source

It is similar to ADD/ADC except that it does subtraction.

3) INC destination
IN AL, DX ; AL← [DX]/o as I/O Port pointed by DX in an 8 bit port
IN AX, DX ¡AX← [DX]1/o as I/O Port pointed by DX in an 16 bit port

14)OUT destination port, source register

Loads the destination I/O port with the contents of the source register
Eg OUT 80H, Al ; [80H]1/0 ←AL as I/O Port 80H in an 8-bit port
OUT 80H, AX ; [80H]1/0←AX as I/O Port 80H in an 16-bit port
OUT DX, AL ; [DX]1/0←AL as I/O Port pointed by DX in an 8 bit port
OUT DX, AX ; [DX]vo ←AX as I/O Port pointed by DX in an 16 bit port

Arithmetic Instructions :-

1) ADD/ADC destination, source

Adds the source to the destination and stores the result back in the destination.
Source: Register, Memory Location, Immediate Number
Destination: Register
Both, source and destination have to be of the same size.
ADC also adds the carry into the result.
Eg: ADD AL, 25H ; AL←AL+25H
ADD BL,.CL ; BL← BL + CL;
ADC BX, CX ; BX ←BX + CX + Carry Flag

2) SUB/SBB destination, source

It is similar to ADD/ADC except that it does subtraction.

3) INC destination
Adds "1" to the specified destination. Destination: Register, Memory Location
Note: Carry Flag is NOT affected.

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-3
microprocessor_ CHAPTER 2 Instruction set of 8086

Eg: INC AX AX← AX +1

INC BL ; BL← BL+1;
INC BYTE PTR [BX] Increment the byte pointed by BX in the Data Segment; i.e. DS:[BX] ←
DS;[BX + 1]
INC WORD PTR [BX] Increment word pointed by BX in the Data Segment ;-(DS[BX], DS:[BX+1]);
← (DS.[BX], DS[BX+1])+1

4) DEC destination
It is similar to INC. Here also Carry Flag is NOT affected

5) MUL source (unsigned 8/16-bit register)

If the source is 8-bit, it is multiplied with AL, and the result is stored in AX (AH-higher byte, AL-
lower byte)
If the source is 16-bit, it is multiplied with AX and the result is AX-lower byte
Source: Register, Memory Location
MUL affects AF, PF, SF and ZF.
Eg:MUL BL ;AX← AL X BL
MUL BX ; DX-AX ←AX X BX
MUL BYTE PTR [BX] ;AX AL x DS:[BX]

6) IMUL source(signed 8/16-bit register)

Same as MUL except that the source is a SIGNED number.

7) DIV source(unsigned 8/16-bit register - divisor)

This instruction is used for UNSIGNED division.
Divides a WORD by a BYTE, OR a DOUBLE WORD by a WORD.
If the divisor is 8-bit then the dividend is in AX register.
After division, the quotient is in Al and the Remainder in AH.
If the divisor is 16-bit then the dividend is in DX-AX registers.
After division, the quotient is in AX and the Remainder in DX.

Source: Register, Memory Location

ALL flags are undefined after DIV instruction.
Eg: DIV BL ;AX + BL AL← Quotient; ← AH Remainder
DIV BX ; (DX,AX) +BX:- AX Quotient; DX← Remainder
Please note If is too large to fit in AL AX for [Link] divisor then 8086 does a type o interrupt (divide error)

8) IDIV source (signed 8/16-bit register - divisor)

Same as div except that it is used for signed division

9) NEG destination
This instruction form the 2,s complement of the destination ,and stores it back in the destination .
Destination: Register, memory location
ALL condition flags are updated.
Eg: Assume AL= 0011 0101 35 H then NEG AL AL← 1100 1011 CBH. i.e. AL← 2's Complement
(AL)

10) CMP destination, source

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-4
microprocessor_ CHAPTER 2 Instruction set of 8086

This instruction compares the source with the destination.

The source and the destination must be of the same size.
Comparison is done by internally SUBTRACTING the SOURCE form DESTINATION.
The result of this subtraction is NOT stored anywhere, instead the Flag bits are affected.
Spurce: Register, Memory Location, Immediate Value.
Destination: Register, Memory Location - ALL condition flags are updated.
Eg: CMP BL, 55H; BL compared with 55H i.e. BL-55H.;

11) CBW [Convert signed BYTE to signed WORD]

This instruction copies sign of the byte in Al into all the bits of AH All is then called sign extension
of AL.
No Flags affected.
Eg: Assume AX = XXXX XXXX 1001 0001
Then CBW gives AX = 1111 1111 1001 0001
Then CWD gives AX = 1000 0000 1001 0001
DX=1111 1111 1111 1111
Note: Both CBW and CWD are used for Signed Numbers.
Decimal Adjust Instructions

13) DAA [Decimal Adjust for Addition]

It makes the result in packed BCD form after BCD addition is performed. It works ONLY on AL
register.
All Flags are updated; OF becomes undefined after this instruction.
For AL register ONLY IF D3 - Do > 9 OR Auxiliary Carry Flag is set => ADD 06H to AL.
If D7-D49 OR Carry Flag is set => ADD 60H to AL.
Assume AL = 14H CL = 28H Then ADD AL, CL gives AL = 3CH
Now DAA gives AL = 42 (06 is added to AL as C > 9) If you notice, (14)10+(28)10 (42) 10

14) DAS [Decimal Adjust for Subtraction]

It makes the result in packed BCD form after BCD tubtraction is performed. It works ONLY on AL
register.
All Flags are updated; OF becomes undefined after this instruction.
for AL register ONLY IF D3.- . Do > 9 OR Auxiliary Carry Flag is set =>subtract 06H from AL .
If D7 D4 > 9 OR Carry Flag is set => Subtract 60H from AL.
Assume AL = 86H CL5711 Then SUB AL, CL gives AL = 2FH.
Now DAS gives AL = 29 (06 is subtracted from AL as F > 9) If you notice, 86)10-(57) 10 = (29) 10
ASCII Adjust Instructions (for the AX register ONLY)

15) AAA [ASCII Adjust for Addition]

It makes the result in unpacked BCD form. In ASCII Codes, O …..9 are represented as 30 39
When we add ASCII Codes, we need to mask the higher byte (Eg: 3 of 39).
This can be avoided if we use AAA instruction after the addition is performed.
AAA updates the AF and the CF; But OF, PF, SF, ZF are undefined after the instruction.
Eq: Assume AL = 0011 0100... ASCII 4.
CL0011 1000... ASCII 8.
Then ADD AL, CL gives AL = 01101100 i.e. AL = 6CH ... it is the Incorrect temporary Result

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-5
microprocessor_ CHAPTER 2 Instruction set of 8086

16) AAS (ASCII Adjust for Subtraction]

It makes the result in unpacked BCD form. In ASCII Codes, O... 9 are represented as 30 ... 39.
When we subtract ASCII Codes, we need to mask the higher byte (Eg: 3 of 39). This can be
avoided if we use AAS instruction after the subtraction is performed. AAS updates the AF and the
CF; But OF, PF, SF, ZF are undefined after the instruction. Ea: Assume AL = 0011 1001... ASCII 9. CL
= 0011 0101... ASCII 5. Then SUB AL, CL gives AL = 0000 0100 i.e. AL = 04H Now AAS gives AL =
0000 0100... Unpacked BCD for 4. Carry = 0... this indicates that the answer is 04.

17) AAM [BCD Adjust After Multiplication]

Before we multiply two ASCII digits, we mask their upper 4 bits. Thus we have two unpacked BCD
operands. After the two unpacked BCD operands are multiplied, the AAM instruction converts this result
intc unpacked BCD form in the AX register. AAS updates PF, SF ZF; But OF, AP, CF are undefined after
the instruction. Eq: Assume AL = 0000 1001 ... unpacked BCD 9. CL = 0000 0101 ... unpacked BCD 5.
Then MUL CL gives AX = 0000 0000 0010 1101 = 002DH. Now AAM gives AX = 0000 0100 0000
0101 = 0405H. This is 45 in the unpacked BCD form.
18)AAD (Binary Adjust before Division) This instruction converts the unpacked BCD digits in AH and
Al into a Packed BCD in AL. AAD updates PF, SF ZF; But OF, AF, CF are undefined after the instruction.
Eg: Assume CL = 07H. AH = 04. AL = 03. AX = 0403H... unpacked BCD for (43)10 Then AAD gives
AX = 002BH i.e. (43)i0 Now DIV CL gives (divide AX by unpacked BCD in CL) AL = Quotient = 06...
unpacked BCD AH = Remainder = 01 unpacked BCD Logical Instructions Bit Manipulation instructions

1) NOT destination This instruction forms the I's complement of the destination, and stores it back in the
destination. Destination: Register, Memory Location. No Flags affected. Eg: Assume AL=0011 0101
NOT AL
; AL ←1100 1010 ... i.e. AL = I's Complement (AL)

2) AND destination, source

This instruction logically ANDs the source with the destination and stores the result in the destination.
Source and destination have to be of the same size. Source: Register, Memory Location, Immediate Value
Destination: Register, Memory Location PF, SF, ZF affected; CF, OF (- - 0; AF becomes undefined. Eg:
AND BL, CL, BL BL AND CL

3) OR destination, source
This instruction logically Ors the source with the destination and stores the result in the destination. Source
and destination have to be of the same size. Source: Register, Memory. Location, Immediate Value.

Destination: Register, Memory Location

PF, SF, ZF affected; CF, OF 4-0; AF becomes undefined
Eg: OR BL, CL.; BL← BL OR CL destination.

4) XOR destination, source:

Source and destination have to be of the same size. Source: Register, Memory Location, Immediate Value
Destination: Register, Memory Location PF, SF, ZF affected; CF, OF. Eg: XOR SL, CL: BL BL XOR
CL

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-6
microprocessor_ CHAPTER 2 Instruction set of 8086

5) TEST destination, source

This instruction logically ANDs the source with the destination BUT the RESULT is NOT STORED
ANYWHERE. ONLY the FLAG bits are AFFECTED. Source: Register, Memory Location, Immediate
valu
Destination: Register, Memory Location PF, SF, ZF affected; CF, OF E 0; AF becomes undefined.
Eg: TEST BL, CL; BL AND CL; result not stored; Flags affected.
Note: Don't forget this instruction because it will be used later in multiprocessor systemsl

Shift Instructions
1) SAL/SHL destination, count
LEFT-Shifts the bits of destination. MSB shifted into the CARRY. LSB gets a.0
Bits are shifted 'count' number of times.
If count1, it is directly specified in the instruction.
If count > 1, it has to be given using CL Register.
Destination: Register, Memory Location.
for this Eg: SAL BL, 1; Left-Shift BL bits, once. Assume:before Operation: BL = 0011 0011 and
CF=1.

2) SHR destination, count

RIGHT-Shifts the bits of destination. MSB gets a 0 (. Sign is lost). LSB shifted into the CARRY
Bits are shifted 'count' number of times. If count is 1, it is directly specified in the instruction.
If count > 1, it has to be given using CL register. Eg: SHR BL, 1; Right-Shift BL bits, once. Assume:
Before Operation: BL = 0011 0011 and CF = 0
After Operation: BL = 00011 1001 and CF = 1
010101111101011

3) SAR destination, count

RIGHT-Shifts the bits of destination. MSB placed in MSB itself Sign is preserved). LSB shifted into
the CARRY.
Bits are shifted 'count' number of times. If count is 1, it is directly specified in the instruction.
If count > 1 it has to be given using CL register. Destination: Register, Memory Location
Eg: SAR BL, 1; Right-Shift BL bits, once.
Assume: Before Operation: BL = 0011 0011 and CF = 0
After Operation: BL = 0001 1001 and CF = 1.
Rotate Instructions

1) ROL destination, count

LEFT-Shifts the bits of destination.
MSB shifted into the CARRY.
MSB also goes to LSB. Bits are shifted 'count' number of times.
If count > 1, it has to be loaded in the CL register, and CL gives the count in the instruction.
If count = 1, it is directly specified in the instruction.
Destination: Register, Memory Location
Eg: ROL BL, 1; Left-Shift BL bits once.
More examples: MOV CL, 05H ; Load number of shifts in CL register.
ROL BL, CL ; Left-Shift BL bits CL (5) number of times.

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-7
microprocessor_ CHAPTER 2 Instruction set of 8086

2) ROR destination, count

RIGHT-Shifts the bits of destination. LSB shifted into the CARRY. LSB also goes to MSB. Bits are
shifted 'count' number of times. If count = 1, it is directly specified in the instruction. If count >
1, it has to be loaded in the CL register, and CL gives the count in the instruction. Eg: ROR BL, 1

3) RCL destination, count

LEFT-Shifts the bits of destination. MSB shifted into the Carry Flag (CF). CF goes to LSB. Bits are
shifted 'count' number of times. If count = 1, it is directly specified in the instruction. If count >
1, it has to be loaded in the CL register, and CL is specified as the count in the instruction.
Destination: Register, Memory Location
Eg: RCL BL,

4) RCR destination, count

RIGHT-Shifts the bits of destination. LSB shifted into the CF. CF goes to msg bites shifted
'count' number of times. If count = 1, it is directly specified in the instruction. If count > 1, it has
to be loaded in the CL register, and CL is specified as the count in t t instruction.
Destination: Register, Memory Location Eg: RCR BL, 1
More examples: MOV CL, O5H ; Load number of shifts in CL register.
RCR BL, CL ;Right-Shift BL bits CL (5) number of times.

Program Execution and transfer Instructions These instructions cause a branch in the program sequence
There are 2 main types of branching:
i. Near branch ii. Far Branch,
This is an Intra-Segment Branch i.e. the branch is to a new location within the current segment
i. Near Branch only.
Thus, only the value of IP needs to be changed. If the Near Branch is in the range of -128 to 127, then it
is called as a Short Branch.
ii. Far Branch
This is an Inter-Segment Branch i.e. the branch is to a new location in a different segment. Thus, the
values of CS and IP need to be changed.
JMP (Unconditional Jump) INTRA-Segment (NEAR) JUMP The Jump address is specified in two ways:
1) INTRA-Segment Direct Jump The new Branch location is specified directly in the instruction. The new
address is calculated by adding the 8 or16-bit displacement to the IP. The CS does not change. A +ve
displacement means that the Jump is ahead (forward) in the program. A-ve displacement means that the
Jump is behind (backward) in the program. It is also called as Relative Jump. Eg: JMP Prey; IP offset
address of "Prev". JMP Next; IP ← offset
address of "Next".
2) INTRA-Segment Indirect Jump The New Branch address is specified indirectly through a register or a
memory location (in DS only). The value in the IP is replaced with the new value. The CS does not change.

IE IMP WORD PTR (BX); IP - (DS[BX], DS: (x+1)

3)INTER-Segment (FAR) JUMP The Jump address is specified in two ways: 3) INTER Segment
Direct Jump The new Branch location is specified directly in the instruction Both CS and IP get
new values, as this is an inter-segment jump. Eg: Assume NextSeg is a label pointing to an instruction in
a different segment. JMP NextSeg: CS and IP get the value from the label NextSeg

4) INTER-Segment Indirect Jump & The new Branch location is specified indirectly through a register or

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-8
microprocessor_ CHAPTER 2 Instruction set of 8086

a location. memory Both CS and IP get new values, as this is an inter segment jump.
Eg:JMP DWORD PTR [BX]; IP (DS[BX], DS:[BX+1])
;CS (DS[BX+2], DS[BX+3]}
Eg: CALL subAdd SS[SP-1], SS[SP-2]) ←IP, SP (SP-2, IP← new Offset Address
of subAdd
INTER-Segment (FAR) CALL
The new subroutine called is in another segment (hence inter-segment). Here CS and IP both get new
values. The CALL address can be specified directly OR through Registers or Memory Location The
following sequence is executed for a Far CALL: [Link] CS into the Stack. ii. Decrement SP by 2. iii.
PUSH IP into the Stack. iv. Decrement SP by 2. v. Load CS with new
segment address. vi. Load IP with new offset address. vii, Control transferred to a subroutine
in the new segment. Eg: CALL subAdd; (SS:[SP-1J, SS:(SP-23) F CS, SP F SP-2, (SS:[SP-1], SSISP-
2D E-CS, SP F SP subAdd. -2,; CS (-New Segment Address of subAdd, IP F New Offset Address of
There is NO PROVISION for Conditional CALL.
RET Return instruction RET instruction causes the control to return to the main program from the
subroutine.

- Intrasegment-RET Eg: RET

RET n ;IP←SS:[SP], SS:(SP+1)
: SP ←SP+2
: IP←SS:[SP], SS:[SP+1];
: :SP← SP + 2 + n

Intersegment-RET Eg: RET

RET n : IP ←SS:[SP], SS:[SP+I.]
: CS ←SS / [SP + 2] ,SS:[SP+3]
: SP←SP+4
: IP ←SS:[SP], SS:[SP+1]
: SP← SP + 4 + n

Iteration Control Instructions

These instructions cause a series of instructions to be executed repeatedly. for number of iterations is
loaded in CX register. If CX is decremented by 1, after every iteration. Iterations occur until The maximum
difference between the address of the instruction and the CX = 0 address of the Jump can be 127.

4) LOOP Label
jump to specified label if CX not equal to 0; and decrement CX
Eg:
MOV CX, 40H
BACK: MOV AL, BL
ADD AL, BL
MOV BL, AL
LOOP BACK ; Do CX CX-1.
Go to BACK if CX not equal to 0.

LOOPE/LOOPZ Label (Loop on Equal / Loop on Zero)

Same as above except that looping occurs ONLY if Zero Flag is set (i.e. ZF = 1)

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-9
microprocessor_ CHAPTER 2 Instruction set of 8086

Eg:
MOV CX, 40H
BACK: MOV AL, BL
ADD AL, BL
MOV BL,AL
LOOPZ BACK : Do CX f-CX-1.
;Go to BACK if Do not equal to O and ZF =1

• LOOPNE/LOOPNZ Label (Loop on NOT Equal / Loop on NO Zero)

Same as above except that looping occurs ONLY if Zero Flag is reset (i. e ZF = 0)
Eg:
MOV CX, 40H
BACK: MOV AL, BL ADD AL, BL
MOV BL, AL
LOOPZ BACK ; Do CX CX-1.
; Go to BACK if CX not equal to 0 and ZF = 0.

Type 6) Processor Control Machine Control Instructions (these are instructions that directly operate on
Flag Reg)
For Carry Flag
1) STC
This instruction sets the Carry Flag. No Other Flags are affected.
2) CLC
This instruction clears the Carry Flag. No Other Flags are affected.
3) CMC
This instruction Complements the Carry Flag. No Other Flags are affected.
For Direction Flag
4) STD
This instruction sets the Direction Flag. No Other Flags are affected.
5) CLD
This instruction clears the Direction Flag. No Other Flags are affected.
For Interrupt Enable Flag
6) STI
This instruction sets the Interrupt Enable Flag. No Other Flags are affected.
7) CLI
This instruction clears the Interrupt Enable Flag. No Other Flags are affected.
7) External Hardware Synchronization Instructions.

1) ESC
This is an 8086 instruction-prefix used to indicate that the current instruction is for the 8087 NDP. We
write a homogeneous program for the two processors 8086 and 8087. Instructions are fetched by 8086 In
to its queue, 8087 duplicates the instruction queue of 8086 and monitors this queue. When an instruction
with ESC prefix (binary code 11011) is encountered, 8087 is activated, and hence it executes the
instruction, 8086 treats the instruction as NOP. ESC has to be written before each 8087 instruction,

2) WAIT
This instruction is used to synchronize 8086 with the 8087 Co-Processor via the TEST input pin of 8086.

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-10
microprocessor_ CHAPTER 2 Instruction set of 8086

Whenever 8087 is busy it puts a "1" on its BUSY o/p line connected to the TEST i/p of
the
The WAIT instruction makes the up check the TEST pin. If the up checks the TEST pin and finds a "1"
on it, 8086 understands that 8087 is busy and so it enters wait state. Here it does no processing. It can
come out of this idle state in 2 ways:
1. TEST input is made low l.e. 8087 is no longer busy. This takes 8086 completely out of the IDLE
state.
ii. Valid Interrupt on INTR or NMI In this case 8086 exits wait state, executes the ISR for the interrupt,
and then re-enters th4 WAIT state. (This is because the address of the WAIT instruction is what was
pushed into the stack before executing the ISR.)
Thus if we write a WAIT instruction before every 8087 instruction, we can ensure that 8087 i ready for
executing its own instruction whenever it arrives. WAIT can also be written before an 8086 instruction
that requires the result of a previous 8087 operation.

3) LOCK
This is an 8086 instruction prefix. It prevents any external bus master from taking control of the system
bus during executor of the instruction, which has a LOCK prefix. It causes 8086 to activate the LOCK
signal so that no other bus master takes control of the system bus.
4) NOP
There is no operation performed while executing this instruction. 8086 requires 3 T-States for this
instruction. It is mainly used to insert time delays, and can also be used while debugging.
5) HLT
This instruction causes 8086 to stop fetching any more instructions. 8086 enters Halt state. 8086 can come
out of this halt state only if there is a valid hardware interrupt (NMI or INTR) or by reset.
8) Interrupt Control Instructions
1) INT Type
This can be a number between 0...255 This instruction causes an interrupt of the given type.
The following action takes place:
i. PUSH Flag Register onto the Stack. SP decremented by 2.
ii. IF and TF are cleared. No other flags are affected.
iii. PUSH CS onto the Stack. SP decremented by 2
iv. PUSH IP onto the Stack. SP decremented by 2. In all SP decremented by 6.
v. New value of IP taken from location type x 4.
Eg: INT 1
;IP← ([00004] and [00005]) (as1x4=00004H)
vi. New value of CS taken from location (type x4)+2
Eg: INT 1
CS← (100006] and [00007])
Execution of ISR begins from the address formed by new values of CS and IP.
2) INTO (Interrupt on Overflow)
This instruction causes an interrput of type 4. Only it overflow flag (OF) is set . The above
sequence is followed and the control is transferaed to the location pointed by 0001011
Eg: INTO ;If OF = 1 then execute INT 4 please note this is INTO ( 0 for Overflow ) and NOT INT
0 (i.e. Type 0==> Zero Divide Interrupt).

3) IRET (Return from ISR)

This instruction causes the 8086 to return to the main program from an ISR.
This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-11
microprocessor_ CHAPTER 2 Instruction set of 8086

The following action takes place:

I) POP IP from the Stack.
SP incremented by 2.
ii, POP CS from the Stack.
SP incremented by 2.
iii. POP Flag Register from the Stack.
SP incremented by 2.
In all SP incremented by 6.
Execution of the Main Program continues from the address formed values of cs and IP restored from the
stack.

String Instructions of 8086

A String is a series of bytes stored sequentially in the memory. String Instructions operate on such
"Strings". The Source String is at a location pointed by St in the Data Segment. The Destination String is
at a location pointed by DI in the Extra Segment. The Count for String operations is always given by CX.
Since CX is a 16-bit register we can transfer max 64 KB using a string instruction. Si and/or DI are
incremented/decremented after each operation depending upon the direction flag "DF" in the flag register.
If DF = 0, it is auto increment. This is done by CLD instruction. If DF = 1, it is auto decrement. This is
done by STD instruction.

1) MOVS: MOVSB/MOVSW (Move String)

It is used to transfer a word/byte from data segment to extra segment. The offset of the source in data
segment is in SI. The offset of the destination in extra segment is in DI. SI and DI are incremented /
decremented depending upon the direction Flag
Eg: MOVSB; ES: [DI] ← DS:[SI] ... byte transfer
; SI←SI±1... depending upon DF;
;DI ←DI ±1... depending upon DF

2) LODS: LODSB/LODSW (Load String)

It is used to Load AL (of AX) register with a byte (or word) from data segment. The offset of the source
in data segment is in SI. SI is incremented / decremented depending upon the
direction flag (DF). Eg: LODSB; AL← DS:[SI]... byte transfer
SI←SI ± 1... depending upon DF
LODSW; AL←DS: [SI]; AH←DS:[SI + 1]; S←IS. ± 2

3) STOS: STOSB/STOSW (Store String)

It is used to Store Al (or AX) into a byte (or word) in the extra segment. The offset of the
source in extra segment is in DI. DI is incremented/decremented depending upon the direction
flag (DF).
Eg: STOSB; ES:[DI]← Al... byte transfer
DI←DI 11... depending upon DF
STOSW: ES: [DI]← AL; ES:[DI+1] AH... word transfer
DI ←DI±2... depending upon DF

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-12
microprocessor_ CHAPTER 2 Instruction set of 8086

4) CMPS: CPMSB/CMPSW (Compare String)

It is used to compare a byte (or word) in the data segment with a byte (or word) in the extra segment. The
offset of the byte (or word) in data segment is in St. The offset of the byte (or word) in extra segment is
in DI. SI and DI are incremented/ decremented depending upon the direction flag. Comparison is done by
subtracting the byte (or word) from extra segment from the byte (or word) from Data segment. The Flag
bits are affected, but the result is not anywhere.
Eg:CMPSB; Compare DS:[SI] with ES:[DI]... byte operation;
SI←SI ±1... depending upon DF;
DI ←DI ± 1 depending upon DF
CMPSW; Compare (DS:[SI]. DS[SI+1])-; with (ES:[DI ] ES:[DI+1]):
SI ←SI ±2... depending upon DF;
DI← DI ± 2... depending upon DF

5) SCAS: SCASB/SCASW (Scan String) It is used to compare the contents of AL (or AX) with a byte (or
word) in the extra segment. The offset of the byte (or word) in extra segment is in DI. DI is incremented
/ decremented depending upon the direction flag (DF). Comparison is done by subtracting a byte (or word)
from extra segment from AL (or AX).
The Flag bits are affected, but the result is not stored anywhere.
Eg: SCASB; Compare AL with ES:[DI] ... byte operation
DI ←DI ± 1... depending upon OF
SCASW; Compare (AX) with (ES:[DI], ES: [DI+1]} DI ←DI ± 1... depending on DF
REP (Repeat prefix used for string instructions)
This is instruction prefix, which can be used in string instructions.
It used with string instructions only. I
It causes the instruction to be repeated CX number of times.
After each execution, the St and DI registers are incremented/decremented based on the DF (Direction
Flag) in the Flag register and CX is decremented. i.e. DF = 1; SI, DI decrements. Thus, it is important that
before we use the REP instruction prefix the following steps must be came out: CX must be initialized to
the Count value. If auto decrementing is required, DF must be set using STD instruction else cleared using
CLD instruction.
- EG: MOV CX, 0023H
CLD
REP MOVSB
The above section of a program will cause the following string operation ES: [DI] ← DS:[SI], SI←
SI+1, DI ←DI + 1, CX CX-1 to be executed 23H times (as CX = 23H) in auto incrementing mode (as DF
is cleared).

6) REPZ/REPE (Repeat on Zero/Equal)

It is a conditional repeat instruction prefix. It behaves the same as a REP instruction provided the-Zero
Flag is set (i.e. ZF = 1 ), It is used with CMPS instruction.

7) REPNZ/REPNE (Repeat on No Zero/Not Equal)

- It is a conditional repeat instruction prefix. It behaves the same as a REP instruction provided the Zero
Flag is reset (i.e. ZF = 0 ) It is used with SCAS instruction.

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-13
microprocessor_ CHAPTER 2 Instruction set of 8086

Assembler directives of 8086:-

Assembly language has 2 types of statements:
1. Executable: Instructions that are translated into Machine Code by the assembler.
2. Assembler Directives: Statements that direct the assembler to do some special task. No M/C
language code is produced for these statements. Their main task is to inform the assembler about the start/end of a
segment, procedure or program, to reserve appropriate space for data storage etc. Some of the assembler
directives are listed below
1. DB (Define Byte); Used to define a Byte type variable.; Assembler reserves 1 Byte of memory for the variable;
named SUM and initialize it to 0.
Eg: SUM DB 0
2. DW (Define Word); Used to define a Word type variable (2 Bytes).
3. DD (Double Word); Used to define a Double Word type variable (4 Bytes).
4. DQ (Quad Word); Used to define a Quad Word type variable (8 Bytes).
5. DT (Ten Bytes); Used to define 10 Bytes to a variable (10 Bytes).
6. DUP(); Copies the contents of the bracket followed by this keyword into the memory location
specified before it. Stores LIST as a series of 10 bytes initialized to Zero.
Eg: LIST DB 10 DUP (0)
7. SEGMENT; Used to indicate the beginning of a segment.
8. ENDS; Used to indicate the end of a SEGMENT.
9. ASSUME E g: Assume CS: Code; Associates a logical segment with a processor segment.; Makes
the segment "Code" the actual Code Segment.;
[Link]; Used to indicate the beginning of a procedure.
[Link]; Used to indicate the end of a procedure.
[Link] ; Used to indicate the end of a program.

This document is property of RKDEMY and cannot be used, disclosed or duplicated without the prior written consent of RKDEMY pg. 1-14
MICROPROCESSOR CHAPTER : 3 8259 PIC

Chapter-3. 8259 PIC

ARCHITECTURE OF 8259:-

1) PIC 8259 is a programmable interrupt controller.

2) A single 8259 can provide 8 interrupts and 8259 in cascaded configuration with 1 Master
and 8 Slaves can provide up to 64 interrupts
3) It is necessary to initialize the 8259 with the help of ICW'S to decide several properties such as
vector numbers, priority, masking, triggering etc.
4) In a cascaded configuration, each 8259 has to be individually initialized, master
as well as each slave.
5) The architecture of 8259 mainly consists of the following:-

i. Interrupt Request Register (IRR):-

An IRR is a 8-bit register, one bit is reserved for each interrupt lines and in 8259 there are
8 interrupt lines named as IRo to IR7.
Whenever an interrupt request occurs on any of these lines, the corresponding bit is set in the
IRR.

ii. In-Service Register (InSR):-

An InSR is a 8-bit register which is used to store the level of the interrupt request which is
currently being serviced.

iii. Interrupt Mask Register (IMR):-

An IMR is a 8-bit register which is used to store the masking pattern for the interrupts, it
stores one bit per interrup level.
MICROPROCESSOR CHAPTER : 3 8259 PIC

iv. Priority Resolver :-

Priority resolver is that component which examines the IRR, InSR and IMR and decides the
interrupt of the highest priority and that interrupt is sent by 8259 on the INTR line of the

v. Control Logic :-
Control Logic unit consists of INT and INTA lines.
INT line of 8259 is used to interrupt the microprocessor on the INTR line of the
Microprocessor.
The microprocessor sends the response of the interrupt request made by 8259 on the INTA
line of the 8259.
It is also used to control the remaining blocks of 8259.

vi. Data Bus Buffer :-

it is the bi-directional buffer which is used to interface the 8 bit data bus of 8259 with the
external System bus.

vii. Read/Write Logic :-

It is used to accept the RD, WR, Ao and CS signal It also holds the ICWS and OCWS.

viii. Cascade Buffer/Comparator :-

Cascade Buffer is available only in cascaded configuration
Cascade Buffer mainly consists of two parts and they are as follows:-

1. CASO, CAS1, CAS2 Lines :-

In 8259, there are 8 interrupt levels therefore 3 lines are enough, since 2³=8.
These lines are used as output lines by the Master to send the slave identification number.
These lines are used as input by the Slaves to receive the Slave Identification number as input.

2. SP/EN:-
In Buffered mode, EN line is used to enable the buffer.
In remaining mode, SP line is available and SP line for master =1 and for slave SP line =0.

Interfacing and Working of a Single 82591-

A single 8259 can accept 8 interrupts.

Whenever 8259 is interrupt by a device in return it will interrupt the microprocessor on
the INTR line.
First there is a need to enable the INTR signal using the STI instruction (i.e. making IF=1).
It is compulsory to initialize the 8259 with ICWS, ICW1 and ICW2 are compulsory while ICW4
is optional.
When one or more interrupts occur on the IR lines of 8259, the following sequence of the events
takes place:-

1. The bits are set in the IRR for those IR lines on which the interrupts occur.
2. The priority resolver checks IRR, InSR and IMR and determines the interrupt of highest priority and
interrupts the microprocessor on the INTR line.
MICROPROCESSOR CHAPTER : 3 8259 PIC

3. On the receiving the interrupt on the INTR line, the microprocessor finishes the current
instruction and acknowledges the interrupt by sending first pulse of INTA on the INTA pin of
the 8259.
4. On receiving the first INTA signal from the microprocessor, 8259 sets the corresponding bit
in the InSR and the bit in the IRR is reset and 8259 now prepares to send the vector number
N to the microprocessor.
5. Now the microprocessor sends the second INTA pulse on the INTA pin of the 8259.
6. On receiving the second INTA pulse 8259 sends the Vector Number one byte to the
microprocessor
7. Now the microprocessor multiplies N*4, to get the values of CS and IP from the IVT.
8. The microprocessor pushes the contents of flag register, CS, IP In to the stack, clears IF and
TF and transfers program to the address of the ISR and the ISR thus begins.
MICROPROCESSOR CHAPTER : 3 8259 PIC

Interfacing and Working of Cascaded 8259:

In cascaded configuration there are more than one 8259's connected to the microprocessor.
A cascaded configuration increases the number of interrupts handled by the system.
A cascaded configuration increases the number of interrupts handled by the system.
In cascaded configuration, the maximum number interrupts handled by the sated are 64. In cascaded
there is 1 master 8259 an interrupts and master 8259's SP/EN is connected to vcc(i.e. SP/EN=+5v) and
slave 821398 8259's and master De SP/EN=0). Each slave's INT pin is connected to the
IR lines connected to the INTR line of the microprocessor.
It is necessary or compulsory to initialize each 8259's (master as well as slaves) individually with ICWS.
First the INTR signal of the microprocessor is enabled using the STI instruction.
And in cascaded configuration, the master addresses the individual slaves through the CAS2, CAS1,
CASo lines connected from the master to each of the slaves.
When an interrupt occurs on the IR lines of slaves, the following events takes place

1. The slave 8259 will resolve the priority of the interrupts and will send the interrupt of highest priority
priority to the master 8259 on the IR line.
2. Now, the master 8259 will resolve the priorities among it slaves and will send the interrupt of highest
3. On receiving the interrupt request, the microprocessor will finish the execution of its current
instruction and will send the first INTA pulse to the 8259 on the INTA pin.
4. On receiving the first INTA pulse, the master 8259 will send a 3-bit slave identification
number on its CAS lines and it will also set the corresponding bit in its InSR and the
slave 8259 will identify its number on the CAS lines and will set the corresponding bit bit in its
InSR and will also start calculating or preparing the vector number N.
5. On receiving the second pulse of INTA signal, the slave 8259 will place the vector number N
on the data bus.
6. Now the microprocessor will push the flag register on the stack along with CS and IP registers
and then it will perform N*4 and fetch the ISR address from the IVT and now now the
microprocessor will load the ISR address in to CS and IP registers and thus then the ISR
begins.
MICROPROCESSOR CHAPTER : 3 8259 PIC
MICROPROCESSOR CHAPTER : 4 8255 PPI

Chapter-4. 8255 PPI

Architecture of 8255:-

8255 is a programmable general purpose I/O device

8255 has 3 8-bit bi-directional I/O ports viz.. Port A, Port B, Port C.
8255 provides 3 modes of data transfer and they are as follows:
a) Simple I/O mode.
b) Handshake I/O mode.
c) Bi-directional Handshake I/O mode.
And 8255 also provides a Bit Set-Reset mode which is applicable only on Port C.

The architecture of 8255 can be divided in to following parts:-

1) Data Bus Buffer :-

It is a 8-bit bi-directional buffer which is used to interface the internal bus of 8255 with the
external data bus (i.e. with the data bus of the microprocessor).
The microprocessor transfers data to and from 8255 through this buffer.

2) Read/Write Logic :-
MICROPROCESSOR CHAPTER : 4 8255 PPI

This unit is used to accept address and control signals from the microprocessor.
A_{1} and A_{0}lines of 8255 are connected with A_{2} and A_{1} of the microprocessor
and A_{1} and A_{0} lines of 8255 are used to select ports and control word register in

the following manner:-

the following manner:-

For 8255 For 8086 Selection

A1 Ao A2 A1
0 0 0 0 Port A
0 1 0 1 Port B
0 1 1 0 Port C
1 1 1 1 Control Word

3) Group A Control :-
The architecture of 8255 is divided in to two groups namely Group A and Group B.
Group A consists of Port A and Port Cupper i.e. PC7-PC4- It accepts control signals from the
control word and forwards them to the respective ports.

4) Group B Control :-
The architecture of 8255 is divided in to two groups namely Group A and Group B.
Group B consists of Port B and Port Clower i.e. PC3-PC0.
It accepts control signals from the control word and forwards them to the respective ports.

5) Port A, Port B, Port C :-

Port A and Port B can be used as 8-bit bi-directional ports
Port C can be used as two 4-bit bi-directional ports.
Bit Set-Reset mode is only applicable to Port C.
These ports can be programmed to work in various modes and they are as

follows:-

Control Word of 8255-1/0 mode:-

To perform data transfer activities using these ports through 8255, 8255 need to be in I/O mode.
The bit pattern for the control word in the I/O mode is as follows:-
MICROPROCESSOR CHAPTER : 4 8255 PPI

Control Word of 8255-1/0 mode:-

To perform data transfer activities using these ports through 8255, 8255 need to be in I/O mode.
The bit pattern for the control word in the I/O mode is as follow

Control Word of 8255-BSR mode:-

BSR mode stands for Bit Set-Reset mode and this mode is only applicable for Port C.
In this mode the bits of Port C can be individually set or Reset due to which we get 8 individually
controllable lines which can be used while interfacing with devices like A to D converter or a
7-segment display.
The bit pattern for the control word in the BSR mode is as follows:-
MICROPROCESSOR CHAPTER : 4 8255 PPI

Data Transfer Modes of 8255:-

For performing data transfer activities 8255 needs to be in I/O mode.
Data transfer can be done through 8255 in following modes:-
1) Mode0- Simple Bi-directional I/O mode.
2) Mode1-Handshake I/O mode.
3) Mode2-Bi-directional Handshake I/O mode.

Mode0- Simple Bi-directional I/O mode:-

In Mode0, Port A and Port B can be used as 8 bit bi-directional ports to perform data transfer activities
through 8255 while Port C can be as two 4 bit bi-directional ports and these ports can be programmed
Individually to work as input or output ports.
But in Mode0, no handshake signals are available due to which ports in this mode don't have
interrupting capability, therefore slower peripheral devices cannot be interfaced.

Mode1- Handshake I/O mode

In Mode1, Port A and Port B can be used two 8-bit bi-directional ports which can be programmed
individually to work as an input or output port.
Port A and Port B uses 3 lines each of Port C to operate in Mode1 (i.e. for handshake signals)
due to which Port C cannot operate in Mode1.
In Mode1, the handshake signals are exchanged between the devices before the data transfer takes
place.
Slower peripheral devices can be interfaced in Mode1 due to its interrupting capability.
The handshake signals are different for input and output modes.

Mode1 Input Handshaking:-

MICROPROCESSOR CHAPTER : 4 8255 PPI

The input handshaking takes place in the following manner:-

STB (Strobe), IBF (Input Buffer Full) are signals used for input handshaking and INTR
signal is used to interrupt the 8086 microprocessor.

1) The peripheral devices places the data on the port bus and informs the 8255 by making STB low.
2) The input port accepts the data and makes IBF high, indicating the peripheral device that its port is
full, so that the peripheral devices should not send more data and should wait until the port is empty
thereby preventing loss of data.
3) And 8255 interrupts the microprocessor through the INTR line provided that the INTE flip-flop is
Set.
4) On receiving the interrupt, the microprocessor will issue the RD signal and will read the data and
in the above way the data byte is transferred to the microprocessor.
5) After the data byte is transferred I to the microprocessor, 8255 makes the IBF low thereby
indicating the peripheral device that it can send more data in the above sequence.

Mode1- Output Handshaking :-

MICROPROCESSOR CHAPTER : 4 8255 PPI

The output handshaking takes place in the following manner:-

OBF (Output Buffer Full) and ACK (Acknowledgement) are used as handshake signals
and INTR is used to interrupt the microprocessor.

1) The output port is empty that is indicated by a high on the INTR line, then the
microprocessor writes data on the output port by giving the WR signal.

2) As soon as the WR operation is complete, the 8255 makes the INTR low, indicating the
microprocessor should wait and this prevents the microprocessor from sending more more data
to 8255 thereby preventing the loss of data.
3) Now, 8255 also makes the OBF low to indicate the peripheral device that the data is available on
the data bus and then the peripheral device performs the read operation (i.e. accepts the data from
the data bus) and acknowledges 8255 by making ACK low
4) In this way the microprocessor transfers the byte of data to the peripheral device through 8255.
5) Now, OBF and ACK lines go high.
6) The INTR line also goes high and thereby indicating the microprocessor that an another byte
can be sent i.e. the output port is empty.
This process is repeated for further bytes.
MICROPROCESSOR CHAPTER : 4 8255 PPI

Mode2- Bi-directional Handshake 1/0 :-

In mode2, there are five lines of Port C are used by Port A to perform bi-directional handshake I/O.
Only Port A can operate in bi-directional handshake I/O.
Port B can either operate in Mode0 or Mode1.
If Port B is operating is in Mode1, then it will use 3 line of Port C, then entire lines of Port C will be
used for handshake signals.
OR
If Port B is operating in Mode0, then remaining 3 lines of Port C can be used in simple
1/0 mode. In Mode2, five handshake signals are used and they are viz... STB, IBF, OBF, ACK and
INTR.
The handshaking process is similar to the Mode1
MICROPROCESSOR CHAPTER : 5 8253 PIT

Chapter-5. 8253PIT

Architecture of 8253:-

Pin Diagram of 8253:-

Block Diagram of 8253:-

MICROPROCESSOR CHAPTER : 5 8253 PIT

The architecture of 8253 consists of following things:-

1) Data Bus Buffer :-
It is a 8 bit bi-directional buffer.
This buffer is used to interface the internal bus of 8253 with the external bus
(i.e. with the data bus of the microprocessor).
2) Read/Write Logic Unit :-
This unit is used to accept the RD and WR signals.
Its A, and Ag are connected to A₂ and A, of the microprocessor respectively. The A₁ and Ag
lines are used to select the counters and the control word in the
following manner :-

3) Control word Register :-

Read Operations :-
This buffer is used to interface the internal bus of 8253 with the external bus
(i.e. with the data bus of the microprocessor).
MICROPROCESSOR CHAPTER : 5 8253 PIT

2) Read/Write Logic Unit :-

This unit is used to accept the overline RD and overline WR signals.
Its A_{1} and A_{0} are connected to A_{2} and A_{1} of the microprocessor respectively.
The A_{1} and A_{0} lines are used to select counters and the control ward in the

following manner:

3) Control word Register :-

Read Operations :-
There are 2 ways in which the microprocessor can read the count and they are as follows:-

Ordinary Read :-
In this method, the next count value is read and the current counting process is stopped by controlling
the gate input of a selected counter.

Read on Fly :
In this method, the microprocessor reads the next count value without stoping the current counting
process and this method is termed as Read on Fly.
MICROPROCESSOR CHAPTER : 5 8253 PIT

4) 3 Independent Counters :-
In 8253, there are 3 16-bit down counters.
Each counter can operate in one of the available six modes.
Each counter can have a BCD or Binary count depending on the type of count.
Each counter mainly has 3 signals and they are viz... CLK , GATE and OUT.
The input clock is applied on the CLK.
Counting is controlled through the GATE input.
The Out pin is used to trigger the microprocessor.

Timer Modes Of 8253:-

There are six possible modes in which 8253 can operate and they are explained below:-

1) Mode0-Interrupt on Terminal Count:-

In this mode, out pin is initially low and when the count value is loaded the gate input is made
to enable the counting.
During counting the out pin remains low but on the terminal count the out pin goes high and
remains high and this can be used to trigger the microprocessor.
Effect of GATE:-
Low-Disables Counting, High- Enables (Resumes) Counting

2) Mode1-Monostable Multivibrator:-
In this mode, the out pin is initially high and then the count value is loaded and to enable the
counting process a rising edge is applied on the gate input The out pin goes low as soon as
counting process starts and remains low during the counting process but on terminal count the out
pin goes high and remains high.
Effect of GATE:- Low- No Effect, High-Starts Counting, can also re-trigger it.

3) Mode2-Rate Generator:-
In this mode, the out pin is initially high and then the count value is loaded and to enable the counting
process the gate pin is made high.
During the counting process the out pin remains high but it goes low for one clock cycle just before
the terminal count and the initial count value is reloaded and the above process repeats.
Therefore this mode produces a continuous pulse.
Effect of GATE:-
Low- Disables Counting, High-Enables (Restarts) Counting.

5) Mode4-Software Triggered Strobe:-

In this mode, the out pin is initially high and then the count value is loaded and to enable the
counting process the gate pin is made high.
During the counting process out pin remains high but just after terminal count for one clock cycle
, the out pin goes low and after that it goes high and remains high.
Effect of GATE:-
Low- Disables Counting, High- Enables (Restarts)Counting
MICROPROCESSOR CHAPTER : 5 8253 PIT

6) Mode5-Hardware Triggered Strobe:-

In this mode, the out pin is initially high and then the count value is loaded and for
enabling the counting process a trigger is applied on the gate input and for counting
to continue there is no need of gate pin to remain high.
During counting, the out pin remains high but just after the terminal count it goes low
For one clock cycle.
Effect
of GATE:- Low- No Effect, High- Starts counting, it.
MICROPROCESSOR CHAPTER : 6 8237 DMAC

Chapter-6. 8237 DMAC

The Pin Configuration of 8237 are explained as follows:

1. DREQ3-DREQO(Data request)
These input pins are used by the I/O device to request the DMAC for DMA Transfer.
These pins can be active high/active low through program.
By default they are active high.
There are 4 DREQ pins as there are 4 channels.
At a time only one channel can perform DMA transfer.
Thus, for multiple requests, priorities are fixed.
DREQO has the highest priority while DREQ3 has the lowest priority.

2. DACK3-DACKO(Data Acknowledge)
These input pins are used by the DMAC to inform the I/O device that it has acquired the
System.
bus, and hence the DMA transfer can begin.
These pins can be made active high/active low through program.
By default they are active low.
There are 4 DACK pins as there are 4 channels.
MICROPROCESSOR CHAPTER : 6 8237 DMAC

3. HRO(Hold Request)
This output pin is used by the DMAC to request microprocessor to release the system bus.
It is connected to HOLD pin of microprocessor.

[Link](Hold Acknowledge)
This input pin is used by the microprocessor to inform the DMAC that it as released to system bus.
It is connected to the HLDA pin of microprocessor.
5.(Address Enable)
This is an output pin from the DMAC.
this pin is high, it disconnects the microprocessor from the system bus.
It is also used to enable the external latch.

6. ADSTB(Address Strobe)
It is an output signal.
It is used to strobe the higher order address byte into the latch.

7.DB7-DB0(Data Bus)
These are 8 bi-directional data lines used to connect the the internal data bus of 8237 with th
external data bus.
In idle cycle microprocessor writes or reads from 8237 using this bus. carries the 8 higher order bits
of the 16 bit address. In active cycle tis bus
During memory to memory transfer this us carries the data byte to be transferred

8.A7-A4(Address bits)
These are 4 output address lines.
In active cycle these lines carry A7-A4 bits of the address at which the transfer is to be done.
As this address is generated by the 8237 these are output lines.

9.A3-A0(Address bits)
These are 4 bi-directional address lines.
In idle cycle microprocessor sends the address A3-AO, to select one of its registers.
Since microprocessor sends the address to 8237 these are input lines.
In active cycle these lines carry A7-A4 bits of the address at which the transfer is to be done.
As this address is generated by the 8237 these are output lines.

[Link], IOW
These are bi-directional control lines.
During idle state the microprocessor issues these signals to read from or write into the 8237 During
active state the DMAC issues these signals to read from or write into an I/O device.

11. MEMR, MEMW

These are output control lines.
During active state the DMAC issues these signals to read from or write into the memory.

[Link]
This is a bi-directional signal indicating the end of DMA process
MICROPROCESSOR CHAPTER : 6 8237 DMAC

During active cycle after each byte is transferred through DMA the count register decrements
by 1.
When the terminal count is reached it means that all the require bytes are transferred.
At this point the DMAC issues this signal and the DMA operation is terminated.
Hence it is an output signal..
During the course of the transfer the DMA operation can be explicitly terminated by giving this signal
externally to the DMAC.
Hence it is also as input signal.

13. CLK
This is a clock input signal for the DMAC It is usually connected to the system clock,

14. RESET
This is reset input signal for DMAC
This signal clears the internal registers of the DMAC and causes it to enter Idle state.

15. READY
This is input signal to the DMAC It is used to synchronize the DMAC with slower peripherals If a
peripheral is slow it put a low on this line causing the DMAC to wait. Only after the DMAC finds a
high on pin it executes the DMA operation.

Architecture of 8237

The Internal Registers (Architecture) of 8237 are explained as follows:

1. BAR(Base Address Register)

It is a 16 bit register.
Each channel has one BAR.
MICROPROCESSOR CHAPTER : 6 8237 DMAC

During idle cycle microprocessor writes the starting address of the data transfer into the BAR.
Thereafter the contents of BAR do not change throughout the transfer.

2. BWCR(Base Word Count Register

It is a 16-bit register. Each channel has one BWCR. During Idle cycle microprocessor writes the
number of bytes to be transferred into the BWCR. Eg: if 5 bytes are to be transferred the
microprocessor writes 0004H into the BWCR Thereafter the contents of BWCR do not change
throughput the transfer.

3. CAR(Control address register)

It is a 16 bit register. Each channel has one CAR. It is used to hold the current address for the DMA
transfer. After each byte is transferred, the CAR is automatically incremented/decremented. The
microprocessor can read the contents of CAR.

[Link](Current word count register)

It is a 16 bit register. Each channel has one CAR. It is used to hold the current address for DMA
transfer. After each byte is transferred the CAR is automatically incremented/decremented
The microprocessor can read the contents of CAR.

[Link] Register
It is a 4-bit register having individual bits per channel. It is used to store the DMA request of the
peripheral device. The request bits can be set/reset as follows:

6. Temporary register
It is an 8 bit register.
It is used to store data temporarily during memory to memory transfer only.

7. Mask Register
It is a 4 bit register having individual bits per channel.
This register holds the masking information about the channels.
By changing these bits the channels can be masked/unmasked in the following two ways:
MICROPROCESSOR CHAPTER : 6 8237 DMAC

a. Single mask command

Using this command an, individual channel can be masked/unmasked.

This action would not effect the other channels.

b. ALL mask command

Using this command all channels can be silmultaneoulsy masked/unmasked.

This action would effect all channels together

8. Command register
It is a 8 bit register
It is used to store the command word.
The microprocessor writes the command word.
MICROPROCESSOR CHAPTER : 6 8237 DMAC

9. Mode Register
It is a 8 bit register.
Each channel has one mode register It is used to program the operational mode of that channel.
MICROPROCESSOR CHAPTER : 6 8237 DMAC

[Link] Register
It is a 8 bit register.
It stores the status word of the 8237.
The microprocessor can read the status register.
MICROPROCESSOR CHAPTER : 7 8036

Chapter-7. 8036

Features of 8036:-
1) In 80386, the size of address bus is 32 bits, therefore the maximum main memory can be
accessed is 232 =4GB.
2) In 80386, the size of the data bus is 32 bits and the size of ALU is also 32 bits, therefore
80386 microprocessor is known as 32 bit microprocessor and since the size of data bus is 32
bits the main memory is divided in to four banks, each bank's maximum size can be 1GB,
therefore A2.A31 address lines are used to access these banks and Ag and A₁ are used to
produces 4 bank signals viz... BE3 to BEO.
3) 80386 supports address pipelining.
4) 80386 supports virtual memory and the total virtual memory that can be accessed is
246=64TB.
5) 80386 supports protection mechanism, in protected model 4 privilege levels are used.
6) 80386 supports multitasking to give higher System performance.
7) 80386 has a 16 bit I/O address, therefore it can access total 216=65536 ports.
Now, DMAC is the bus master and after performing the bus operations, it will return back the
Control of the system bus to the microprocessor by making HOLD=0.

PEREQ(PERIPHERAL EXTENSION REQUEST):

This pin is used by the co-processor 80387.
The physical address calculation and protection mechanism is performed by the 80386co-processor and
not by the 80387 co-processor, so whenever 80387 needs to perform some data transfer operations using
the system bus,
it will make request the microprocessor to initialize the bus operation i.e. perform all
the physical address calculations and place the physical address on the address bus by making
PEREQ=1, although the data will be transferred to 80387.

ERROR:-
This pin is used by the co-processor 80387.
Whenever 80387 will encounter any errors it will make ERROR =0, thereby informing the
microprocessor about these errors.

BUSY :-
This pin is used by the co-processor 80387.
Whenever the co-processor is busy, it makes BUSY =0.
Whenever the microprocessor encounters the WAIT instruction, it will check the BUSY pin and if the
BUSY =0, indicating the co-processor is busy and will enter wait states until BUSY =1.
And if the BUSY =1, the microprocessor will or will continue.

Address Bus:-
80386 has a 32 bit address bus.
And A2-A31 address lines are used to access the main memory and address lines Ao-A₁ are used
to produce the bank signals.
MICROPROCESSOR CHAPTER : 7 8036

Data Bus:-
80386 has a 32 bit data bus.

BS16:-
80386 can operate with 16 bit data bus also.
So this makes the process easier and cheaper to upgrade from 8086 to 80386.
So if BS16 =0, then the 16-bit data bus is available for use.
And if BS16=1, then the 32-bit data bus is available for use.
M\10,D\C.W\R:-
These signals are used to perform control operations in the following manner:-

LOCK :-
Whenever there is a LOCK prefix written in the instruction, it indicates the
processor that it should not release the control of system bus just after the machine cycle instead it
should release the control of the system bus after the execution of the current instruction is completed.
So by making LOCK =0, it will inform the peripheral devices that it will not release the control of the
system until the execution of the current instruction is completed.

ADS:-
This signal is made low, when an address is placed on the address bus by the
microprocessor.
In a non-pipelined cycle, the ADS goes low during the T1 T-state of a cycle. machine
In a pipelined cycle the ADS goes low during T2 T-state cycle. of the previous machine
It is used to signal the external devices that the microprocessor has placed a new address on the
address bus.
NA:-
This signal is used to inform the microprocessor whether it should implement address pipelining or
not.
If NA =0, address pipelining will be implemented.
If NA =1, address pipelining will not be implemented.
MICROPROCESSOR CHAPTER : 7 8036

ARCHITECTURE OF 80386:-

The architecture of 80386 is divided in to following parts:-

1) Bus Unit:-
The data transfer to and from the microprocessor takes places using the bus unit and the bus unit is
connected to external memory and I/O devices and to fetch the data and the instruction it needs the
physical address and the physical address is calculated by memory management unit (MMU) and
passes this physical address to the bus unit.

2) Prefetch Unit:-
80386 supports pipelining, so this unit is used to prefetch the next instructions and store them in
to the prefetch queue.
In 80386, the maximum size of an instruction can be 15 bytes, therefore this unit fetches the next 16
bytes of the program and stores them in to the prefetch queue.
The prefetch unit gets refilled after every 4 bytes.
Whenever Execution unit and prefetch unit makes the request to the bus unit simultaneously then
higher priority will be given to the execution unit.

3) Decode Unit:-
This unit is used to decode (i.e. interpret) the instructions.
After decoding the instruction, the decoded instructions are stored in an instruction queue.
And in an instruction queue at a time, next 3 decoded instructions are stored.

4) Execution Unit:-
The main task of execution unit is to execute the instructions.
80386 has a 32-bit ALU, so this unit to perform operations on 32-bit operands in one cycle.
In 80386, the ALU has a dedicated multiplier and a divider, this makes its ALU more powerful.
MICROPROCESSOR CHAPTER : 7 8036

The architecture of 80386 is divided in to following parts:-

1) Bus Unit:-
The data transfer to and from the microprocessor takes places using the bus unit and the bus
unit is connected to external memory and I/O devices and to fetch the data and the instruction
it needs the physical address and the physical address is calculated by memory
management (MMU) and passes this physical address to the bus unit.

2) PreFetch Unit:-
80386 supports pipelining, 50 this unit is used instructions and store them in to the prefetch
queue. to prefetch the next
In 80386, the maximum size of an instruction can be 15 bytes, therefore this unit fetches the
next 16 bytes of the program and stores them in to the prefetch queue.
The prefetch unit gets refilled after every 4 bytes.
Whenever Execution unit and prefetch unit makes the request to the bus unit simultaneously
then higher priority will be given to the execution unit.

3) Decode Unit:-
This unit is used to decode (i.e. interpret) the instructions.
After decoding the instruction, the decoded instructions are stored in an instruction queue.
And in an instruction queue at a time, next 3 decoded instructions are stored.

4) Execution Unit:-
The main task of execution unit is to execute the instructions.
80386 has a 32-bit ALU, so this unit to perform operations on 32-bit operands in one cycle.
In 80386, the ALU has a dedicated multiplier and a divider, this makes its ALU more
powerful.
MICROPROCESSOR CHAPTER : 7 8036

5) Memory Unit:-
Memory Unit comprises of segment unit and page unit. This unit is used to convert the virtual
address in to 32 bit physical address.
Segmentation is compulsory and the virtual address is an input to segment unit and after
performing segmentation this virtual address is converted in to 32-bit linear address and
paging is optional if paging is not performed then this 32-bit linear address is treated as 32-bit
physical address. And if paging is performed then the 32-bit linear address is an input to page
unit and after performing paging the 32-bit linear address is converted in to 32-bit physical
address.
MICROPROCESSOR CHAPTER : 8 80386

Chapter-8. 80386
Flags of 80386:-

There are four new flags are added and remaining flags are same as of 8086 flags and new flags
are explained as follows:-

VM- Virtual 8086 Mode:-

80386 can operate in virtual 8086 mode to run the 8086 programs in the faster environment of the
80386 and this can be done by making VM=1.
And by making VM=0, the 80386 enters back in the protected mode.

RF- Resume Flag:-

Resume flag is used during debugging, a debug fault in the next instruction(l.e. resuming to the same
instruction instead to next instruction) can occur and by making RF=1, this fault can be ignored and this
flag automatically resets after the next instruction.

NT- Nested Task:-

This flag is used to indicate that the current program is nested l.e. it is invoked by another program and
after executing the current program it needs to return back to the program because of which it got
invoked. If NT=1, then the current task is nested and its TSS has a valid back link to the TSS of the
previous task.
This flag is automatically set whenever a Nested task is initiated and it can only be reset by the software.

1/O Privilege level:-

These bits are used to assign I/O privilege level.
80386 microprocessor has 4 level privilege levels, where privilege level=0 is the highest and the
privilege level=3 is the lowest.

Real Mode of 80386:-

In real mode, the 80386 microprocessor works as a fast 8086 machine and all registers are like in 8086
microprocessor even the maximum main memory that can be accessed is 1MB.
In this mode the physical address is calculated using following formula:-
PA-segment address*10H + offset address.
This mode is basically used to run the BIOS on reset.
Once the required registers are initialized, 80386 can enter in the protected mode by making PE bit=1 in
CRO.
Real mode consists of the following:-
There are six 16-bit segment register are available and they are viz...
CS,SS,DS,ES,FS,GS.
MICROPROCESSOR CHAPTER : 8 80386

There are five 16-bit offset register are available and they are viz...
IP, SP, BP, SI and DI.
There are four 16-bit general purpose registers available and they are viz...
AX, BX, CX and DX.
Only the lower 12 bits of the flag register is available.
CRO and remaining control registers are not available. remaining bits of
In real mode, the size of main memory can be up to 1 MB only and address ranges from 00000H to
FFFFFH..
In real mode, the size of I\O address is 16 bits and therefore the total number of ports can be accessed
=65536.

Protected Mode of 80386:-

MICROPROCESSOR CHAPTER : 8 80386

80386 supports the protection mechanism and in protected model four privilege levels are available
where privilege level=0 is the highest and privilege level=3 is the lowest

Level0:-
Privilege level=0 is the highest privilege level and it is assigned to the kernel of the os.
Any program at privilege level=0 can access any data at any of the privilege but the data present
at this level can be accessed only by the programs present at this level and not by the programs
present at remaining privilege levels.

Level1:-
It is the 2nd most privileged level. This level is assigned to the system services. Any program present at
this level can access the any data which is present at this level or lower than this level but not the data
present at privilege level0.

Level2:-
It is the 3rd most privileged level. This level is assigned to os extensions. Any program present at this
level can access the any data which is present at this level or lower than this level but not the data present
at privilege levelo and privilege level1.

Level3:-
It is the least privileged levels. This level is assigned to the user applications and programs. The programs
present at this level can access any data from the programs present at this level and not at any other level.
MICROPROCESSOR CHAPTER : 8 80386

Control Registers of 80386:-

In 8086, there are four control registers available and they are explained as
follows:-

Control Register 0:-

The various bits of CRO are explained as follows:-

PG (Paging Enable):-
In 80386, paging is optional, therefore this pin is use indicate whether paging will be performed or not.
If PG-1, then paging will be performed and if PG=0, then the paging will not be performed.

ET (Extension Type):-
In 80386, Extension Type is used to indicate the type of the Math Co-processor interfaced with 80386.
If ET-1, then 80387 Math Co-processor is interfaced.
If ET=0, then 80287 Math Co-processor is interfaced.

TS (Task Switched):-
80386 supports multitasking and TS bit is used to indicate whether task switch is performed or not.
If TS=1, then Task switch will be performed.
If TS=0, then Task switch will not be performed.

EM (Emulate Co-processor):-
If co-processor is not connected to the 80386 so the EM bit will always be 1.
If EM = 1 then this will indicate that the co-processor is not present in the system and microprocessor
will emulate the co-processor (i.e. will execute the instructions of the co-processor).
If EM = 0 then the microprocessor will not emulate the Co-processor.
MICROPROCESSOR CHAPTER : 8 80386

MP (Math Co-processor Present):-

If MP = 1 then the Math Co-processor is present in the system.
If MP=0, then the Math Co-processor is not present in the

PE (Protection Enable):-
80386 enters in the protected mode by making PE bit=1 On reset, by default this bit is 0.

Control Register 1:-

Not used.

Control Register 2:-

This is a 32 bit register will stores the 32 bit linear address that caused the last page fault.

Control Register 3:-

This is used to store the upper 20 bits of the starting address of the page directory and the reason of
storing only upper 20 bits is that the page directory is of 4KB and is stored at 4KB aligned location so
the last 12 bits will be assumed to be 0 of the starting address of the page directory.

Address Translation Mechanism in Protected Mode:-

1) In 80386, the maximum physical memory (i.e. main memory) that can be accessed is 232 =4GB.
2) Virtual memory is the total space that can be accessed by the processor using its Registers.
3) Virtual address is made up of 16 bit segment address and a 32 bit offset address, therefore the .
virtual address is of 48 bits.
4) Here the segment register is used as a selector which selects a descriptor for the segment.
5) The size of the selector is 16 bits but two bits are used to give the privilege levels, which is used for
the protection mechanism.

6) Each selector value corresponds to a different segment, hence there can be max 2¹4 segments.
7) The total virtual memory that can be accessed 246 =64TB.
8) The total descriptors are 16k which can be stored either in LDT (Local Descriptor Table) or in GDT
MICROPROCESSOR CHAPTER : 8 80386

(Global Descriptor Table).

9) So basically there are 8k descriptors in GDT and 8K descriptors in LDT.
10) Out of 14 bits of the selector, 1 bit is reserved for TI, which is used to identify whether the
descriptor is present in LDT or in GDT.
11) If TI=1, then the descriptor is present in LDT and if TI=0, then the descriptor is present in GDT.
12) And 13 bit selector is enough to select a descriptor from GDT/LDT.
13) The virtual address goes as an input to the segment unit and segmentation is compulsory and after
performing segmentation the 48 bit virtual address is converted in to 32-bit linear address.
14) And paging is optional, if paging is not being performed then this 32 bit linear address is treated as
32 bit physical address.
15) And if paging is being performed then this 32 bit linear address goes as an input to the page unit
and after performing paging this 32 bit linear address is converted in to 32 bit physical address.

11 In 80385, the size of virtual address is 48 bits (1.0. and 32 bit offset address) 16 bit segment address
21 Out of 16 bits of segment address, 2 bits are used for protection mechanam and 1 bit is reserved for
Ti
31 So remaining 13 bits of segment address is used as selector to select a descriptor from LDT/GDT,
depending upon the Ti bit, if If Te, then GDT, bir Tin 1, then LDT and
4 The size of each descriptoris of & bytes
5 The descriptor is copied into an on chip segment descriptor cache.
There is a Pbit in the descriptor which is used to indicate whether the segment is present in the physical
memory or not.
Pbit then the segment is present in the physical memory and the base address in the descriptor gives the
starting address of the segment. If Pibit, then the segment is net-present is not present in the physical
memory and the base address in the descriptor does not gives the starting address of the segment.
And then the segment will be copied from virtual memory in to the physical memery and the base address
in the descriptor will be updated for the further use
21 Now, the offset address of 32 bits will be added on the base address to get the 32 bit linear address
of the desired location in the segment.
MICROPROCESSOR CHAPTER : 8 80386

Before giving the access to the desired location a series of protection checks are performed based on the
information given by the access rights
in the descriptor, such as limit not exceeded, type of segment, type of access, privilege level etc.
9) If the checks are valid, then the access to the desired location is given else a general protection fault
occurs.
10) If paging is not implemented, then the 32 bit linear address is treated as 32 bit physical address

Basic structure of a descriptor:-

PAGE Translation:-
MICROPROCESSOR CHAPTER : 8 80386

11 The virtual memory is divided in to equal size blocks of 4KB called pages.
2) The physical memory is also divided in to equal size blocks of 4KB called page frames.
32 31 The maximum size of physical memory can be 4GB l.e. 2" and size of each frame is 4KB i.e. 2,
therefore the physical memory can be divided in to 3M such page frames.
4) Now, there is a need to map which page is stored in which page frame in the physical memory since
any page from virtual memory can be loaded in to any
available page frame of main memory, so for the above reason there is a need of a page table.
5) Now, instead of having a single page table containing 1M entries upright, since it will make the
search process very slow, so we should have Ik page tables each containing 1k entries.
6) So this will help to make the search process little faster and each entry in the page table will be
called as PTE (Page Table entry) and each entry will be of 4 bytes and therefore size of each page
table will be of 4KB and each page table
will be stored at a 4KB aligned location. 7) Each PTE will give following information
Upper 20 bits will give the starting address of the page frame and the last 12 bits will be O as
explained earlier.
D: Dirty Bit indicates whether the page has been modified or nat If D=1, page is modified. If D=0, page
is not modified.
A: Accessed bit will indicate whether the page has been accessed
If A=1, page is accessed.
If A=0, page is not accessed.
This bit is used by page replacement algorithms
U/S: User or Supervisor.
R/W: Read or Read and write.
P: Present bit will indicate whether the pace is present in the physical memory or
not.
If P=1, the page is present in the physical memory and the address indicated by the upper 20 bits is valid.
If p=0, the page is not present resent in the by the upper 20 bits is invalid physical memory and the
address indicated (And if the page is not present in the physical memory it is termed as a page fruit or
page miss and the memory management unit will copy the desired page from the virtual memory in to
available page frame in physical memory using zags replacement algorithms).
8) Now, we also need to keep the track of which page table contains which sat entries and for that a
MICROPROCESSOR CHAPTER : 8 80386

page directory is required.

9) The total number of entries in the page directory will be 1k and each any will be of 4 bytes and that
entry will be called as PDE (Page Directory Encry therefore the size of page directory will be 4K8
and it will de stored at a 463 aligned location.
10) The base address (i.e. starting address) of the page directory will be given de PDBR (Page
Directory Base Register) whose upper 20 bits are stored in RS register and last 12 bits will be 0
since the size of page directory4KB and it stored at a 4KB aligned location.
11) Each PDE gives following information Upper 20 bits gives the starting address of the
corresponding be of the address will be O as explained earlier.
available page frame of main memory, so for the above reason there is a need of a page table.
5) Now, instead of having a single page table containing 1M entries upright, since it will make the
search process very slow, so we should have 1K page tables each containing 1K entries.
6) So this will help to make the search process little faster and each entry in the page table will be
called as PTE (Page Table entry) and each entry will be of 4 bytes and therefore size of each page
table will be of 4KB and each page table
will be stored at a 4KB aligned location. 7) Each PTE will give following information:-
Upper 20 bits will give the starting address of the page frame and the last 12 bits will be O as explained
earlier.
D: Dirty Bit indicates whether the page has been modified or not.
If D-1, page is modified.
If D=0, page is not modified.
A: Accessed bit will indicate whether the page has s been accessed or not,
If A-1, page is accessed.
If A=0, page is not accessed.
This bit is used by page replacement algorithms.
U/S: User or Supervisor.
R/W: Read or Read and write.
P: Present bit will indicate whether the page is present in the physical memory or
not.
If P-1, the page is present in the physical memory and the address indicated by the upper 20 bits is valid.
If p=0, the page is by the upper 20 bits is invalid. not present in the physical memory and the address
indicated
(And if the page is not present in the physical memory it is termed as a page fault or page miss and the
memory mariagement unit will copy the desired page from the virtual memory in to available page frame
in physical memory using page replacement algorithms).
8) Now, we also need to keep the track of which page table contains which set of entries and for that a
page directory is required.
9) The total number of entries in the page directory will be 1k and each entry will be of 4 bytes and
that entry will be called as PDE (Page Directory Entry), therefore the size of page directory will be
4KB and it will be stored at a 4KB aligned location.
10) The base address (l.e. starting address) of the page directory will be given by PDBR (Page Directory
Base Register) whose upper 20 bits are stored in CR3 register and last 12 bits will be 0 since the size
of page directory is 4KB and it is stored at a 4KB aligned location.
11) Each PDE gives following information:-
Upper 20 bits gives the starting address of the corresponding table, last 12 bits of the address will be
o as explained earlier.
Remaining bits are explained earlier.
12) The 32 bit linear address is divided in to 3 parts and they are as follows:
MICROPROCESSOR CHAPTER : 8 80386

i) Upper 10 bits are used to select the desired PDE from 1K PDE's present in the page directory.
ii) The next 10 bits are used to select the desired PTE from 1k PTE's present in the corresponding
page table.
iii) The last 12 bits are used as a offset to select a desired location from in the 4KB page.
13) In this way, the paging is implemented in 80386 and after performing we conve the 32 bit linear
address in to 32 bit physical address
MICROPROCESSOR CHAPTER : 9 sun sparc

Chapter-9. SUN SPARC

Architecture of sunsparc:-

SPARC ARCHITECHTURE

The SuperSPARC manufactured by Texas Instruments (TI) in co-operatic. With Sun Microsystems. As
shown in Fig. the Sun SuperSPARC processor contains Integer Unit(IU), Floating Point Unit (FTU),
Memory Management Unit (MMU), Floating split cache (20KB code and 16KB data). It is a three issue
superscalar system i e it can execute upto three instructions simultaneously.
Cache coherent bus interface unit:
The Sun SuperSPARC has 36 address line :s and can hence access up to a total of 64 GB physical
memory. The number of data lines in SuperSPARC is 64; hence we have eight banks as in Pentium
processor system.
Split cache:

The Sun Supersparc has 20KB of code cache (instruction cache) with five way set associative mapping.
The data cache is 16KB which is four way set associative.

Prefetcher and queue:

The Prefetcher fetches the instructions from the instruction cache and places them in the instruction
queue. The instruction pairability cheek is performed and upto three instructions are issued to be
MICROPROCESSOR CHAPTER : 9 sun sparc

executed simultaneously

IU file and FP file:

These are register files for integer execution unit and floating point unit.
Integer control unit

• The integer unit dynamically selects "a group" of up to three instruction in each cycle .
• This is accomplished by grouping logic which scans the next available instructions, and selects from
zero to three for execution.
• The remaining instructions from either the sequential or target instruction and selects from zero to
three for execution.
• It allows for most combinations of independent as well as dependent integer operations to be
Completed.
• Memory reference address calculation are performed using a dedicated set of register file ports and
a dedicated virtual address adder.
• The virtual address is then used by the cache and NMI to access load/store data Floating point unit
• It is capable of executing single and double precision floating point operations
• It is optimized fur double precision operations
• The FPU provides a 4-entry floating point instruction queue and a five port floating point register
file.
• One unique feature of the FPU is that dependent floating point instructions may be issued in the same
instruction group.

Cache and MMU operation

• SuperSPARC uses fully physically addressed caches
• The caches re organized as set associative caches, each set of the cache is required to he equal to the
minimum page size ([Link])
• The Caches are accessed in parallel with the MMU.

Memory Model in Sun SPARC

• The SPARC memory model defines the method of memory operations such as load and store, and
specifies how the order in which these operations are issued by a processor is related to the order in
which they are executed by memory.
• A standard memory model called as Total Store Ordering, (TSO) is defined for SPARC. The model
applies to both the uniprocessors and the shared-memory multiprocessors.
• The memory model guarantees that the stores, FLUSHes and atomic load-stores of all processor are
executed by memory serially in an order that match to the order in which the instructions were issued
by processors.
• All SPARC implementations must support TSO.
• Another model called Partial Store Ordering (PSO) built. ) allows higher-performance memory
systems to be built.
• Machines (including all early SPARC-based systems) that implement Strong Consistency (also
(also known as Strong Ordering) automatically satisfy both the TSO sad the PSO. Machines that
implement TSO also automatically satisfy PSO.
• Programs written using single-writer-multiple-readers locks will be Strong Consistency. portable
across PSO, TSO and
MICROPROCESSOR CHAPTER : 9 sun sparc

• Programs that use write-locks but read without locking will be portable across PSO, TSO and Strong
Consistency only if writes to shared data are separated by STBAR instructions. If these STBAR
instructions are omitted, then the code will be portable across TSO and Strong Consistency only. The
guidelines for other programs are as follows

1. Programs written for PSO machine will work automatically on a TSO machine or on a Strong
Consistency machine
2. Programs written for TSO machine will work automatically on a Strong Consistency machine
3. Programs written for Strong Consistency machine may not work on a TSO or PSO machines
4. Programs written for ISO machine may not work on a PSO machine.

• Multithreaded programs where all threads are restricted to run on a single processor will behave the
same on PSO and TSO machines as they would on a Strongly Consistent machine.
• Input/Output SPARC assumes that input/output registers are accessed via load/store alternate
instructions, normal load/store instructions coprocessor instructions or read/write ancillary state
register instructions i.e(RDASR and WRASR)
• In the load/store alternate instructions case, the I/O registers can be accessed by the supervisor only.
• If normal load/store instructions, coprocessor instructions or read/write Ancillary State Register
instructions are used, whether the I/O registers can be accessed besides the supervisor or not is
implementation dependent.
• The contents and addresses of I/O registers are also implementation-dependent.
Before we see these memory models in detail, we need to know some definitions according to
SPARC
1. Real Memory: Real (or main) memory is defined as those memory locations accessed which have
either of the following.

•The ASI field is 8, 9, OxA or OxB

• The ASI field, together with a field I in a corresponding : MMU entry, implies a reference to real
memory. (i.e. ASIs Ox20-2F )2.
1/O registers are locations that are not real memory locations. I/O locations include the following:
• Those memory locations accessed when the ASI field is not 8,9,OxB or Ox20-2F
• Those memory locations with the ASI field8, 9, OxA or OxB and a field in a corresponding MMU
entry identifies the access as an I/O access
• Coprocessor registers
• Ancillary state registers

Overview of Memory Model

Memory is byte-addressed, with half word (16-bit accesses aligned on 2-byte boundaries, word (32-bit)
accesses aligned on 4-byte boundaries, and double word (64-bit) accesses aligned on 8-byte boundaries.
The largest data that is atomically read or written by memory hardware is a double word.
The memory references to different bytes, half words and words in a given double word boundary are
treated for ordering purposes as references to the same location. Thus the unit of ordering for memory
is a double word.
A processor initiates the memory operation via its port in what is called the issuing order. Each port
contains a Store Buffer used to hold stores, FLUSHes, and atomic load-stores operation. A switch
MICROPROCESSOR CHAPTER : 9 sun sparc

connects a single-port memory to one of the port at a time, for the duration of each memory operation

(kind of time multiplexing) The order in which this switch is thrown from One port to another is
nondeterministic and it defines the memory order of operations.
For this memory each processor consist of an idealized Processor(IP) and instruction Buffer (IBuf)
• IP executes one instruction at a time as specified by the TSP, without overlap, in what is called
program order. For each instruction the IP fetches the IBuf. IBuf may also prefetch the instructions
via memory port. Thus IBuf models the prefetch queue of instruction pipelining and/or a instruction
cache, in a processor implementation
The issuing order of data loads rind stores match to the order of the coressponding instructions in
program order. However, the issuing order of instruction loads in general does not match to the order
of the instructions fetches, defines program order.
• The FLUSH instruction synchronizes instruction fetches with data loads and stores. For e.g. when a
processor executes FLUSH A, the data corresponding to location A is removed from the IBufs of all
processors in the system some time after the execution of the FLUSH.

Total Store Ordering (TSO) Total Store Ordering guarantees that the store, FLUSH and atomic load-
store instructions of all processors appear to be executed by memory serially id a single order called the
memory order. Also, the sequence of store, FLUSH, and atomic load-store instructions in the memory
order for a given processor is identical to the sequence in which they were issued by the processor. Fig.
below shows the ordering constraints for this model graphically.

FLUSHes, and atomic load-stores issued by processor, are placed in its dedicated FIFO Store Buffer.
The order in which memory executes the operations for a given processor is the same as the order in
which the processor issued them. The order of these operations corresponds to the order in which the
switch is thrown from one port to another.

• To maintain consistency, a load by a processor first checks its Store Buffer to see if it contains a store
to the same location (atomic load-stores do not need to be checked because they block the processor). If
it does, then the load returns the value of the most recent such store from the buffer; else the load
goes directly to memory.

Partial Store Ordering (PSO)

• Partial Store Ordering guarantees that the store, FLUSH and atomic load-store instructions of all
processors appear to be executed by memory serially in a single order i.e. the memory order. But, the
memory order of store, FLUSH, and atomic load-store instructions for a given processor is, not the same
as the order in which they were issued by the processor.

• Match between issuing order and memory order is provided by use of the STBAR instruction. If two
of the instructions are separated by an STBAR in the issuing order of a processor, or if they reference
the same location, then the memory order of the two instructions is the same as the issuing order.

•Fig. 16.8.4 shows the Partial Store Ordering (PSO) Memory Model
Here also Stores, FLUSHes and atomic load-stores issued by a processor are placed in its dedicated Store
Buffer, However, this buffer is not guaranteed to be FIFO as it was in TSO; it does maintain the order
of stores and atomic load-stores to the same location, but otherwise it is partitioned only by the
occurrence of STBAR instructions.
MICROPROCESSOR CHAPTER : 9 sun sparc

• Thus the order in which memory executes two stores or atomic load-stores that are separated by an
STBAR for a given processor is the same as the order in which the processor issued them.
Data format
Sun SPARC implements two types of data formats viz. Integer and Floating point data formats.

Integer Data Formats

The integer data formats are byte (8 bit), halfword (16-bit), word 32-bit and double word (64-bit). These
data formats are available as signed or unsigned. As shown in the Fig. 16.4.1, the signed data formats
have MSB as sign BIT and remaining bits as magnitude. While the unsigned have all the bits as
magnitude, shown in below.

Floating Point

Besides the IEEE 754 standards of floating point representation, Sun SPARC also supports a higher
precision called as Quad-precision format. Hence Sun SPARC supports Single precision format as
shown in Fig, which is a 32-bit IEEE 754 floating point standard. Sun SPARC also supports Double
precision format as shown in Fig, which is a 64-bit IEEE 754 floating point standard. Sun SPARC also
supports Quad precision format as shown in Fig. 16.4.2 (c), which is a 128-bit Mating point format.

As shown in the figure, single precision has 8 bits for biased exponent, while double precision has 11
bit biased exponent and quad precision has 15 bits for exponent. The MSB of each of these formats is
the sign bit. The remaining bits 23 bits in case of single precision, 52 bits in case of double precision
and 112 in case precision are meant for fraction (mantissa) part.

SPARC Instruction Formats

RISC processors have less number of instruction format. There are three bask instruction formats in Sun
SPARC

1. CALL
2. Branch Instructions
3. Operate instructions (register to register)

As seen in Fig below, each format has 2 bits for the opcode. The fields marked op2 or op3 are also
opcodes (additional information of the opcode for integer instruction), while opf field (floating point
opcode field) are opcode to indicate, the, floating point operation.

In the first, format (Format 1), as shown in, the remaining 30 bits are for the displacement for the call
instructions.

The second format (Format 2, case 1) is specially meant (Or the SETHI instruction, which sets the first
22 bits of the destination registered to the 22-bit immediate data given in the instruction.

The trird format (Format 2, case 2) is meant for branching instructions. This format has four hits for
condition and 22 bits for displacement from the current value of program counter.

The "i" hit in the format. ;t, indicate"; if the data is immediate or register addressing mode: (i=0 indicates
register addressing mode; i=1 indicates immediate addressing mode.)
MICROPROCESSOR CHAPTER : 9 sun sparc

The Fields rs1 and rs2 are the source rogisters, while the field rd is destination register. The instructions
in SunSPARC are normally three operand instructions where the two source operands and the destination
operands are different. In case of the immediate addressing mode format (where i=1); there is a field
called as simm13, which is immediate 13-bit data. In the register addressing mode format (where i=0),
there is a field called as ASI (Address Space Indicator). The ASI is used to indicate the normal or
privileged memory locations. For the last format, which floating point format instruction, also two source
operands (rs1 and rs2), a destination operand (rd) and a opcode information using the bits opf.