UNIT 1

Introduction to embedded system

System:
A system is a way of working, organizing or doing one or many tasks according to a fixed plan,
program, or set of rules. A system is also an arrangement in which all its units assemble and
work together according to the plan or program.
Example:
Watch, washing machine
Embedded system:
Definition:
One of the definitions of embedded system is as follows:
“An embedded system is a system that has embedded software and computer-hardware, which
makes it a system dedicated for an application(s) or specific part of an application or product
or a product a larger system."
A computer is a system that has the following or more components.
I. A microprocessor
2. A large memory at the following two kinds:
(a) Primary memory (semiconductor memories: Random Access Memory (RAM), Read Only
Memory (ROM) and fast accessible caches)
(b) Secondary memory [(magnetic memory located in hard disks. diskettes and cartridge tapes.
optical memory in CD-ROMs or memory sticks (in mobile computers)] using which different
user programs can he loaded into the primary memory and run
3. V) units such as touch screen, modem, fax cum modem, etc.
4. Input units such as keyboard, mice, digitizer, scanner, etc.
5. Output units such an LCD screen, video monitor, printer, etc.
6. Networking unit such as an Ethernet card, from-end processor-based server, bus drivers, etc.
7. An operating system (OS) that has general purpose user and application software in the
secondary memory
An embedded system is a system that has three main components embedded into it
I. It embeds hardware similar to a computer. Figure 1.1 shows the units in the hardware or an
embedded system. As its software usually embeds in the ROM or flash memory, it usually do
not need a secondary hard disk and CD memory as in a computer
2. It embeds main application software. The application software may concurrently perform a
series of tasks or processes or threads
3, Itembeds a real-time operating system (RTOS) that supervises the application software
running on hardware and organizes access to a resource according to the priorities of tasks in
the system. It provides a mechanism to let the processor run a process as scheduled and context-
switch between the various processes. (The concept of process. thread and task explained later
in Sections 7.1 to 7.3.) It sets the rules during the execution of the application software. (A
small-scale embedded system may no embed the RTOS)
Built-in process:
Assembly language coding is extremely useful for configuring physical devices like ports. A
line-display interface, ADC and DAC and reading into or transmitting from a buffer. These
codes are also called low-level codes for the device driver functions
Lack of knowledge of writing device driver codes or codes that utilize the processor-specific
features- invoicing codes in an embedded system design team can cost a lot a vendor may
charge for the APIs and also charge intellectual property fees for each system shipped out of
the company.
To make all the codes in assembly language may, however, be very time consuming. Full
coding assembly may be done only for a few simple, small-scale systems, such as toys,
automatic chocolate vending machines, robots or data acquisition systems.
1. An assembler translates the assembly software into the machine codes using a step called
assembling.
2. In the next step, called linking, a linker links these codes with the other codes required.
Linking is necessary because of the number of codes to be linked for the final binary file. For
example, there are the standard codes to program a delay task for which there is a reference in
the assembly language program. The codes for the delay must link with the assembled codes.
The delay code is sequential from a certain beginning address. The assembly software code is
also sequential from a certain beginning address. Both the codes have to be linked at the distinct
addresses as well as at the available addresses in the system, the linked file in binary for run
on a computer is commonly known as an executable file or simply an ‘.exe’ file. After linking,
there has to be reallocation of the sequences of placing the codes before actually placing the
codes in memory.
3. In the next step, the louder program performs the task of reallocating the codes after finding
the physical memory addresses available at a given instant. The loader is a pail of the operating
system and places codes into the memory after reading the ‘exe’ rile. This step is necessary
because the available memory addresses may not start from Ox0000, and binary codes have to
be loaded at different addresses during the run. The loader finds the appropriate start address.
In a computer, after the loader loads into a section of RAM, the program is ready to run.
4. The final step of the system design process is locating these codes as a ROM image. The
codes are permanently placed at the addresses actually available in the ROM. In embedded
systems, there is no program to keep track of the available addresses at different times during
the run, as in a computer. In embedded systems, therefore, the next step instead of loader after
linking is the use of a locater, which locates the I0 tasks and hardware device driver codes at
fixed addresses. P0(1 and device addresses are fixed for a given system as per the interfacing
circuit between the system buses and ports or devices. the locator program reallocates the
linked file and creates a file for a permanent location of the codes in a standard format. The file
format may be in the Intel Hex file format or Motorola s-record format .The designer has to
define die available addresses to locate and create files to permanently locate the codes.
5. Lastly, either (i) a laboratory system. called device programmer, takes as input the ROM
image file and finally burns the image into the PROM or flash or (ii) at foundry, a mask is
created for the ROM of the embedded system from the ROM image file. (The process of
placing the codes in PROM or flash is also called burning.]The mask created from the image
gives the ROM in IC chip form.
Build Process of Embedded Systems:

Design Process in Embedded System

• Design Metrics
– Power Dissipation
– Performance
Process Deadlines
– User Interfaces
– Size
– Engineering Cost
– Manufacturing Cost
– Flexibility
Prototype Development Time
– Time to Market
– System and User Safety
– Maintenance
 1.1 STRUCTURAL UNITS

The processor in any embedded system contains various units for its successful and fast
operation. Buses, memories, processing units, instructions, registers, and control units are some
of the structural units that an embedded processor should possess.
For quick operation, the system may have advanced processing units for superscalar and
pipeline processing. Let us discuss some of the structural units in an embedded processor.
1. Internal Buses
It internally connects all the structural units inside the processor. Its width can be of 8, 16, 32
or 64 bits. The internal buses include address bus, data bus and control bus. All the internal
units of the processor are communicated with the external buses through an interface unit
called Bus Interface Unit(BIU).
 Address bus is an external bus that carries the address from the Memory Address
Register(MAR) to the memory as well as to the IO devices and other units of the system.
 Data bus is an external bus that carries the data from or to the address determined by Memory
Address Register(MAR).
 Control Bus is an external bus that carries, control signals to or between the processor and
memory.
2. Instruction Units
The processor executes several operations with the help of a piece of code or program called
instructions. All these instruction are arranged in a queue called Instruction Queue(IQ). This
helps the Instruction Register to execute the instructions without the need to wait.
Instruction Register(IR) takes the instruction codes(opcodes) sequentially to the execution unit
of the processor. Instruction decoder(ID) decodes the instruction opcode received at the
Instruction Register and passes it to the processor Control unit for its execution..
3. Caches
In general, cache is the temporary storage place in the processor, where the data can easily be
retrieved by the CPU for quick operation. Cache is available in your computers, laptop, mobile
phone, browser, app, etc. The embedded processor has three cache memory for fast operation.
Similar to an instruction queue, Instruction Cache(I-Cache) sequentially stores the instructions
in FIFO mode. It lets the processor to execute the instructions at a greater speed.
Branch Target Cache(BT Cache) facilitates the ready availability of the next instruction set,
when a branch instruction like jump, call or loop is encountered. Its fetch unit foresees a
branching instruction in the I – cache.
 Data Cache(D – Cache) stores the pre – fetched data from the external memory. A data cache
holds both the address and data together at a location. It also stores the write-through data that
is to be transferred to the external memory addresses. Write-through data is nothing but the
output data from the execution unit.
4. Control Units
The control unit(CU) is one of the important structural units in an any embedded processor. It
is responsible for all the control of the bus activities and unit functions needed for processing.
It directs all the units of a processor to respond to the instruction that is executed.
Pre fetch control Unit(PFCU) controls the fetching of data into the I-Cache and D-Cache in
advance from the memory unit. The instructions and data are delivered when needed to the
processor’s execution units.
Memory Management Unit(MMU) manages the memories such that the instructions and data
are readily available for processing. There are several memory management methods for
managing the memory in an embedded processor such as fixed block allocation, dynamic block
allocation, dynamic page allocation, etc.
5. Processing Units
Processing units receives the input data, process it and produces the output. Depending on the
function of the embedded system, the processing is done through different units like ALU,
FLPU, AOU and advanced units.
Arithmetic Logic Unit(ALU) is used for the execution the arithmetic and logic instructions
according to the instruction present at the Instruction Register.
floating point processing unit(FLPU) is different from ALU, used primarily for floating point
processing. It is essential for fast processing mathematical functions in a microprocessor or
Digital Signal Processor.
Atomic operation unit(AOU) lets a user (compiler) instruction when broken into number of
processor instructions called atomic operations, finish before an interrupt of the processor
occurs.
The embedded processor also has Advanced processing units for multistage pipeline
processing, multi-line superscalar processing to obtain processing speeds higher than one
instruction per cycle.
6. Register Sets
Application Register Set(ARS) is a set of on-chip registers used during processing of
instructions of the application program of the user. A register window consists of a subset of
registers with each subset storing static variables of software – routine.
system Register Set(SRS) is a set of registers used while processing the instructions of the
supervisory system program.
Floating point register set(FRS) is dedicated for storing floating point numbers in the standard
format and used by Floating point Processing Units for its data.
7. Memory Registers
Registers are smallest part of the CPU, where the data and address can be stored and accessed
quickly. There are various registers like accumulator, general purpose registers, flag registers,
memory address register, memory data register, program counter, stack pointer, etc.
Memory Address Register(MAR) holds the address of the data byte or word that is to be fetched
from external memories. Memory Data Register(MDR) holds the data byte or word that is
fetched from external memory or stored to the external memory.
8. Program Counter and Stack Pointer
Program counter is a register that stores the address of the next instruction to be executed from
the memory. It generates the instruction cycle to fetch the address from memory through MAR.
Stack pointer is a register that stores the address of the last program request in a stack. It is a
pointer for an address which corresponds to a stack top in the memory.
 1.2 PROCESSOR EMBEDDED INTO A SYSTEM
A processor is an important unit in the embedded system hardware. It is (he hean of the
embedded system.
Knowledge of basic concept of microprocessors and microcontrollers is must loran embedded
system designer.
The processor is selected from the following considerations
Instruction Set
– Maximum bits in an operand in an operation
– Processing Speed
– Ability to solve the complex algorithms
– A processor gives high computing performance when it has
Pipeline and Superscalar architecture
• Pre-fetch cache unit, caches, register files and MMU
• RISC core architecture
– A processor with register windows provides fast context switching in a multitasking system.

– A Processor has auto shut down features for its Units.

– A processor with burst mode accesses external memories fast.

1.2.1 Embedded Processors in a System
A processor has two essential units: Program Flow Control Unit (CU) and J3xecrnion Unit
(EU). The CU includes a fetch unit for fetching instructions from (he memory. The EU has
circuits that implement the instructions pertaining to data transfer operations and data
conversion from one form to another. The EU includes the Arithmetic and Logical Unit (ALU)
and also the circuits that execute instructions for a program

Memory Case 1: Case 2: Case 3: Case 4: Case 5:

required Automatic Data Multi port Voice Digital camera
chocolate acquisition network processor or voice
vending system transceiver. or video recorder
machine or Fast processing system
real time switches, or mobile
robotic routers, or phone or
control system multi pocket PC
channel fast system
 or
encryption
and
decryption
system
Processor microcontroll microcontroll Microproces Microproce Microprocesso
used er er sor system ssor + DSP r
based
multiproces
sor system
Internal 4 to 32 KB 8KB - - -
ROM or
EPROM
Internal 256 to 512 B 256 to 512 B - - -
EEPROM
Internal 256 to 512 B 256 to 512 B - - -
RAM
ROM or No no 64KB 64KB 64KB
EPROM
device
EEPROM or No 64 to 128 512B 32KB TO Flash 16MB
flash device 256KB YO 8 GB
2 TO 8 GB memory sticks
Memory
sticks
RAM device No 64 KB TO 512 64 KB TO 8MB 1MB
MB 512 MB
Parameterise No No Yes for IO -
d distributed buffers 4 kb
RAM per channel
Parameterise No no Yes for -
d block RAM MAC unit ,
dialing IO
unit

Selection of Memory Devices:

A simple credit-debit transaction card may require just 2kB of memory.
◦ On other hand, smart card for secure transactions (cryptographic functions) require 32kB of
memory.
◦ A memory- a data byte, or a word, or a double word, or a quad word may be accessed from all
addressable locations with a similar process and there is would be equal access time for a read
or for a write operation.
 ◦ Memory is the important resource, there is a constant interaction and
communication between the processor.
◦ Semiconductor memory is the primary memory
◦ Hard disk is the secondary memory
◦ All programs run with the data and code in the RAM
◦ Virtual memory is a concept by which the application is made to believe that it
has much more memory than in physically available.
◦ Enlarged Address space which is also a virtual address space.

ROM: Uses, Forms & Variants:

 Non- Volatility is an important asset useful to embed codes & data in a system.
 ROM embeds software/application logic circuit in either forms – Masked ROM,
PROM & EPROM.
 During runtime programming EEPROM/Flash memory is used.

Masked ROM:

 One time masking charge – very high

 Therefore, system manufacturer will place order & manufacturing foundry will
accept the order for a minimum of 1000 pieces.
 ROM is a cost effective solution to a bulk user.
 EPROM:
o It is an ultraviolet ray erasable & device programmable.
o Erasing means restoring 1 at each bit.
 EEPROM:
o Electrically Erasable and Programmable Read Only Memory
 Flash Memory:
o Form of EEPROM, in which sector of bytes can be erased in a flash.
 PROM:
o Once written is not erasable.
o OTP (One Time device Programmer)

A system designer considers RAM devices of EIGHT forms.

1. SRAM – Static RAM,
2. DRAM – Dynamic RAM,
3. NVRAM – Non Volatile RAM,
4. EDORAM – Extended Data Output RAM,
5. SDRAM – Synchronous DRAM,
6. RDRAM – Rambus DRAM,
7. Parameterized distributed RAM and
8. Parameterized Block RAM.
USES:
 Stores variables during a program run & stores stack.
 Stores input & output buffers.
◦ Eg: Speech & Image

1. SRAM: commonly used for designing caches & in embedded systems and
microcontrollers.
2. DRAM: mostly used in high performance computers / high memory density systems.
3. EDORAM: used for system having buses with clock rates up to 100MHz.
4. SDRAM: synchronizes read operations & keeps next word ready, used for processor
speed of 1GHz.
5. RDRAM: accesses in burst (four successive words in a single fetch), thus performance
1GHz speed.
6. Parameterized distributed RAM: distributes in various system sub-units - IO buffers
& transceiver sub-units. Distribution provides buffering of memory at subunits &
facilitates faster inputs from IO devices.
7. Parameterized Block RAM: used when specific block of RAM is dedicated to sub-
unit (eg: MAC unit), used when access by the system / IO / Internal bus is slow
compared to processing speed of sub-unit.

MemorySelectionforanEmbeddedSystem
— Once Software designer’s coding is over and the ROM image file is ready, a hardware
designer is faced with the questions, of what type of memory and what size of each should be
used.
CASE STUDIES:

1. Automatic chocolate vending machine or real time robotic control system.

2. Data Acquisition Systems
3. Multi-port network transceivers, Fast switches, Routers, or Multi-channel Fast
Encryption and decryption System
4. Voice processor or video processing or Mobile Phone system
5. Digital Camera or Video recorder [Link], Processes, Data and Stacks
at the Various Segments of Memory:
6. Program routines & processes can have different segments.
7. A pointer address, points to the start of memory block storing a segment and an
offset value is used to retrieve for a memory address within that segment.
8. Segment wise memory allocation in four segments:Code, Data, Stack and
Extra (for examples, image, String)
9. A segment can have partitions of fixed sizes called PAGES.

Figure shows different segment types required by software designer.

Different Data Structures/Sets at Various Memory Blocks:

Stacks –

• allotted memory block, from which data is read (LIFO)

• Return addresses on the nested calls,
• Sets of LIFO (Last In First Out) retrievable data,
• Saved Contexts of the tasks as the stacks
 2) Arrays – One dimensional or multidimensional data can be retrieved from any element
address.
3) Queues – Sets of FIFO (First In First Out) retrievable data;Two pointer (Front/Head &
Back/Tail)
Circular Queue (Example- a Printer Buffer);
bounded memory block, on exceeding limit reset to start. For Circular Queue, when back
attempts to exceed end, back becomes equal to start.

PIPE / Block Queue (Example- a network stack)

common memory block allotted for a queue with source & destination.

4) Table – two dimensional array (matrix)

three pointers – table base, column index, destination index pointer
5) Hash Table – collection of pairs of key & corresponding [Link] set allocated with a
memory block - Look-up-table
6) List – a data structure with number of memory blocks, one for each [Link] list-element
stores pointer to next element last element points to NULL.A list is for non-consecutively
located objects at the memory.
DIRECT MEMORY ACCESS

A DMA is required when a multi-byte data set or a burst of data or a block of data is to be
transferred between the external device and system or two systems. A device facilitates DMA
 transfer with a processing element (single purpose processor) and that device is called DMAC
(DMA Controller).
Three modes of DMA operations:
◦ Single transfer at a time and then release of the hold on the system bus.
◦ Burst transfer at a time and then release of the hold on the system bus. A burst may be of a
few kB.
◦ Bulk transfer and then release of the hold on the system bus after the transfer is completed.
Data transfer occurs efficiently between I/O devices and system memory with the least
processor intervention using DMAC.

◦ Separate set of registers for programming each channel.

◦ Separate interrupt signals in the case of a multichannel DMAC

DMA proceeds without the CPU intervening,Except (i) at the start for DMAC programming
and initializing and (ii) at the end.
◦ Whenever a DMA request by external device is made to the DMAC, the CPU is requested
(using interrupt signal) the DMA transfer by DMAC at the start to initiate the DMA and at the
end to notify (using interrupt signal) the end of the DMA by DMAC.
A typical DMA controller includes three registers:
 Starting Address Register
 Length Register
 Status Register

TIMERANDCOUNTINGDEVICES

TIMER
◦ Timer is a device, which counts the input at regular interval (δT) using clock pulses at its input.
◦ The counts increment on each pulse and store in aregister, called count register
◦ Output bits (in a count register or at the output pins) for the present counts.
COUNTER:
 ◦ A device, which counts the input due to the events at irregular or regular intervals.
◦ The counts gives the number of input events or pulses since it was last read.
◦ Has a register to enable read of present counts
◦ Functions as timer when counting regular interval clock pulses.
Timer States:
 Reset State (initial count = 0)
 Initial Load State (initial count loaded)
 Present State (counting or idle or before start or after overflow or overrun)
 Overflow State (count received to make count = 0 after reaching the maximum count)
 Overrun State (several counts received after reaching the overflow state)
 Running (Active) or Stop (Blocked) state
 Finished (Done) state (stopped after a preset time interval or timeout)
 Reset enabled/disabled State (enabled resetting of count = 0 by an input)
 Load enabled/disabled State (reset count = initial count after the timeout)
 Auto Re-Load enabled/disabled State (enabled count = initial count after the timeout)
 Service Routine Execution enable/disable State (enabled after timeout or
 overflow)
Timer cum Counting Device:
It is a counting device that has two functions:
• It counts the input due to the event at irregular instances and
• It counts the clock input pulses at regular intervals.

Control bits are as per the hardware signals and corresponding bits at the control register.
Control bits (or signals) can be of nine types.
1. Timer Enable (to activate a timer).
2. Timer Start (to start counting at each clock input).
3. Timer Stop (to stop counting) from next clock input).
4. Pre-scaling bits (to divide the clock-out frequency signal from the processor).
5. Up count Enable (to enable up counting by incrementing the count value on each clock input)
6. Down Count Enable (to decrement on a clock input).
7. Load Enable (to enable loading of a value at a register into the timer).
8. Timer Interrupt Enable (to enable interrupt servicing when the timer outs (overflows) and
reaches count value = 0)
 9. Timer Interrupt Enable [to enable interrupt servicing when the timer overflows (reaches count
=0)].
Ten forms of a Timer:
1. Hardware internal-Timer
2. Software timer (SWT)
3. User software-controlled hardware timer
4. RTOS controlled hardware timer. An RTOS can define the clock ticks per second of a hardware
timer at a system.
5. Timer with periodic time-out events (auto-reloading after overflow state).A timer may be
programmable for auto-reload after each time-out.
6. One shot timer (No reload after the overflow and finished state). It triggers on event-input for
activating it to running state from its idle state. It is also used for enforcing time delays between
two states or events.
7. Up count action Timer. It is a timer that increments on each count-input from a clock.
8. Down count action Timer. It is a timer which decrements on each count-input.
9. Timer with its overflow-flag, which auto resets as soon as interrupt service routine starts
running.
10. Timer with overflow-flag, which does not auto reset.
Software timer – SWT:
 Innovative concept – VIRTUAL Timing device.
 A software, which executes and increases or decreases a count-variable (count value) on an
interrupt from system timer output or real time clock interrupt.
 The software timer also generate interrupt on overflow of count-value or on finishing value of
the count variable.
• SWT is a timer based on the system clock interrupts
• The interrupt functions as a clock input to an SWT.
• This input is common to all the SWTs that are in the list of activated SWTs.
• Any number of SWTs can be made active in a list.
• Each SWT will set a status flag on its timeout (count-value reaching 0).

WATCH DOG TIMER

Watch dog timer is a device that can be set for a present interval, and an event error must occur
during that interval else the device will generate the time out signal .For example, we anticipate
that a set of tasks must finish within [Link] watch dog timer disables and stops in case the
tasks finish within 100ms. The watch dog timer generates the interrupts after 100ms and
executes a routine that runs because the tasks failed to finish in the anticipated interval. A
software task can also be programmed as a watchdog timer.
 The watchdog timer has a number of applications. One application in a mobile phone is that
the display is turned off in case no GUI interaction takes place with specified time. The interval
is usually set at 15, 20 , 25 , or 30 s in a mobile phone. This saves power.
Another application in a mobile phone is that if a given menu is not selected by a click within
a pre-set time interval, another menu can be presented or a beep can be generated to invite
user’s attention.
An application in a temperature controller is that if a controller takes no action to switch off
the current within the pre-set time, the current is switched off and a warning signal raised,
indicating controller failure. Failure to switch off current may cause a boiler in which water is
heated to burst.

• Example: checking the stack depth, number of buffers allocated and the state of mechanical
components in the system before resetting the watchdog timer.
• A flag should be set at various points in the code indicating the successful completion of that
block of code.
• Before the timer is reset, all flags are checked, if all the flags have been set, the timer can be
retriggered for another interval.
• If not, the failure mode is recorded and the timer is allowed to time out.
What applications require WDTs?
• MCUs are used in all sorts of electronic devices, but whether a WDT is required or not
depends on the “level of safety demanded by or deemed necessary for a specific
application.”
• Automotive devices are devices where MCU failure or malfunction could lead to life-
threatening accidents. In water heaters and kitchen stoves, MCU failure or malfunction
poses a fire risk.
• In systems that impact human life or in applications where malfunction of electronic
control can cause serious accidents, an external WDT is required to ensure sufficient
redundancy.
REALTIME COLCK
Real time clock (RTC) is a clock that causes occurrences of regular interval interrupts on its
each tick(time out) .An interrupt service routine executes on each timeout (over flow) of this
clock. This timing device started never resets or is never reloaded with another value. Once it
is set, it is not modified later. The RTC is used in a system to save the current time and date.
The RTC is also used in a system to initiate return of control to the system (OS) after the pre-
set system clock periods.
 Used for synchronizing the operations of the OS kernel
 Can Interrupt OS kernel by asserting interrupt line of MP and MC to which RTC is
connected.
 OS identifies interms of IRQ number generated by the interrupt controller
 Then System time, date updating can be done.