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Digital Logic Design: Storage Components

The document discusses storage components in digital logic design, including registers, counters, and stacks, which are essential for constructing datapaths and controllers in modern processors. It covers the design and implementation of a one’s counter using a datapath with a 3 port register file, along with examples and state logic. Additionally, it outlines various control unit implementation styles and concludes with exercises for designing specific datapaths.

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0% found this document useful (0 votes)
9 views22 pages

Digital Logic Design: Storage Components

The document discusses storage components in digital logic design, including registers, counters, and stacks, which are essential for constructing datapaths and controllers in modern processors. It covers the design and implementation of a one’s counter using a datapath with a 3 port register file, along with examples and state logic. Additionally, it outlines various control unit implementation styles and concludes with exercises for designing specific datapaths.

Uploaded by

vmq552
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

1

DIGITAL LOGIC DESIGN


( CE_118 )

CHAPTER 2:
Storage Components
(part_2)
2

Storage components
➢ Storage components store data and perform some
simple operations.
➢ Storage components include:
o registers
o counters
o register files
o queues
o stacks
➢ Combinatorial and storage components are used for
construction of:
o datapaths
o controllers
➢ Main subsystems of modern processors and other
microchips.
3

Simple datapath with One accumulator


➢Datapath are used for temporary variable storage and
operation execution

ALU operations

Accumulator (SRwPL)
operations

Datapath schematic

Control word
4

Datapath with 3 port register-file

Datapath
ALU operations
schematic

Shifter operations
Control word
5

One’s-count algorithm
➢Example: One’s-counter implementation.

➢Problem: Using a datapath with a 3 port register file,


design a one’s counter that will count the number of ones in
an input dataword , and return the result after completion
6

Datapath with 3 port register-file

Datapath
ALU operations
schematic

Shifter operations
Control word
7

One’s-count algorithm

Repeated
while
Data ≠ 0

Control words for one’s counter


8

FSM representation of One’s-counter


➢State lasts for a clock cycle.
➢In each state the datapath executes the statement
indicated on its right side.

Sách sai tín hiệu Done


9

Next-state logic for One’s- counter


Q2(next) = Q2’Q1Q0 + Q2Q1’ + Q2Q0’
Q1(next) = Q1’Q0 + Q2’Q1Q0’ + (Data=0)Q1Q0’
Q0(next) = Q2’Q1Q0’ + Q2Q1’Q0’ + StartQ2’Q0’
+ (Data=0)Q2Q0’
Next-state equations
10

Output logic for One’s- counter controller

IE = Q’2Q’1Q0 RAA2= 0 RAB2= Q’1Q0 S2 = Q1 + Q0


S1= Q’2Q0
WA2= Q’1Q’0 RAA1= Q2Q0 RAB1= Q’1Q’0
S0= 1
WA1= Q2Q0+Q2Q’1 RAA0= Q2 RAB0= 0
Sh2= Sh1= Q2Q1Q’0

WA0= Q’1Q0+Q1Q’0 REA = Q2+Q1 REB = Q2+Q1Q’0 Sh0= 0


OE = Q2Q1Q0
WE = Q2Q’1+Q’2Q0+Q1Q0 Sách sai
11

Design model
12

One’s-counter
schematic

Mạch bị sai tại các dòng


màu xanh trong slide 10
13

General Datapath - Parallel datapath


➢Datapath allows 2 operations in each clock cycle.
➢Choice of operations performed simultaneously is limited.
14

An example of a custom datapath


➢Uses latches as temporary storage on the input and
output of functional units.
➢Latches allow shorter clock cycles and more concurrency.
15

Control-unit implementation styles


16

Control-unit implementation styles


17

Control-unit implementation styles


18

Control-unit implementation styles

Control unit with state-register, ROM and push-down stack


( microprogrammed control unit )
19

Chapter Summary
➢We introduced sequential components

o Simple (registers, counters)

o Storage (register-files, memories)

o Complex (stacks, queues, datapaths and control units)

➢Datapath and control units are used to implement

standard processors and application specific integrated


circuits (One’s count example)
20

Bài tập
➢Thiết kế datapath thực hiện công việc sau:
S=1+2+3+…+n
Với n là dữ liệu do người dung nhập vào
21

Bài tập
➢Thiết kế datapath thực hiện các công việc sau:
a. S = a0x0 + a1x1 + … + anxn
b. S = a0x0 + b0 + a1x1 + b1 + … + anxn + bn
Với các tham số
22

Bài tập
➢Thiết kế datapath thực hiện công việc sau:
o Cho 2 số A, B có độ dài 8 bit: A = a7a6a5a4a3a2a1a0; B =
b7b6b5b4b3b2b1b0
o Kết quả trả về C như sau: C = b7b6a3a2a1a0b1b0

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