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UVM Driver for Memory Transaction Control

The document outlines a hardware verification environment with constraints on memory addresses and data sizes, including a RAM space of 2KB and alignment requirements. It describes a property for monitoring data validity and a UVM driver class for managing transactions during simulation. The driver handles both read and write operations based on transaction validity and readiness signals.

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sivaji
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2 views2 pages

UVM Driver for Memory Transaction Control

The document outlines a hardware verification environment with constraints on memory addresses and data sizes, including a RAM space of 2KB and alignment requirements. It describes a property for monitoring data validity and a UVM driver class for managing transactions during simulation. The driver handles both read and write operations based on transaction validity and readiness signals.

Uploaded by

sivaji
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd

0011001100110011

1100110011001100

bit [15:0] array1

constraint c1 { array1 ==

RAM space : 2KB


4B algined
data can be 1KB, 64B, 128B
start address,
end address
rand bit[11:0] addr
rand bit [11:0] start_addr, end_addr;
rand int mem_size;

constraint c1 { addr inside [start_addr: end_addr];}


constraint c2 { addr[1:0] == 2'b0;}

property p1 @posedge clock

$rose (dvalid) -> ##[2:4] data[*2:4] ##[1:3] dack

endproperty

class tb_Driver extends uvm_driver

trasncation tx;
virtual task run_phase (uvm_phase pahse)
phase.raise_objection

seqitem_port.get_next_item

@(posedge clock)

if((!tx. write_read) & ([Link]) ) begin

@([Link]);
vif. address = tx.write_address;
vif. write_data = tx.write_data;
end

else if ( (tx. write_read) & ([Link]) begin

@([Link]);
vif. address = tx.read_address;

@(posedge clock)

tx.read_data= vif.read_data;
end

seqitem_port.item_done
phase.drop_objection

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