EE282: Computer Systems Architecture Problem Set
Stanford University Spring 2025 SOLUTION
Problem 5: Main Memory (24 points)
Adapted from H&P Chap. 2, Case Study 3, page 153.
A processor chip typically supports a few DDR3 or DDR4 memory channels. We will focus on a
single memory channel in this case study and explore how its performance and power are impacted
by varying several parameters. Recall that the memory channel is populated with one or more
DIMMs. Each DIMM supports one or more ranks – a rank is a collection of DRAM chips that
work in unison to service a single command issued by the memory controller. For example, a rank
may be composed of 16 DRAM chips, where each chip deals with a 4-bit input or output on every
channel clock edge. Each such chip is referred to as a →4 (by four) chip. In other examples, a rank
may be composed of eight →8 chips or four →16 chips – note that in each case, a rank can handle
data that are being placed on a 64-bit memory channel.
A rank is itself partitioned into 8 (DDR3) or 16 (DDR4) banks. Each bank has a row bu!er that
essentially remembers the last row read out of a bank. Here is an example of a typical sequence of
memory commands when performing a read from a bank:
(i) The memory controller issues a Precharge command to get the bank ready to access a new
row. The precharge is completed after time tRP (Row Precharge Time).
(ii) The memory controller then issues an Activate command to read the appropriate row out of
the bank. The activation is completed after time tRCD (RAS to CAS Delay) and the row is
deemed to be part of the row bu!er.
(iii) The memory controller can then issue a column-read or CAS command that places a specific
subset of the row bu!er on the memory channel. After time CL (CAS Latency), the first 64
bits of the data burst are placed on the memory channel. A burst typically includes eight
64-bit transfers on the memory channel, performed on the rising and falling edges of 4 memory
clock cycles (referred to as transfer time).
(iv) If the memory controller wants to then access data in a di!erent row of the bank, referred
to as a row bu!er miss, it repeats steps (i)—(iii). For now, we will assume that after CL has
elapsed, the Precharge in step (i) can be issued; in some cases, an additional delay must be
added, but we will ignore that delay here. If the memory controller wants to access another
block of data in the same row, referred to as a row bu!er hit, it simply issues another CAS
command. Two back-to-back CAS commands have to be separated by at least 4 cycles so that
the first data transfer is complete before the second data transfer can begin.
Note that a memory controller can issue commands to di!erent banks in successive cycles so that it
can perform many memory reads/writes in parallel and it is not sitting idle waiting for tRP, tRCD,
and CL to elapse in a single bank.
Exercise 1 (24 points)
Adapted from H&P exercise 2.8 – 2.13. For the subsequent questions, assume that tRP = tRCD =
CL = 24 ns, and that the memory channel frequency is 1 GHz (memory cycle = 1 ns), that is, a
transfer time of 4 ns (4 memory cycles).
a) (2 points) What is the read latency experienced by a memory controller on a row bu!er
miss? (Read latency is the time between the memory controller issuing the first command
and receiving the last bit of the data burst.)
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EE282: Computer Systems Architecture Problem Set
Stanford University Spring 2025 SOLUTION
Solution On a row bu!er miss, the time taken to retrieve eight 64-bit data burst (64-byte)
equals tRP + tRCD + CL+transfer time = 24 + 24 + 24 + 4 = 76 ns.
b) (2 points) What is the read latency experienced by a memory controller on a row bu!er hit?
Solution On a row bu!er hit, the latency equals CL+transfer time = 24 + 4 = 28 ns.
c) (3 points) If the memory channel supports only one bank and the access pattern has a
100% row bu!er miss rate, what is the utilization of the memory channel? Utilization is the
percentage of time used for data transfer.
Solution Each row bu!er miss involves steps (i)–(iii). Before a new read operation can start a
new Precharge command, it has to wait the Precharge, Activate, and CAS commands of the
previous read operation to be finished. Therefore, back-to-back read operations are separated
by tRP + tRCD + CL = 72 ns. Within this 72 ns, the memory channel is only occupied for 4 ns
transfer time. Therefore, the channel utilization is 4 / 72 ↑ 5.55%.
d) (3 points) Assuming a 100% row bu!er miss rate, what is the minimum number of banks that
the memory channel should support in order to achieve a 100% memory channel utilization?
Solution 18 banks. This answer can be arrived at by using the answer from the last question:
↓100% ÷ 5.55%↔ = 18. Or the memory controller should issue read operations every 4 ns to fill
the 72ns gap: ↓72 ÷ 4↔ = 18
e) (3 points) Assuming a 50% row bu!er miss rate, what is the minimum number of banks that
the memory channel should support in order to achieve a 100% memory channel utilization?
Solution 10 banks. If we assume accesses alternate between hits and misses, we can have the
following sequence (start from a row bu!er miss): Precharge begins at time 0; Activate starts
at time 24 ns; CAS starts at time 48 ns; the second CAS (a row bu!er hit) starts at time 52
ns; then another Precharge (a new row bu!er miss) begins at time 76 ns. We can issue a row
bu!er miss and a hit every 76 ns. Within this time, the channel is busy for 8 ns; the channel
utilization is 10.5%. We need ↓76 ÷ 8↔ = 10 banks to achieve 100% utilization.
Another way to solve this question is to think the average gap between back-to-back CAS
operation would be 72ns → 50% + 4 ns → 50% = 38 ns. Within this time, the channel is busy
for 4 ns; we need ↓38 ÷ 4↔ = 10 banks to achieve 100% utilization.
f ) (3 points) Assuming a 35% row bu!er miss rate, what is the minimum number of banks that
the memory channel should support in order to achieve a 100% memory channel utilization?
Solution 5 banks. The average gap between back-to-back CAS operation would be 72 ns
→ 35% + 4 ns → 65% = 27.8 ns. Within this time, the channel is busy for 4 ns; we need
↓27.8 ÷ 4↔ = 7 banks to achieve 100% utilization.
g) (4 points) Assume that we are executing an application with four threads and the threads
exhibit zero spatial locality, that is, a 100% row bu!er miss rate. Every 300 ns, each of the
four threads simultaneously inserts a read operation into the memory controller queue. What
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EE282: Computer Systems Architecture Problem Set
Stanford University Spring 2025 SOLUTION
is the average memory latency among four threads if the memory channel supports only one
bank?
Solution With a single bank, the first read operation would be finished at 76 ns. The second
would be finished at 76 + 72 = 148 ns. The third would be finished at 148 + 72 = 220 ns.
The last one would be finished at 220 + 72 = 292 ns. Hence, the average latency is (76 + 148
+ 220 + 292) / 4 = 184 ns.
h) (4 points) Assume the same setting as the preceding question. If we increase the number of
banks, will this application always benefit from having more banks? What is the minimum
average memory latency among four threads?
Solution This application can get benefit if requests went to di!erent banks. If all requests
are served by the same bank, adding more banks will not improve the latency. The minimum
average latency is achieved when requests went to four di!erent banks. The requests then
would be finished after 76 ns, 76 + 4 = 80 ns, 84 ns, and 88 ns. The minimum average latency
is (76 + 80 + 84 + 88) / 4 = 82 ns.
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